1 The MOS Transistor - unibo.itfranchi/Dida02/Processo_pre.pdf · 1 Adapted from J. Rabaey et al,...

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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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The MOS TransistorThe MOS Transistor

Polysilicon Aluminum


2CMOS Process CMOS Process attatt: non : non sonosono indicatiindicati i i contatticontatti di di substratosubstratoVVbulk,pbulk,p = 0 (= 0 (regioneregione p+)p+)VVbulk,nwellbulk,nwell = = VddVdd ((regioneregione n+)n+)

Field oxideThin oxide

2


3

Die and WaferDie and Wafer

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)


4

Patterning of SiOPatterning of SiO22

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

3


5

Circuit Under DesignCircuit Under Design

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2


6

Layout ViewLayout ViewArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

N-plus

4


7

Layout ViewLayout ViewArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

A

A

N-plus

area attiva and polygate

LIds

W


8

1) Area 1) Area attivaattivaArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

1

N-plusWn

Wp

5


9

2) n2) n--wellwellArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

2

N-plus


10

2b) p2b) p--wellwellArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well(2b)

N-plus

6


11

3) 3) polysiliciopolysilicio

Area attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

Ln

3

N-plus

Lp

Lp = Lp = Lmin


12

4) P4) P--plusplusArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

4N-plus

7


13

5) N5) N--plusplusArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

5 N-plus


14

6) 6) contatticontattiArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

N-plus6

8


15

7) 7) ConnessioniConnessioni in in metallometalloArea attiva

Polysilicio

Metallo

Contatti

P-plus

n-well

p-well

N-plus

7


16

CMOS Process WalkCMOS Process Walk--ThroughThrough

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

1 maschera: area attiva

9


17

CMOS Process WalkCMOS Process Walk--ThroughThroughSiO Field oxide2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

2 maschera: n-well

(2b maschera: p-well)


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(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

3 maschera: polisilicio

4 maschera: drogaggio p+

5 maschera: drogaggio n+

6 maschera: contatti

10


19


(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.

AlSiO2

7 maschera: metallo

maschere aggiuntive: via e livelli superiori di metallo


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Via

Mosfet

Contatto

(isolamento) trench

11


21VDD VDD

VinVout

M1

M2

M3

M4

Vout2

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

Metal1No !CORTOCIRCUITO

2 livello di metallo e viaOk !


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~0.7X Scaling

12


23

-30%1/S((Cg+Cd) Vdd)/ImaxTp

+40%S 1/Tp

1/S

1/S

1/U

S 21/S2

S/U

1/U

1/S

fattore di scala

-30%

-30%

-30%

+96%

-50%

campo costante

-30%

-30%

Areadie/WLnumero gate Ng

W Cox vsat(Vdd-Vtn)Imax (Isat)

WLarea

Cox W LCgate (Cg)

(esi/xj ) W ZCgiunzione (Cd)

Ecampo elettrico

Vdd (Vtn, Vtp)tensioni

W, L, tox, xjdimensioni lineari

espressioneparametro

Scaling a campo Scaling a campo elettricoelettrico costantecostante S =U≈1.4


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costanteS 2 / U2(1/Tp) Vdd2 (Cg+Cd)/(WL)densità di

potenza

(1/U)e (Vtn/nVth)(1-1/U)

1/(U2 S )

1/U2

1/U

1/S

fattore di scala

26 (*)cresce

-65%

-50%

-30%

-30%

Vdd Iss e (-Vtn/nVth)Potenza statica

(1/Tp) Vdd2 (Cg+Cd)Potenza dinamica

alla massima f

f Vdd2 (Cg +Cd)Potenza dinamica

a f fissata


W, L, tox, xjdimensionilineari


*Vtn=0.3 V, n=1, Vth = 25mV

13


25


26

-30%1/S((Cg+Cd) Vdd)/ImaxTp

+40%S1/Tp

1/S

1/S

1/U

S 21/ S 2S/U

1/U

1/ S

fattore di scala

-30%

-30%

-15%

+96%

-50%

aumenta

-15%

-30%

Areadie/WLnumero gate Ng

W Cox vsat(Vdd-Vtn)Imax (Isat)

WLarea

Cox W LCg

(esi/xj ) W ZCd

Ecampo elettrico


W, L, tox, xjdimensioni lineari


Scaling non a campo Scaling non a campo elettricoelettrico costantecostante S ≈1.4, U ≈1.18

14


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+40%cresce

S 2 / U2(1/Tp) Vdd2 (Cg+Cd)/(WL)densità di potenza

(1/U) e (Vtn/nVth)(1-1/U)

1/(U2 S )

1/U2

1/U

1/S

fattore di scala

5.2 (*)cresce

-50%

-30%

-30%

-30%

Vdd Iss e (-Vtn/nVth)Potenza statica

(1/Tp) Vdd2 (Cg+Cd)Potenza dinamica

alla massima f

f Vdd2 (Cg +Cd)Potenza dinamica

a f fissata


W, L, tox, xjdimensionilineari


*Vtn=0.3 V, n=1, Vth = 25mV


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Transistor CountsTransistor Counts

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium®

Pentium® Pro

K1 Billion 1 Billion

TransistorsTransistors

Source: IntelSource: Intel

ProjectedProjected

Pentium® IIPentium® III

Courtesy, Intel

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29

FrequencyFrequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel


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16


31

Power will be a major problemPower will be a major problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel


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33

Cost of Integrated CircuitsCost of Integrated Circuits

q NRE (non-recurrent engineering) costs§ design time and effort, mask generation§ one-time cost factor

q Recurrent costs§ silicon processing, packaging, test§ proportional to volume§ proportional to chip area


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costo IC = NRE/volume + (costo del die +costo del package + costo del collaudo)

costo del die = (costo lavorazione dellafetta)/(numero totale dei pezzi * resa )

cresce all’aumentare dell’area

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NRE Cost is IncreasingNRE Cost is Increasing


36

DefectsDefects

α is approximately 3

resa del die = f (area)-α

1 The MOS Transistor - unibo.itfranchi/Dida02/Processo_pre.pdf · 1 Adapted from J. Rabaey et al,...

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Transcript of 1 The MOS Transistor - unibo.itfranchi/Dida02/Processo_pre.pdf · 1 Adapted from J. Rabaey et al,...