Digital Control of a Boost PFC With SAB80C166 Microcontroller

November 1999 1Simone Buso - University of Padova - Lesson 6

LessonLesson 6 6

DigitalDigital Control of Control of a a Boost Boost PFC PFCwithwith SAB80C166 SAB80C166 Microcontroller Microcontroller


•• Developing a Developing a fully digital controlfully digital control for a for a boostboostpower factor power factor preregulatorpreregulator..

•• Exploiting the potentialities of digital control toExploiting the potentialities of digital control toimproveimprove the system’s the system’s dynamic performance.dynamic performance.

•• Keeping Keeping controller’s complexitycontroller’s complexity as as lowlow as aspossible so as to use a possible so as to use a standardstandard microcontroller microcontrollerfor the practical implementation.for the practical implementation.

Design GoalsDesign Goals


L D

S

CiL

Vo

Vg R

refVo

V'g

+

-

A/D Converter

PWM

X

+

-

Vo

+-

KV

-

+KI

iS

iS εI

Vε

gVo

V'g

δ

80C166 Cµ

L D

S

CiL

Vo

Vg R

refVo

V'g

+

-

A/D Converter

PWM

X

+

-

Vo

+-

KV

-

+KI

iS

iS εI

Vε

gVo

V'g

δ

80C166 Cµ

System StructureSystem Structure


Power Converter DesignPower Converter Design

Design Specifications:

• Input Voltage ……….............…….. Vg = 110 VRMS

• Output Voltage ….....................…. Vo = 200 V

• Nominal Output Power................…. Po = 200 W

• Switching Frequency …............….. fsw = 20 KHz

Design Specifications:Design Specifications:

•• Input Voltage ……….............……..Input Voltage ……….............…….. VVgg = 110 V = 110 VRMSRMS

•• Output Voltage ….....................….Output Voltage ….....................…. VVoo = 200 V = 200 V

•• Nominal Output Power................….Nominal Output Power................…. PPo o = 200 W = 200 W

•• Switching Frequency …............…..Switching Frequency …............….. ffswsw = 20 KHz = 20 KHz

Design Choice:

• Use of CCM and average current mode control

Design Choice:Design Choice:

•• Use of Use of CCMCCM and and average current modeaverage current mode control control


CC

iiinin

vvininRR

LL DD

SS VVoo

iidd

++

IIoo

IIoo


)(senV2v RMS,inin ϑϑ⋅⋅⋅⋅== )(senV2v RMS,inin ϑϑ⋅⋅⋅⋅== )(senI2i RMS,inin ϑϑ⋅⋅⋅⋅== )(senI2i RMS,inin ϑϑ⋅⋅⋅⋅==

oooo

RMS,inRMS,inin IVPP

IVP ⋅⋅==≅≅ηη

==⋅⋅== oooo

RMS,inRMS,inin IVPP

IVP ⋅⋅==≅≅ηη

==⋅⋅==

ti ⋅⋅ωω==ϑϑ ti ⋅⋅ωω==ϑϑ


)(senP2)(senIV2)(p 2o

2RMS,inRMS,inin ϑϑ⋅⋅⋅⋅==ϑϑ⋅⋅⋅⋅⋅⋅==ϑϑ )(senP2)(senIV2)(p 2

o2

RMS,inRMS,inin ϑϑ⋅⋅⋅⋅==ϑϑ⋅⋅⋅⋅⋅⋅==ϑϑ

)(iV)(p)(p dooin ϑϑ⋅⋅==ϑϑ==ϑϑ )(iV)(p)(p dooin ϑϑ⋅⋅==ϑϑ==ϑϑ

)(senI2)(senV

IV2)(i 2

o2

o

RMS,inRMS,ind ϑϑ⋅⋅⋅⋅==ϑϑ⋅⋅⋅⋅==ϑϑ )(senI2)(sen

V

IV2)(i 2

o2

o

RMS,inRMS,ind ϑϑ⋅⋅⋅⋅==ϑϑ⋅⋅⋅⋅==ϑϑ

•• The The power balance based equationspower balance based equations are totally are totallyindependentindependent on the PFC topology. on the PFC topology.

•• The The 100Hz (Europe) output ripple100Hz (Europe) output ripple is inherent in is inherent inthe PFC operation and the PFC operation and cannot be avoidedcannot be avoided without withoutdistorting the input current.distorting the input current.




•• The The input current equation,input current equation, in the Boost PFC in the Boost PFCtopology is used to topology is used to design the converter inductor.design the converter inductor.

A7.2V

P2II

RMS,in

omax,inmax,L ==

⋅⋅ηη⋅⋅

==== A7.2V

P2II

RMS,in

omax,inmax,L ==

⋅⋅ηη⋅⋅

==== Peak inputPeak inputcurrentcurrent

[[ ]]

T

td,

V

)(v1)(d

t)(vVt)(v

on

o

in

offinoonin

==ϑϑ

−−==ϑϑ

⋅⋅ϑϑ−−==⋅⋅ϑϑ [[ ]]

T

td,

V

)(v1)(d

t)(vVt)(v

on

o

in

offinoonin

==ϑϑ

−−==ϑϑ

⋅⋅ϑϑ−−==⋅⋅ϑϑ Voltage integralVoltage integralbalancebalance



)(dLf

)(vt

L

)(vi

s

inon

inL ϑϑ⋅⋅

⋅⋅ϑϑ

==⋅⋅ϑϑ

==∆∆ )(dLf

)(vt

L

)(vi

s

inon

inL ϑϑ⋅⋅

⋅⋅ϑϑ

==⋅⋅ϑϑ

==∆∆

A54.0I%20i max,Lmax,L==⋅⋅==∆∆ A54.0I%20i max,Lmax,L==⋅⋅==∆∆

Lf4

Vii

sw

o

2

VVmax, o

inLL ⋅⋅⋅⋅==∆∆==∆∆

== Lf4

Vii

sw

o

2

VVmax, o

inLL ⋅⋅⋅⋅==∆∆==∆∆

==

mH6.4if4

VL

max,Lsw

o ==∆∆⋅⋅⋅⋅

== mH6.4if4

VL

max,Lsw

o ==∆∆⋅⋅⋅⋅

==

InductorInductorcurrent ripplecurrent ripple

MaximumMaximumcurrent ripplecurrent ripple

Design choiceDesign choice

NeededNeededinductor valueinductor value


• The output current equation is used to designthe output capacitor.

•• The The output current output current equation is used to equation is used to designdesignthe output capacitor.the output capacitor.


CI

)2(senC2

1d)2cos(I

C1

Vin

o4

3

4in

43

4

oi

c ⋅⋅ωω==ϑϑ

⋅⋅ωω⋅⋅∫∫ −−==ϑϑϑϑ⋅⋅−−

⋅⋅ωω==∆∆

ππ

ππ

ππ

ππ CI

)2(senC2

1d)2cos(I

C1

Vin

o4

3

4in

43

4

oi

c ⋅⋅ωω==ϑϑ

⋅⋅ωω⋅⋅∫∫ −−==ϑϑϑϑ⋅⋅−−

⋅⋅ωω==∆∆

ππ

ππ

ππ

ππ

• The integration of the capacitive current(alternating part of the output current) over halfof the period, gives the peak to peak outputvoltage ripple. This depends on the loadcurrent and on the C value.

•• The integration of the The integration of the capacitive capacitive currentcurrent(alternating part of the output current) over (alternating part of the output current) over halfhalfof the period,of the period, gives the gives the peak to peak outputpeak to peak outputvoltage ripple.voltage ripple. This depends on the This depends on the loadloadcurrentcurrent and on the and on the C value.C value.


∆∆∆∆VVCC < 5% V < 5% Voo = 10 V = 10 V


• Imposing the voltage ripple to be:•• ImposingImposing the voltage ripple to be: the voltage ripple to be:

the minimum needed output capacitor value isfound:the minimum neededthe minimum needed output capacitor value output capacitor value isisfound:found:

F320V

IC

cin

o µµ==∆∆⋅⋅ωω

≥≥ F320V

IC

cin

o µµ==∆∆⋅⋅ωω

≥≥

F470C µµ== F470C µµ==



• Converter switch and diode can be selectedanalyzing the current and voltage stresses:

•• Converter Converter switch and diodeswitch and diode can be selected can be selectedanalyzing the analyzing the current and voltage stresses:current and voltage stresses:

VVDS DS > V> Vo,nomo,nom= 200 V= 200 V

A32

iI II max,L

maxL, maxD, maxS, ≅≅∆∆

++==== A32

iI II max,L

maxL, maxD, maxS, ≅≅∆∆

++====

Operating frequency > fOperating frequency > fswsw = 20 KHz = 20 KHz

NMOS BUZ60 NMOS BUZ60 RURD460RURD460

• A possible choice is the following:•• A A possiblepossible choice is the following: choice is the following:


Control SchemeControl SchemeLL DD

SS

CC

iiLL

VVOO

++

RR

RRssPWMPWM ModulatorModulator

11KvKv

voltagevoltageerror amplifiererror amplifier

sinusoidalsinusoidalreferencereference

VViiVVgg

11KoKo

PFC DIGITAL CONTROLLERPFC DIGITAL CONTROLLER

VcVcccii

x=x= ic ic

multipliermultiplier

VxVx

VrefVref

currentcurrenterror amplifiererror amplifier

K'vdK'vd PI - IPI - IKRKR

AADD

++zohzoh

AADD

AADD

KiDKiD

KoDKoD PI -VPI -V++

__

__KvdKvd

++


•• The control strategy The control strategy replicatesreplicates the standard the standardanalog control structure.analog control structure.

•• An inner An inner average current controlaverage current control loop is loop iscontrolled by an controlled by an outer voltage loop. outer voltage loop. The currentThe currenttemplate is given by thetemplate is given by the rectified input voltage. rectified input voltage.

•• Some Some refinementsrefinements are introduced exploiting the are introduced exploiting thepotentialities of the potentialities of the digital implementation:digital implementation:

•• soft-start;soft-start;

•• digital notch filter digital notch filter on the output voltageon the output voltagefeedback signal.feedback signal.

Control StrategyControl Strategy


Average Current Control DesignAverage Current Control Design

•• State space averagingState space averaging allows to calculate the allows to calculate thetransfer functionstransfer functions which are needed to design which are needed to designthe controllers. In the casethe controllers. In the case of theof the current loop,current loop,the analysis shows that:the analysis shows that:

dsL

Vi oL ⋅⋅≅≅ d

sL

Vi oL ⋅⋅≅≅

is, withis, with very good approximation, very good approximation, the transfer the transferfunction function ‘seen’ by the control system. ‘seen’ by the control system. TheThecurrent regulator can be designed current regulator can be designed as if the loadas if the loadwere purely inductive.were purely inductive.


KKRsRs rr

VVoosLsL

112V2Voscosc

ddee--sTsT /2 /2 ii

__

++ LL * *KKiiii

ssKKpipi++

vvxx++

++

11sLsL

vvinin

iiLLcc

•• Desired bandwidth: Desired bandwidth: 2 kHz.2 kHz.

•• Desired phase margin: Desired phase margin: 70°.70°.

•• Average current valueAverage current value (in CCM) is attained by (in CCM) is attained bysynchronizing PWM and samplingsynchronizing PWM and sampling processes. processes.



KKiiiiss

KKpipi ++

ffzizi

ffcici = 2 = 2 KHzKHz

TiTi ( (jjωωωω))

log (ωω)

VVoo

sLsL

KrKr

2 2 VVoscosc


H [dB] H [dB]

Asymptotic Bode DiagramAsymptotic Bode Diagram


1V2

KKR

L

V)j(T

osc

pirs

ci

oi ==

⋅⋅

⋅⋅⋅⋅⋅⋅

⋅⋅ωω==ωω 1

V2

KKR

L

V)j(T

osc

pirs

ci

oi ==

⋅⋅

⋅⋅⋅⋅⋅⋅

⋅⋅ωω==ωω

7.2KRV

LV2K

rso

cioscpi ==

⋅⋅⋅⋅⋅⋅ωω⋅⋅⋅⋅

== 7.2KRV

LV2K

rso

cioscpi ==

⋅⋅⋅⋅⋅⋅ωω⋅⋅⋅⋅

==


•• Proportional gainProportional gain is calculated imposing the is calculated imposing thedesired desired cross-over frequency.cross-over frequency.


ωω⋅⋅==

ωω⋅⋅++°°−−°°−−==ϕϕ

−−ϕϕ

−−

ii

cipi1

ii

cipi1i

K

Ktanm

K

Ktan9090

i

ωω⋅⋅==

ωω⋅⋅++°°−−°°−−==ϕϕ

−−ϕϕ

−−

ii

cipi1

ii

cipi1i

K

Ktanm

K

Ktan9090

i


•• Integral gain Integral gain is calculated imposing theis calculated imposing thedesireddesired phase-margin. phase-margin.

•• This has to beThis has to be over-sized over-sized to take into accountto take into accountthe holder delay.the holder delay.

°°==⋅⋅ωω

==∆∆−− ϕϕ 182

Tccizoh

°°==⋅⋅ωω

==∆∆−− ϕϕ 182

Tccizoh


(( )) (( ))i

cizi

i

cipiii mtan

ff;

mtan

KK

ϕϕϕϕ==

ωω⋅⋅== (( )) (( ))i

cizi

i

cipiii mtan

ff;

mtan

KK

ϕϕϕϕ==

ωω⋅⋅==

)s/rad(9087Kii ≅≅ )s/rad(9087Kii ≅≅

Hz535fzi ≅≅ Hz535fzi ≅≅


•• The The PI integral gainPI integral gain is calculated according to is calculated according tothe following equations:the following equations:



•• Due to the Due to the reduced current loop bandwidth,reduced current loop bandwidth, the theregulated current regulated current shows an unexpected behavior.shows an unexpected behavior.

•• It appears to be It appears to be phase-leadingphase-leading with respect to the with respect to theinput voltage,input voltage, from which the current reference is from which the current reference isextracted.extracted.

•• This is This is not desirablenot desirable because it negatively affects because it negatively affectsthe the system’s power factor.system’s power factor.

•• The The practical solutionpractical solution is to is to delay the currentdelay the currentreference,reference, to keep current and voltage in phase. to keep current and voltage in phase.

•• The The following analysis discusses the originfollowing analysis discusses the origin of the of theproblem.problem.


TheThe line current line current isisaboutabout 7° phase-7° phase-leadingleading thethe linelinevoltagevoltage

ig Vg2

3

1

[V]

- 2

- 1

- 3

120

180

60

- 120

- 60

- 180

[A]

[ms]

0 0

0 2010

ig Vg2

3

1

[V]

- 2

- 1

- 3

120

180

60

- 120

- 60

- 180

[A]

[ms]

0 0

0 2010

Input Current Phase DisplacementInput Current Phase Displacement


22

Lo

oL

1)1(

RL

sLCs

i)1(RV

CVs

ˆi

)s(Gδδ−−++++

⋅⋅δδ−−++++==

δδ==

22

Lo

oL

1)1(

RL

sLCs

i)1(RV

CVs

ˆi

)s(Gδδ−−++++

⋅⋅δδ−−++++==

δδ==

22g

L2

)1(RL

sLCs

R1

sC

Vi

)s(Gδδ−−++++

++====

22g

L2

)1(RL

sLCs

R1

sC

Vi

)s(Gδδ−−++++

++====


++

+- KKII(s)(s) G (s)G (s)11

22G (s)G (s)

εεεεii δδδδirefiirefref^

iLiiLL^

VgVVgg^

Current controlblock diagramCurrent controlCurrent controlblock diagramblock diagram


The closed-loop transferThe closed-loop transferfunctionfunction W(s)W(s) fromfrom linelinevoltagevoltage to to inductorinductorcurrentcurrent can be calculated can be calculatedfrom the from the previous blockprevious blockdiagram.diagram.

)s(K)s(G1

)s(K)s(G

i

i)s(W

I1

I1

ref

L1 ⋅⋅++

⋅⋅====

)s(K)s(G1

)s(K)s(G

i

i)s(W

I1

I1

ref

L1 ⋅⋅++

⋅⋅====

)s(K)s(G1

)s(G

V

i)s(W

I1

2

g

L2 ⋅⋅++

====)s(K)s(G1

)s(G

V

i)s(W

I1

2

g

L2 ⋅⋅++

====

)s(W)s(WgV

i)s(W 21V

g

LO

++⋅⋅==== )s(W)s(WgV

i)s(W 21V

g

LO

++⋅⋅====



2 3 4 5 6

11

22

33

44

55

66

77

88

99

[[degdeg]]

Bandwidth [kHz]Bandwidth [kHz]

75°75°

70°70°

60°60°

50°50°

1

mmφφ =

11 22 33 44 55 66

4040

5050

6060

7070

8080

[kHz][kHz]

[dB][dB]

BandwidthBandwidth

70°70°

60°60°

50°50°

75°75°mmφφφφ = =

Phase ShiftPhase Shift Current Loop GainCurrent Loop Gain



Analysis Final Results:Analysis Final Results:

•• thethe phase displacementphase displacement is is highhigh when the when thecurrent loop gaincurrent loop gain at the line frequency isat the line frequency islow.low.

•• thethe current loop gaincurrent loop gain at the line frequency isat the line frequency islowlow when when the phase marginthe phase margin isis highhigh or theor thebandwidthbandwidth isis low.low.

•• The The phase displacementphase displacement can be easily can be easilycorrected introducing a corrected introducing a delay linedelay line between betweenthe the reference generationreference generation and the and the currentcurrentloop.loop.




Implementation of the delay lineImplementation of the delay line

11

KvKv

sinusoidalsinusoidal

VVinin

ccii

x=x= ic ic

multipliermultiplierVVCC

VVXXK'vDK'vDAADD

referencereference

KvDKvD

Delay lineDelay line

delay = delay = mmcc ·T ·T



•• To To reducereduce the number of the number of data movesdata moves the line is the line isimplemented implemented using address pointers.using address pointers.

•• The The part of programpart of program which deals with the delay which deals with the delayline is line is the following:the following:

mov R0, #linemov R0, #line ; head of the line address; head of the line addressadd R0, #nadd R0, #nlineline ; end of line address; end of line addressmov [R1], ADDATmov [R1], ADDAT ; WRITE from A/D to k position; WRITE from A/D to k positionadd R1, #2add R1, #2 ; k ; k ⇒⇒⇒⇒ k+1 k+1cmp R1, R0cmp R1, R0 ; check if end of line; check if end of linejmp le, OKR jmp le, OKR ; conditional jump; conditional jumpmov R1, #linemov R1, #line ; if end of line, point the head; if end of line, point the head

OKR:OKR: mov R4, [R1]mov R4, [R1] ; READ from k+1 position; READ from k+1 position


•• Desired bandwidth: Desired bandwidth: 20Hz.20Hz.

•• Desired phase margin: Desired phase margin: > 70°.> 70°.

•• The The loop bandwidthloop bandwidth can be increased by can be increased by notch-notch-filteringfiltering the output voltage feedback signal to the output voltage feedback signal toeliminate the 100Hz ripple.eliminate the 100Hz ripple.

Output Voltage Control DesignOutput Voltage Control Design

KK iviv

ssKKpvpv ++

1+1+sCrsCrggcc

rrpp

pp

voltagevoltageerror amplifiererror amplifier

VVrefref

KK

++__

VVoovvcc

oo

11


•• The The design proceduredesign procedure for the voltage loop is for the voltage loop isessentially essentially the same used for the current loop.the same used for the current loop.

•• Also in this case the Also in this case the system’s transfer functionsystem’s transfer functionis given by is given by state-space averaging analysis.state-space averaging analysis.

•• Imposing the Imposing the cross-over frequency and phasecross-over frequency and phasemargin constraintsmargin constraints the PI gains can be the PI gains can becalculated. The calculated. The final resultsfinal results are: are:

Output Voltage Control DesignOutput Voltage Control Design

31.12Kg

CK o

c

cpv ==⋅⋅

⋅⋅ωω== 31.12K

g

CK o

c

cpv ==⋅⋅

⋅⋅ωω==

)s/rad(1289Kiv == )s/rad(1289Kiv == Hz17fzv ≅≅ Hz17fzv ≅≅


Discretization Discretization of the Controllersof the Controllers

•• Since the control Since the control bandwidths are sufficientlybandwidths are sufficientlylow,low, as compared to the as compared to the sampling frequency,sampling frequency, it itis possible to use a is possible to use a simple simple discretizationdiscretizationmethod,method, without an excessive frequency without an excessive frequencyresponse distortion.response distortion.

•• In this case In this case Euler Euler integration methodintegration method was used. was used.

•• This uses the following This uses the following Z-form, where Z-form, where TTcc is the is thesampling period:sampling period:

c

1

T

z1s

−−−−==

c

1

T

z1s

−−−−==


Discretization Discretization of the Controllersof the Controllers

•• It is worth noting that, It is worth noting that, in these conditionsin these conditions, the, theuse of use of different different discretization discretization techniques,techniques, such suchas the as the trapezoidal trapezoidal Z-form, only implies a Z-form, only implies a smallsmallvariation of the controllers’ gains.variation of the controllers’ gains.

•• It is also worth noting that the It is also worth noting that the rectangular (rectangular (EulerEuler))Z-form maintains the proportional gain and onlyZ-form maintains the proportional gain and onlymodifies the integral gainmodifies the integral gain (it is multiplied by (it is multiplied by TTcc).).

•• Finally, both the Finally, both the PI’sPI’s include include anti wind-up action,anti wind-up action,to improve the control behavior in case ofto improve the control behavior in case ofsaturation.saturation.


Voltage Loop Bandwidth ImprovementVoltage Loop Bandwidth Improvement

•• By means of a By means of a suitably designed digital notchsuitably designed digital notchfilterfilter it is possible to it is possible to eliminate the 100 Hzeliminate the 100 Hzcomponentcomponent from the from the voltage feedback signal.voltage feedback signal.

•• This allows to This allows to increase the voltage loopincrease the voltage loopbandwidth bandwidth without causing without causing additional distortionadditional distortionin the line current, in the line current, or to get aor to get a lower distortion if lower distortion ifthe same bandwidth is maintained.the same bandwidth is maintained.

•• In fact, the feedback signalIn fact, the feedback signal component, component, whosewhosecompensation compensation would imply would imply input currentinput currentdistortion distortion can be almost totallycan be almost totally removed. removed.


VVoo 11KoKo

++ 100 Hz100 Hz

AADD

Vref

__ vv

(2666h)

ee

notch filternotch filter low-passlow-pass

yy11 voltagevoltage

error amplifiererror amplifier

PI -VPI -Vyy22

VcVcKoDKoD

Implementation of output voltage notch filterImplementation of output voltage notch filter

Voltage Loop Bandwidth ImprovementVoltage Loop Bandwidth Improvement


22

11

211

v

1NOTCH

zaza1

zzb1

)z(E

)z(Y)z(H −−−−

−−−−

−−−−

++++==== 2

21

1

211

v

1NOTCH

zaza1

zzb1

)z(E

)z(Y)z(H −−−−

−−−−

−−−−

++++====

Notch Filter DesignNotch Filter Design

λλλλoo

zz

pp11

pp22

zz11

zz22

|H|HNOTCHNOTCH||

λλλλο ο ο ο = = = = ωωωωοοοο ··TTcc

11rr

ππππ λλλλ = ω = ω = ω = ω ··TTcc


•• With With r = 0.95r = 0.95 the following values can be found: the following values can be found:

bb11 = -1.99901 a = -1.99901 a11 = 1. 89906 a = 1. 89906 a22 = -0.9025 = -0.9025

22

o1

o1

ra

;)cos(r2a

;)cos(2b

−−==

λλ⋅⋅⋅⋅==

λλ⋅⋅−−==

22

o1

o1

ra

;)cos(r2a

;)cos(2b

−−==

λλ⋅⋅⋅⋅==

λλ⋅⋅−−==


•• The The filter coefficientsfilter coefficients can be designed as follows: can be designed as follows:


zz-1-1

zz-1-1

zz-1-1

zz-1-1aa22

bb11 aa11

44eevv''(k)(k) yy11(k)(k)

yy11(k-1)(k-1)

yy11(k-2)(k-2)

eevv(k-1)(k-1)

eevv(k)(k)

eevv(k-2)(k-2)

+ 5+ 5

- 5- 5

Notch Filter AlgorithmNotch Filter Algorithm

Implementation of output voltage notch filterImplementation of output voltage notch filter

)2k(e)1k(eb)k(e)2k(ya)1k(ya)k(y vv1v12111 −−++−−⋅⋅++++−−⋅⋅++−−⋅⋅== )2k(e)1k(eb)k(e)2k(ya)1k(ya)k(y vv1v12111 −−++−−⋅⋅++++−−⋅⋅++−−⋅⋅==



•• The The notch filter notch filter presentspresents some drawbacks: some drawbacks:

•• the the gain in the high frequencygain in the high frequency region is higher region is higherthan unity;than unity;

•• the filter the filter introduces a phase rotationintroduces a phase rotation which whichreduces the reduces the voltage loop phase margin.voltage loop phase margin.

•• CountermeasuresCountermeasures can be taken: can be taken:

•• compensatingcompensating the high frequency amplification the high frequency amplificationwith a with a low-pass filter;low-pass filter;

•• compensatingcompensating the phase rotation the phase rotation over-sizingover-sizingthe the voltage loop phase margin.voltage loop phase margin.


Low-Pass Filter DesignLow-Pass Filter Design

zz

aaz

|H|HLOW-PASSLOW-PASS||

λλλλ s λ =λ =λ =λ = ω ω ω ω⋅⋅⋅⋅TTcc

b/(1-a)b/(1-a)

ππππ

11

2LP

az1

b

)z(Y

)z(Y)z(H

−−−−====

11

2LP

az1

b

)z(Y

)z(Y)z(H

−−−−====


1571.0Tf2 css ==⋅⋅⋅⋅ππ⋅⋅==λλ 1571.0Tf2 css ==⋅⋅⋅⋅ππ⋅⋅==λλ


•• The The design of the low-pass filter can be done asdesign of the low-pass filter can be done asfollows:follows:

Normalized cut-offfrequency.Normalized Normalized cut-offcut-offfrequency.frequency.

8429.011

1a s

s==λλ−−≅≅

λλ++== 8429.01

1

1a s

s==λλ−−≅≅

λλ++==

1571.0a1b s ==λλ==−−== 1571.0a1b s ==λλ==−−==

To get desired cut-off frequency.To get desired To get desired cut-cut-off frequency.off frequency.

To get unity lowfrequency gain.To get To get unity lowunity lowfrequency gain.frequency gain.


zz-1-1aa

bbyy22(k)(k)

yy22(k-1)(k-1)

+ 5+ 5

- 5- 5

yy11(k)(k)

)k(yb)1k(ya)k(y 122 ⋅⋅++−−⋅⋅== )k(yb)1k(ya)k(y 122 ⋅⋅++−−⋅⋅==


•• The The implementation is implementation is the following:the following:

which corresponds to the following equation:which corresponds to the following equation:


INT ?INT ?INT ?

nonono

yesyesyes

start A/Dstart A/Dstart A/D

end A/Dend A/Dend A/D

Current RegulatorCurrent RegulatorCurrent Regulator

Current ReferenceCurrent ReferenceCurrent Reference

Notch Filter Notch Filter Notch Filter

PEC channel 0PEC channel 0PEC channel 0INITINITINIT int T0int T0

int CC1int CC1

int A/Dint A/D

11

22

33Voltage RegulatorVoltage RegulatorVoltage Regulator

+++

Flow chartof controlalgorithm

Flow chartFlow chartof controlof controlalgorithmalgorithm

Digital Control ImplementationDigital Control Implementation


Control TimingControl Timing


startstartA/DA/D

IsIs

EMPTYEMPTY

9.7 µs9.7 µs 9.7 µs9.7 µs 9.7 µs9.7 µs

10.410.4 µsµs

CurrentCurrent IIrefrefVoltage Voltage Loop Loop

5.5 µs5.5 µs 12 µs12 µs 7.2 µs7.2 µs

T = 50 µsT = 50 µscc

UgUg UoUo

tt

ttttonon/2/2

OutputOutput

Notch FilterNotch Filter

convertedconverted

switchswitchcommandcommand

variablevariable

LoopLoop VoltageVoltage


s252

ts6

s50ts11%100d%23

on

on

µµ<<<<µµ⇒⇒

µµ<<<<µµ⇒⇒<<<<

s252

ts6

s50ts11%100d%23

on

on

µµ<<<<µµ⇒⇒

µµ<<<<µµ⇒⇒<<<<


•• The program The program starts at the end of currentstarts at the end of currentconversion.conversion. With respect to the modulation With respect to the modulationperiod period the conversion can start after a variablethe conversion can start after a variabledelay,delay, depending on the duty cycle: depending on the duty cycle:

•• The The current control loop always ends within thecurrent control loop always ends within themodulation period,modulation period, so that the control delay is so that the control delay isminimum.minimum.



•• The other control tasks can extend in theThe other control tasks can extend in thefollowingfollowing modulation period.modulation period. Therefore, a Therefore, amodulation cycle delay has to be expected.modulation cycle delay has to be expected.

•• The external loop has a very The external loop has a very low bandwidth,low bandwidth, so sothe the delay is not critical.delay is not critical.

•• Since the Since the A/D conversion mode is continuous,A/D conversion mode is continuous,the only constraint is not to waste the only constraint is not to waste anyanyconverted value.converted value.

•• Additionally, Additionally, the total duration of the algorithmthe total duration of the algorithmmust be lower thanmust be lower than the modulation period. the modulation period.


end A/Dend A/DCUR_PI:CUR_PI:

CUR_REF:CUR_REF:

VOUT :VOUT :

intint A/D A/D

11jmpjmp [R15] [R15]movmov R15,#CUR_REF R15,#CUR_REF

22movmov R15,#VOUT R15,#VOUT

33 movmov R15,#CUR_PI R15,#CUR_PI

Handling of the interrupt routinesHandling of the interrupt routines



RectifiedRectifiedvoltagevoltageandandconverterconverterinputinputcurrentcurrent

ExperimentalExperimental MeasurementsMeasurements

V'g

iL

[V]

0

33

66

99

132

165

[A]

0

1

2

3

V'g

iL

[V]

0

33

66

99

132

165

[A]

0

1

2

3


withoutwithout notch filter notch filter withwith notch filter notch filter


1

2

3

4

- 1

- 2

i g

Vg

60

120

- 60

- 120

- 180

- 240

[A] [V]

0 2 4 6 8 10 12 14 16 18 20[ms]

0

0

1

2

3

4

- 1

- 2

i g

Vg

60

120

- 60

- 120

- 180

- 240

[A] [V]

0 2 4 6 8 10 12 14 16 18 20[ms]

0

0

1

2

3

4

- 1

- 2

i g

Vg60

120

- 60

- 120

- 180

- 240

[A] [V]

0 2 4 6 8 10 12 14 16 18 20[ms]

0

0

1

2

3

4

- 1

- 2

i g

Vg60

120

- 60

- 120

- 180

- 240

[A] [V]

0 2 4 6 8 10 12 14 16 18 20[ms]

0

0


0 50 100 150 200 250 300 350 400 450 500[Hz]

withNOTCH filter

without

NOTCH filter

0

- 20

- 40

- 60

0

- 20

- 40

- 60

20 [dB]

0 50 100 150 200 250 300 350 400 450 500[Hz]

withNOTCH filter

without

NOTCH filter

0

- 20

- 40

- 60

0

- 20

- 40

- 60

20 [dB]

Line current spectraLine current spectra



[V]

0

70

140

210

0

2

4

[A]

Vo

iL

[V]

0

70

140

210

0

2

4

[A]

Vo

iL

ConverterConverterdynamicdynamicresponseresponsewithoutwithoutnotch filternotch filter



0

70

140

210

0

2

4

[V] [A]

Vo

iL

0

70

140

210

0

2

4

[V] [A]

Vo

iL

ConverterConverterdynamicdynamicresponseresponsewithwithnotch filternotch filter



200

150

100

Vo

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1[s]

2

0

-2

i g

tsoft-start

[A]

[V]200

150

100

Vo

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1[s]

2

0

-2

i g

tsoft-start

[A]

[V]

Soft-startSoft-startprocedureprocedure



ReferencesReferences

[1][1] P. F.P. F. Kocybik Kocybik, K. N., K. N. Bateson Bateson, , "Digital Control of a ZVS Full-Bridge"Digital Control of a ZVS Full-BridgeDC-DC Converter",DC-DC Converter", APEC APEC Conf Conf.. Proc Proc., 1995, pp. 687-693.., 1995, pp. 687-693.

[2][2] W. C. So, C. K.W. C. So, C. K. Tse Tse, Y. S. Lee, , Y. S. Lee, "An Experimental Fuzzy Controller"An Experimental Fuzzy Controllerfor DC-DC Converters",for DC-DC Converters", PESC PESC Conf Conf.. Proc Proc., 1995, pp. 1339-1345.., 1995, pp. 1339-1345.

[3][3] C.C. Zhou Zhou, M. M., M. M. Jovanovic Jovanovic, , "Design Trade-"Design Trade-OffsOffs in Continuous in ContinuousCurrent-Mode Controlled Boost Power-Factor-Correction Circuits",Current-Mode Controlled Boost Power-Factor-Correction Circuits",HFPCHFPC Conf Conf.. Proc Proc., 1992, pp. 209-220.., 1992, pp. 209-220.

[4][4] R. B.R. B. Ridley Ridley, , "Average Small-Signal Analysis of the Boost Power-"Average Small-Signal Analysis of the Boost Power-Factor-Correction Circuit",Factor-Correction Circuit", VPEC Seminar VPEC Seminar Proc Proc., 1989, pp. 108-120.., 1989, pp. 108-120.

[5][5] J. B. Williams, J. B. Williams, "Design of Feedback Loop in Unity Power Factor AC"Design of Feedback Loop in Unity Power Factor ACto DC Converter",to DC Converter", PESC PESC Conf Conf.. Proc Proc., 1989, pp. 959-967.., 1989, pp. 959-967.

[6][6] G.G. Spiazzi Spiazzi, P., P. Mattavelli Mattavelli, L., L. Rossetto Rossetto, , "Methods to Improve"Methods to ImproveDynamic Response of Power FactorDynamic Response of Power Factor Preregulators Preregulators: an Overview",: an Overview",European Power ElectronicsEuropean Power Electronics Conf Conf. (EPE),. (EPE), Sevilla Sevilla (Spain), (Spain),September 1995,September 1995, Vol Vol.3, pp.754-759..3, pp.754-759.

Digital Control of a Boost PFC With SAB80C166 Microcontroller

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