Boost PFC preregulator Design

7/29/2019 Boost PFC preregulator Design

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Reference DesignSLUA269 - July 2002

1

UCC3819 250-W Power Factor Corrected (PFC) BoostFollower Preregulator Design

Michael OLoughlin System Power

ABSTRACT

This paper reviews the benefits of a boost follower topology and the design of a 250-W PFCboost follower preregulator.

Contents

1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Power Stage Design 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 VAI Output Sensing Circuit with Clamp 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Slower Voltage Loop Small Signal Transient Response at High Line 11. . . . . . . . . . . . . . . . . . . .

5 Reference Design Performance Curves 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 References 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

Conventionally PFC off-line power converters are designed with two power stages. The firststage is typically a boost converter. This is because the boost converter topology has continuous

input current that can be shaped through the use of a multiplier and average current modecontrol to achieve near-unity power factor (PF). However the boost converter requires a higheroutput voltage than the input and requires a second converter to step this voltage down to auseable level.

The boost converter is traditionally designed to have a fixed output voltage greater than themaximum peak line voltage. However, the boost voltage does not have to be well regulated orfixed because the step down converter can be designed to handle the variations in voltage. Aslong as the boost voltage is above the peak input voltage the converter will regulate properly.There are actually some benefits that can be gained by having the boost voltage vary withvariations in peak line voltage (i.e. boost follower preregulator). One is reduced inductor size andthe other is lower switch loss at low line operation. This paper reviews the benefits of a boost

follower topology and the design of a 250-W PFC boost follower preregulator.

NOTE: The reference design was generated using typical parameters rather than worst-casevalues. Please refer to the table in Figure 1 and Figure 2 for design specifications andcomponent placement. Refer to Table 1 for all variable definitions.

Trademarks are the property of their respective owners.


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2 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design

VOUTVLINE

85 VACTO

265 VAC

UDG02075

+

PFC

CONTROLLER

PWM

CONTROLLER

STAGE 1 STAGE 2

Figure 1. Functional Block Diagram

Table 1. Design Specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VIN Input offset voltage 85 265 VRMS

fIN Input frequency 60 Hz

VIN = 85 VRMS 195 205 215VOUT dc Output voltage VIN = 265 VRMS 370 390 410

V

POUT Output power 0 250 W

VRIPPLE Output voltage ripple VIN = 85 VRMS 3%

Efficiency POUT = 250 W 93%

VIN = 85 VRMS, POUT = 250 W 5%THD Total harmonic distortion

VIN = 265 VRMS, POUT = 250 W 7%

fOSC Operating frequency 100 kHz

tHOLDUP Hold-up time 16.7 ms

VOVP Overvoltage protection threshold voltage VOUT = 400 V 409 416 422 V

PLIM Power limit VIN = 85 VRMS 275 360 385 W

ILIM Peak current limit 5.335 5.500 5.665 A


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3UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design

+

+

Figure 2. Reference Design Schematic


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Table 2. Variable Definitions

VARIABLE DEFINITIONS

CDIODE Boost diode capacitance

COSS FET Drain to source capacitance

GVEA

Gain of the voltage amplifier

D Duty cycle

fS PWM switching frequency

GPID Control to output gain of the current loop at the desired crossover frequency

GPID (f) Control to output gain of the current loop

GPS(f) Voltage loop control to output gain

IMO_MAX(high_line) Peak IMO current at high-line input

IRMS_DIODE Boost diode current

IRMS_FET RMS current in the FET

IRMS_L RMS inductor current

Osc_Amplitude Typical oscillator ramp amplitude

PSEMI Power dissipated by a semiconductor device

PCON_FET Conduction losses in the FET

PCOND_DIODE Diode conduction losses

PCOSS Power dissipated by the FETs drain to source capacitance

PDIODE Total loss in the boost diode

PDIODE_CAP Loss due to boost diode capacitance

PDIODE_TR Boost diode transition loss

PFET_TR FET transition losses

PGATE Power dissipated by the FET gate

POUT Maximum output power

PQ1 Total FET losses

QGATE FET gate charge

RDS(on) On resistance of the FET

RCS Thermal impedance case to sink

RJC Thermal impedance junction to case

RSA Thermal impedance sink to air

TA Ambient temperature

tHOLDUP Boost capacitor holdup time

TJ(max) Maximum semiconductor temperature

tF FET fall time

tR FET rise time

tRR Reverse recover time for a boost diode

TS(f) Voltage loop frequency response

VAI(max) Maximum voltage amplifier referenceVAI(min) Minimum voltage amplifier reference voltage

VCLAMP Voltage reference clamp to ensure the boost voltage is not exceeded

VEA(max) Maximum voltage amplifier output.

VEA(min) Minimum voltage amplifier output

VGATE Gate drive voltage

VDROP Amount of voltage the boost capacitor is allowed to drop during holdup.

VIN(max) Maximum RMS input voltage


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VARIABLE DEFINITIONS

VIN(min) Minimum RMS input voltage

VOUT(max) Maximum dc output voltage

VOUT(min) Minimum dc output voltage

VPP Output peak-to-peak ripple voltage

VREF_TL431 Reference voltage of the TL431

I Change in boost inductor ripple current

Efficiency

%THD Percentage of allowable total harmonic distortion

2 Power Stage Design

2.1 Inductor Selection

The boost inductor is selected based on the maximum allowed ripple current at maximum dutycycle at the peak of minimum line voltage. The following equations can be used to calculate the

required inductor for the power stage with ripple current that is 20% of the peak input current.The calculated inductance for this design was roughly 570 H. In traditional application theboost voltage (VOUT(min)) would be fixed at roughly 390 V. For the same power levels and inputconditions for the traditional boost converter would require and inductance of roughly 1 mH. Tomake the design process easier the inductor was designed by Cooper Electronics.

DI +POUT 2

0.2VIN (min)

D + 1*VOUT (min)* VIN (min) 2

VOUT (min)

L1 + VIN (min) 2 D

DI fS

2.2 Boost Switch Selection (D1) and Boost Diode Selection (Q1)

To properly select D1 and Q1 a power budget is generally set for these devices to maintain thedesired efficiency goal. Equations (4), (5), and (6) are used to estimate power loss in theswitching devices. To meet the power budget for this design an IRFP450 HEX FET andHFA08TB60 fast recovery diode from International Rectifier were chosen for this design to meetthe power constraints.

To calculate the loss in Q1:

IRMS_FET +POUT

VIN (min) 2 2*

16 VIN(min) 2

3 p VOUT(min) IRMS_L + POUTVOUT (min)

PGATE + QGATE VGATE fS

PCOSS +12

COSS VOUT(min)2

fS

(1)

(2)

(3)

(4)

(5)

(6)


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PCOND_FET + RDS(on) IRMS_FET2

PFET_TR +12

VOUT(min) IRMS_L 0.9 tR ) tF fS

PQ1 +

PGATE)

PCOSS)

PCOND_FET)

PFET_TR

To calculate the loss in D1:

IRMS_DIODE +POUT

VOUT (min)

16 VOUT(min)

3 p VIN(min) 2

PCOND_DIODE + VF IRMS_DIODE

PDIODE_CAP +CDIODE

2 VOUT(min)

2

fS

PDIODE_TR +

1

2V

OUT(min)IRMS_DIODE

tRR

fS

PDIODE + PCOND_DIODE) PDIODE_CAP) PCOND_TR

2.3 Benefits of the Boost Follower Topology on the Power Stage at Low-Line

The more traditional PFC preregulator topology has a fixed output voltage that is greater thanthe peak line voltage. The fixed boost voltage for a universal input is typically set at 390 V. Theboost follower is designed so that the output voltage is greater than the peak input voltage. Forthis design the output tracks the input from 206 V to 390 V. From the equations for transitionloss and capacitance loss for the boost switch (Q1), it can be observed that these losses shouldbe less at lower line voltages for the boost follower topology as compared to the traditional

preregulator. The calculated losses for Q1 and D1 in the traditional topology were approximately25 W and the calculated losses for switch and diode for the boost follower was approximately17.4 W. The boost follower topology should be at least 3% more efficient at low line than thetraditional topology. When compared to that of a traditional converter with the same powerlevels, the finished converters low-line efficiency is approximately 5% more efficient. (SeeFigure 3.)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)


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EFFICIENCYvs

OUTPUT POWER

Figure 3.

Efficiency

(%)

POUT Output Power W25 50 75 100 125 150 175 200 225 250

82

84

86

88

96

90

92

94

98

100

85 VRMSof Boost-Follower PFC

85 VRMSof Traditional PFC

2.4 Heat Sinks

Equation (15) calculates the minimum required thermal impedances of the heat sinks (RSA)required for this design. The heat sinks are designed to ensure that the junction tempature staysbelow 75% of the rated maximum. The heat sinks require a fan capable of forcing 40C air at150 LFPM. The heat sink required for Q1 using the traditional topology required an AVVID heatsink part number 53002 that is approximately 4.125 cubic inches. The heat sink for the boost

follower topology required an AVVID heat sink part number 531202 of approximately 1.38 cubicinches which is about 66% smaller than the heat sink used in the traditional design.

RqSA +TJ(max)* TA * PSEMI RqCS)RqJC

PSEMI

2.5 Holdup Capacitor Selection

Equation (16) is used to estimate the size of the hold-up capacitor and the maximum allowableRMS current through the boost capacitor. The hold-up capacitor was designed for 16.7 ms of

holdup time (tHOLDUP) allowing the output 85 V of drop (VDROP). For this design the calculatedminimum hold-up capacitance was approximately 330 F requiring roughly 1.7 A of RMS currentat low-line operation. This minimum calculated capacitance value is roughly double of what isrequired in the traditional design. This is one of the negative aspects of using a boost followertopology.

C12 w 2 POUTtHOLDUP

VOUT(min)2

* VOUT(min)* VDROP2

(15)

(16)


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IRMS_C12 +POUT

VOUT (min)

16 VOUT(min)

3 p VIN(min) 2 * 1

2.6 Multiplier Setup

The multiplier is used to shape the input current waveform and must be set up correctly to getproper PFC. Equations (18) and (19) are used to set up the multiplier.

R13)R21 +VIN(max) 2

500 mA

R6 + 1.4 VVIN(min)

R13)R212 0.9

Three voltage signals in this circuit, having a 120-Hz ripple component, contribute to input

current total harmonic distortion (THD). The voltage feedforward (VFF) of the multiplier is onethat contribute to THD. To meet the design goal of less than 5% THD, each signal is allowed tocontribute only 1.5% allowable 120-Hz distortion (%THD). To meet the current THDrequirements, C6 is set to attenuate the 120-Hz voltage ripple present on the VFF input of themultiplier to 1.5% (%THD) of the VFF pins voltage range.

C6 + 12 p%THD

66% 120 HzR6

2.7 Peak Current Limit

The UCC3819 has a peak current limit comparator that can be set up with a voltage divider

using the VREF pin of the PWM controller. R14, R12 and R11 are selected to have the peaklimit comparator trip at 110% of the maximum output power to protect Q1. This comparator limitsonly the current through the switch and not the current drawn by the output.

(17)

(18)

(19)

(20)


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2.8 Power Limiting

Resistor R9 is selected to achieve soft power limiting at maximum output power[1].

R9 +

POUT 2

hVIN(max) R14

IMO_MAX(high_line) , R9+ R10

2.9 Current Amplifier

Equations (22) and (23) are used to compensate the current loop with a desired crossoverfrequency at 1/10 of the switching frequency. Resistor R8 and capacitor C9 form a zero at thedesired crossover frequency that gives an added 45 degrees of phase margin for circuit stability.Capacitor C8 and and resistor R8 form a high-frequency pole to attenuate any high-frequencynoise that may be present in the system.

GPID +VOUT(max) R14

2 p fS10 L1 Osc_AmplitudeR8 + 1

GPID, C9 + 1

2 p fS10R8

, C8 + 1

2 p fS2 R8

3 VAI Input Sensing Circuit with Clamp

The UCC3819 PWM controller allows the user to set the reference voltage (VAI) externally. It isthis feature that allows the designer to use an integrated PWM controller with a boost follower

topology. With a few external components, a circuit can be constructed that sets VAI proportionalto the input voltage. This reference voltage is then used to make the output voltage track theinput voltage. Figure 4 shows the external components that are required to generate the VAIvoltage.

(21)

(22)

(23)


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VCC

VREC

1

2

3

4

8

7

6

5

U2

OP07

C19

33 pF

C18

C160.01 F

C174.7 F

R3322.1 k

R32499 k

R31499 k

R34432

VFF

R353.3 k

R362 k

UDG02076

1 F

D13TLV431CLP

Figure 4. VAI Output Sensing Schematic

R31, R32, R33 and C17 form a voltage divider with a single-pole filter that is used to monitor theline voltage. R35, R36, and D13 form a VAI clamp to ensure the boost voltage does not exceedthe design specification of 390 V. Equations (24) and (25) can be used to select the propercomponents for the circuit.

VAI(min) +VAI(max)

2

R33 +

VAI(min) (R31)R32)

VIN(min) 0.9* VAI(min)

The VAI signal includes a 120-Hz component that can contribute to THD. Capacitor C17 isselected to keep its contribution to less than 1.5% THD.

C17 + 1

2 pVAI(max)%THD

VIN(max) 2 66%

120 Hz R33

Setting up the clamp voltage requires that the divider to the VSENSE pin be set up first.

R3 +V

AI(min)(R19

)R2)

VOUT(min)* VAI(min)

VCLAMP +VOUT(max)R3

R19)R29)R3

R35 +VCLAMP* VREF_TL431R36

VREF_TL431

(24)

(25)

(26)

(27)

(28)

(29)


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3.1 Voltage Amplifier

The voltage amplifier is compensated to attenuate the 120-Hz boost-ripple voltage (VPP) in orderto reduce its contribution to THD.

VPP +

POUTh

p 120 HzC12 VOUT(min)

GVEA +%THD VEA(max)* VEA(min)

VPP 100

C8 + 12 p 120 HzGVEAR9

fC +POUT

VEA(max)* VEA(min) VOUT(min) 2 pC12 1

2 pR9C8R8 + 1

2 p fS10C8

4 Slower Voltage Loop Small Signal Transient Response at High Line

Another drawback to using a boost follower topology is the small signal transient response isslower at lower line voltages. Equations (35) through (38) model the voltage loop frequencyresponse of both a boost follower and traditional PFC offline voltage regulator. These equationsdescribe the power stage gain (G

PS(f)) as inversely proportional to output voltage. In the

boost-follower topology the voltage loop is compensated when the boost voltage is at its lowestto ensure circuit stability. As the input voltage increases, VOUT increases, which decreases theoverall loop gain (TS(f)). As TS(f) decreases the loop crosses over at a lower fC, resulting inslower transient response. The traditional topology has a fixed output voltage and a fixed TS(f),which results in a fixed transient response, independent of line voltage.

s(f) +j 2 p f

GPS(f) +POUT

VEA(max)* VEA(min) VOUT s(f)C12

GEA(f) +(s(f)R8C9) 1

)

S(f)R9 (C9) C8) S(f)R8 C9C8C9)C8) 1Ts(f) +*GPS(f)GEA(f)

Figures 5 and 6 show the measured voltage loop small-signal frequency response. The smallsignal transient response at low line is roughly twice as fast as it is at high line.

(30)

(31)

(32)

(33)

(34)

(35)

(36)

(37)

(38)


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50

40

30

20

10

0

10

20

30

40

50

1 1060

40

20

0

40

60

80

100

120

140

20

100

G

Gain

(dB)

f Frequency Hz

Phase

(_)

Phase

Gain

Figure 5. Voltage Loop Low-Line Frequency Response at Maximum Load

G

Ga

in

(dB)

f Frequency Hz

Phase

(_)

1 1050

40

30

20

10

0

10

20

30

40

50

10060

40

20

0

40

60

80

100

Phase

Gain

Figure 6. Voltage Loop High-Line Frequency Response at Maximum Load


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5 Reference Design Performance Curves

The following graphs show the performance of the reference design.

TOTAL HARMONIC DISTORTION (THD)vs

OUTPUT POWER

Figure 7.

THDTotalHarmonicDistortion

(%)

POUT Output Power W

250

1

2

3

4

5

6

7

8

9

10

50 75 100 125 150 175 200 225 250

VRMS= 265

VRMS= 120 VRMS= 85

82

84

86

88

96

90

92

94

98

100

25 50 75 100 125 150 175 200 225 250

Figure 8.

EFFICIENCYvs

OUTPUT POWER

POUT Output Power W

Efficiency

(%)

VRMS= 265VRMS= 85

VRMS= 120

POWER FACTORvs

OUTPUT POWER

Figure 9.

PF

PowerFactor

(%)

POUT Output Power W

25 50 100 125 150 175 200 22575 25040

50

60

70

80

90

100

VRMS= 265

VRMS= 85

VRMS= 120


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LOW-LINE OPERATION

Figure 10.

t Time 5 ms / div

VIN=85 VPOUT= 25 W

Input Current(500 mA / div)

Rectified Line Voltage(100 V / div)

Figure 11.

LOW-LINE OPERATION

VIN=85 VPOUT= 250 W

t Time 5 ms / div

Input Current(5 A / div)


HIGH-LINE OPERATION

Figure 12.

t Time 5 ms / div

VIN=265 VPOUT= 25 W


Input Current(200 mA / div)

Figure 13.

HIGH-LINE OPERATION

VIN=265 VPOUT= 25 W

t Time 5 ms / div

Input Current(2 A / div)

Rectified Line Voltage

(100 V / div)


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6 References1. Laszlo Balogh, UCC3854A/B and UCC3855A/B Provide Power Limiting With Sinusoidal Input

Current, Texas Instruments Literature No. SLUA196.

2. Lloyd Dixon, High Power Factor Switching Prergulator Design Optimization, Unitrode PowerSupply Design Seminar SEM700, 1990, Topic 7, Texas Instruments Literature No. SLUP093.

3. POWER CONVERSION, September 1992 Proceedings, (LIST PUBLICATION HERE) p. 67

4. Practical Considerations in Current Mode Power Supplies, Application Note, Texas InstrumentsLiterature No. SLUA110.


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Boost PFC preregulator Design

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