PETER DELOS

Technical Lead

Aerospace and Defense Applications Group

Greensboro NC

Digital Beamforming Techniques

for Phased Array Systems

101/25/2017

Topics

►Historical Perspective

►Phased Array Overview

Block Diagram

Antenna Pattern

Benefits / Challenges

Element Spacing

►Front End Subsystems

T/R Modules

Analog Beamformers

2

►Cascaded Analysis Noise Figure

Third Order Intercept

Phase Noise

►Receiver Architectures

Heterodyne

Direct Conversion

Direct Sampling

►Calibration

►References

Phased Array Concept

► An array of antenna elements where the relative phase of each element is varied

► Effective radiation pattern is constructively reinforced in the desired direction (main lobe)

and suppressed in undesired directions (side lobes)

► Allows the radar to

concentrate energy in

one place and maintain

stealth elsewhere.

3

Analog vs Digital Beamforming

Analog Beamforming Systems: Legacy, Limited flexibility

Digital Beamforming Systems: Emerging, Most flexible

Challenged by SWaP (Size, Weight, and Power)

Digital processing of all data requires significant power

Difficult to implement close to the antenna

Many systems use a mix (Sub-Arrayed Architecture)

Analog Sub-arrays with reduced digital channels and digital beamforming

Digital Beamforming

Distributed Receivers

Analog Beamforming

Centralized Receiver

4

Phased Array Radar System Evolution

► Analog Beamforming or

Mechanical Scanning

► Centralized Receivers & Exciters

► Low electronics content:

► Sub-array Architecture

► Analog/Digital Beamforming

► Distributed Receivers & Exciters

► At Subarray Level

► Every Element Digital Beamforming

► No Analog Beamforming

► Distributed Receivers & Exciters

► At a per element level

Classical Hybrid Solution All Digital

5

Generic Digital Beamforming Phased Array Signal Flow

6

Digital Beamforming Converters

Analog Up/Down

Conversion Analog BeamformingT/R

ModulesAntenna Elements

1 : Number of Elements

DigitalUp/Down

Conversion

LO

LO

D/A

A/D

D/A

A/D

NCO

NCO

EQ

EQ

EQ

EQ

Bea

m D

ata

1 : Number of Channels

1 : Number of BeamsChannels ofNumber

Elements ofNumber :1

Waveform Generator and Receiver Channels

Digitally Beamformed Antenna Patterns

Key Points

►Three Beam Patterns to Consider

Element Pattern

Subarray Pattern

Digitally Beamformed Pattern

►Subarray Pattern Limitations

Antenna gain for interference outside of

digitally beamformed pattern

Directional diversity of multiple digitally

beamformed patterns Element

Pattern

Subarray

Pattern

Digitally

Beamformed

Pattern

Angle

An

ten

na

Ga

in

7

Digital Beamforming : Benefits / Challenges

►Benefits

Most flexible, programmable

system

Many simultaneous beam

patterns possible

Adaptive antenna pattern

programming possible

Noise improvement from

combining distributed waveform

generator and receivers

8

►Challenges Synchronization / Calibration of

many waveform generator and receiver channels Power up Synchronization

Channel to Channel drift

LO / Clock Distribution

DC Power Distribution

SWAP-C associated with thewaveform generator and receiver designs More difficult at higher frequency

operating bands

Processing large volume of digital data

Channel Footprint Considerations

► Element Spacing

Max spacing at λ/2 -> As operating frequency ↑, channel spacing ↓

Reduced based on scan angles and sidelobe objectives

Reduced to account for mechanical structure

Reduced in half for a dual pole system

► Analog Beamforming Impact

Transmit Receive Module size allocations typically unchanged

Waveform Generator, Receiver, and Processor Quantity Reduced

Footprint allocation relaxed

Performance requirements may become more stressing

► Dilated Array:

Electronics wider than the Antenna face

Method to increase volume for system electronics

Reduces Scalability

9

Basic Radar Transmit & Receive Module (TRM) Diagram

► TRM

► Combines PA, LNA, TR Switch and

potentially Phase / Gain control

► Highly integrated solution

10

Functional Block Diagram

Example Front End Integrated Approach

Analog Beamforming Topologies

11

Analog Beamformer 1

Analog Beamformer M

Element 1

Element N

Subarray Beam 1

Subarray Beam M

FromElement 1

FromElement N

FromElement 1

FromElement N

To AnalogBeamformer 1

To AnalogBeamformer M

To AnalogBeamformer 1

To AnalogBeamformer M

Generic Analog Beamformer

Reuse Phase Shifter and Attenuator

Multi Sub-Arrayed Analog Beamforming Architecture

Phase Shift vs True Time Delay

Beam Squint: Change in Beam Direction vs Frequency

Narrow Band: Phase Shifters Adequate

Wide Band: True Time Delay Used

Figures From:

Cascaded Analysis

13

Receiver Noise

► Much receiver design effort is placed on minimizing noise figure (NF). Noise figure

is a measure of the degradation in signal to noise ratio.

OT290Kat edstandardiz , /

/

Out

In

NS

NSF

log10 FNF

Gain/NFTerm

Noise Power = -174dBm/Hz + Gain(dB) + NF(dB)

► The impact of a component or subsystem noise figure is that the output noise power

is increased above the level of thermal noise and gain by the noise figure.

𝐹𝑇𝑜𝑡𝑎𝑙 = 𝐹1 +𝐹2 − 1

𝐺𝑎𝑖𝑛1+

𝐹3 − 1

𝐺𝑎𝑖𝑛1 ∗ 𝐺𝑎𝑖𝑛2+⋯+

𝐹𝑁 − 1

𝐺𝑎𝑖𝑛1 ∗ 𝐺𝑎𝑖𝑛2 ∗ ⋯∗ 𝐺𝑎𝑖𝑛𝑁−1

► Cascaded Noise Figure Equation

14

Receiver Noise (Continued)

► Receiver Total Noise

Combination of RF section and A/D

RF section shaped by anti-aliasing filter

A/D noise typically flat

► Calculation Method

Convert to common units

Noise added in units of power

► Noise Limited Dynamic Range

Signal – Noise Power in Channel BW

15

A/D Noise

Receiver Noise

Total Noise

A/D Sensitivity Loss

Noise Limited Dynamic Range= Signal – Noise Power in Channel BW

Signal at -1dBFs

)/(NoiseReceiver )/(Noise Total (dB) Lossy Sensitivit A/D

1010log10/Noise Total

)/(tyNoiseDensi A/D)( Scale Full A/D)/(Noise A/D

10

)/(Noise A/D

10

)/(NoiseReceiver

10

HzdBmHzdBm

Hz)(dBm

HzdBFsdBmHzdBm

HzdBmHzdBm

Third Order Intercept (TOI)

► Purpose: Industry standard metric to measure linearity in RF amplifiers

16

Two Tone InputTwo Tone Output

With Intermodulation Products

dBc

Pout

f1 f2 f1 f2

2f2-f12f1-f2

Illustration of Two Tone Intermodulation Intercept Point Concept

Po

ut

Pin

Input F

requency

↑1dB/d

B

Intermodulation Product

↑3dB/dB

Third Order Intercept Point

Amplifier Compression Curve

Cascaded ITOI

1

𝐼𝑇𝑂𝐼𝑇𝑜𝑡𝑎𝑙=

1

𝐼𝑇𝑂𝐼1+

1𝐼𝑇𝑂𝐼2𝐺𝑎𝑖𝑛1

+⋯+1

𝐼𝑇𝑂𝐼𝑁𝐺𝑎𝑖𝑛1𝐺𝑎𝑖𝑛2𝐺𝑎𝑖𝑛𝑁−1

Linear ITOI, not dB, used for this equationGainOTOIITOI

dBcPoutOTOI

InterceptOrder ThirdInput

2

InterceptOrder ThirdOutput

Calculation Method

Cascaded Analysis, ADISimRF

► Purpose

Cumulative Tracking of Key RF

Parameters

Signal Power, Cumulative Gain

NF, Noise Power, TOI,

Compression Headroom

► Common Methods

Spreadsheets

Pros: most user flexibility

Cons: cut and paste error prone

RF Simulators

Industry Calculators

Example: ADISimRF

17

ADISimRF Example

► Many components included

► Easy to add user defined blocks

► Most common key metrics calculated

Phase Noise: Definition

Measure of Deviation in the zero crossing of a signal

Consider a Cosine Wave with Phase Fluctuations

Power Spectral Density

Phase Noise:

– Absolute Phase Noise

Total Phase Noise at Output

Sum of Source Oscillators and Device

– Residual Phase Noise

Additive Phase Noise of a Device

Device Noise independent of source used

)(2cos)( tfttx

Hz

rad of units with

)( 22

BW

tfS RMS

2

fSfL

radiansin phase gfluctuatinrandomly )(

frequency ousinstantane

t

f

specified in dBc/Hz from 10𝑙𝑜𝑔 𝐿 𝑓 Plot Method

Frequency Offset

dB

c/H

z

18

Phase Noise Test Setups

Figures from Keysight Application Notes

Residual Phase Noise

Absolute Phase Noise

Phase Detector MethodCross Correlation Method

DUTs with No Frequency Translation DUTs with Frequency Translation

19

System Phase Noise Considerations

► Noise Tracked by

– Quantities

• 10logN

– Frequency Scaling

• 20logN

– PLL Loop BWs

Master

Reference

Synthesizers Receivers / WFGs TRMs

LO/Clock Generation

LO/Clock Generation

Could be:· DDS Based· PLL Based· Direct Analog

D/A

A/D

D/A

A/D

Phased Array Block Diagram from LO/Clock Perspective

Coherent Combining

– Sum of Noise Voltages

𝒗𝑻 = 𝒗𝟏𝟐 + 𝒗𝟐

𝟐 + 𝟐𝒄𝒗𝟏𝒗𝟐

C = correlation coefficient

Ranges -1 to +1

-1 -> Cancels

0 -> Uncorrelated

1 -> Completely Correlated

– Uncorrelated Noise

Signal Increases 20logN,

Noise Increase 10logN

-> 10logN Improvement

20

Objective

10logN Combining Improvement of Distributed Waveform Generators and Receivers

Receiver Architectures

21

Receiver Architecture Options

Type Configuration Benefits Challenges

Heterodyne

• Proven/Trusted

• High Performance

• Optimum Spurious

• High Dynamic Range

• EMI Immunity

• SWAP

• Many Filters

Direct Conversion• Maximum A/D BW

• Simplest WB option

• Image Rejection

-IQ Balance

• In-band IF harmonics

• LO Radiation

• EMI Immunity (IP2)

• DC and 1/f noise

Direct Sampling• No Mixing

• Practical at L/S Band

• A/D Input BW

• Gain not distributed across

Frequency

A/D

ClockLO

RX

A/D

Clock

RX

A/D

Clock

LO

A/D

090

RX

22

Receiver Architecture Options (Continued)

23

Heterodyne with 2nd Nyquist IF Sampling

Direct Sampling with Digital Downconversion

Direct Conversion / Zero IF

FsFs/20

Aliasing

DigitalDown

Conversion

NCO

A/D

Clock

RX NCO

I

Q

A/D

ClockLO

RX

FsFs/2High Side LO

=Fc+3Fs/40 Fc

Aliasing

Downconversion

-Fs/2-Fs FsFs/2LO

0

Downconversion

A/D

Clock

LO

A/D

090

RX

I

Q

Superheterodyne Solutions

Traditional Dual Up/Down Converter Approach

• ADI components available for entire signal chain

• Support will continue24

Trends in Direct Conversion Architectures

► Architecture Benefit

Lowest power: process only the

desired band at the lowest

possible frequency

Best out-of-band performance: no

images, NXM mixing products …

Smallest size: eliminate some

filters and relax others

Lowest system cost

Reduces filters:

Reduce cost and volume and

increase flexibility

► Challenge : Quadrature Error

Digital Assistance implemented in

CMOS mitigates issue

LOgen

ADC

ADC

Digital.DecimateQECDc offsetAGCRSSIBW tune

JESD204b

Synth/ VCO ClkGen

Digitally Assisted Analog

• Digital processing implemented in CMOS

• Correct Analog Errors

• I/Q matching,

• Digital detection with analog correction

• Zero power correction

• Correction tracks temperature

• Infrequent updates

• Better dynamic performance25

AD9371: Integrated Dual RF Transceiver with Observation Path

► Integrated Dual Traffic Rx and Tx

Tuning Range: 300MHz < Fc < 6GHz

FDD/TDD Operation

► Receiver

Max Rx BW = 100MHz

NF: 14dB @ 3.5GHz, max gain

IIP3 20dBm @ 3.5GHz, max gain

IIP2: 65dBm @ 3.5GHz, max gain

Gain Range/Step (dB): 30/0.5

► Transmitter

Max Tx BW = 250MHz

64dBc ACLR (20MHz LTE)

OIP3: 27dBm (5dB atten)

Gain Range/Step (dB): 42/0.05

► Integrated Observation and Sniffer Rx

Max ORx BW = 250MHz

2 inputs

AD9361-like sniffer front end

Dedicated LO

3 inputs

► Total Power (@ max

bandwidth)

Dual Rx = 2.7W

Dual Tx = 3.7W

FDD = 4.9W

► Digital Features

Tx/Rx QEC,

DC offset,

LO leakage

6GSPS JESD204-B

interface

26

All digital Radar Using RF Transceivers

► ADI Transceivers in Radar:

Integration level supports SWaP needs for digitizing

every element

Consistent Interface to Baseband Processor / FPGA

Complete solution for L & S band

Combines with ADI RF portfolio for X, Ku, Ka Band systems

Flexible Frequency Planning

High linearity Direct Conversion Architecture

► Utilized Today in a Number of Next Gen Radar

Systems

ADI TRx + TRM (LNA, PA, SW)

ADI

Transceivers

Ra

da

r D

igit

al

Pro

ce

ss

or(

s)

SW

ADI

TransceiversSW

ADI

TransceiversSW

27

Trends in Direct Sampling & Higher IF Conversion

Digitally Influenced Architectures

► L&S band systems

Direct RF sampling using GSPS ADCs / TRx Solutions

No Discrete Mixing stages

► X, Ku and Higher

Analog Sub-Array ICs

Reduced Mixing Stages with higher integration using GSPS ADCs / TRx.

► DDCs

Increase system configurability

Increased Agility

Dynamic changing from Wideband to Narrowband system ADC

FP

GA

/DS

P

LNA

MXR

DDC

X & Ku band with no 2nd IF & Utilizing DDC

28

Direct Sampling Solution Example

L –Band Direct Sampling now Practical,

S-Band Direct Sampling Imminent with Emerging Converters

Clock

ADF4355

HMC111410 W

2.7-3.8GHz

ADL5602G=20dB

DC-4.0GHz

BPFPout: +36 to +40 dBm

Balun

AD9164

RF DAC

Inte

rfa

ce

to

FP

GA

(JE

SD

20

4B

Se

ria

l In

terf

ace)

BPF

BPF

Balun

AD9625

AD9680

ADC

BPF Preselector

HMC625BRF DVGA

DC-6.0 GHz

HMC8410LNA

.01 – 10 GHz

Clock

Dist.

HMC7043

29

Device Level

Channel Level

Multi-channel

System Level

• Deterministic latency between the converter and

FPGA/ASIC

• Component Level Programmability

Channel level, across multiple components

• Equalization

• Linearization

• I&Q matching and compensation

Synchronizing and maintaining local and remote

system level sync

• Large phased array radar

• Distributed antenna arrays

Device & System Calibration / Synchronization Challenges

► Some applications need a solution that just works to a reasonable degree at power up and is repeatable cycle to cycle.

► Advanced/Extreme synchronization can in some cases be done off-line (although undesirable) but should take less than

a few ms, and at a known interval/instance in time.

► Advanced/Extreme synchronization will likely need to continuously monitor environment conditions to compensate for

temp drift

30

Building the Solution

31

MODULES / SYSTEMSIntegrated SW, FW & HW

REFERENCE

DESIGN

SOLUTIONS

ADVANCED

DEVICES

Support: Products:System

Applications & ISS Technology

Group

Integrated Analog,

Modules, SIPS and iSensors

Sensor Fusion

Support: Products:

Systems Applications

Group

CFTLs, FMCs, Prototypes,

Tier 1 Example Solutions

Support: Products:

Product and Systems

ApplicationsGroups

Die, EP Devices, Class

S Devices, Integrated Products

Solutions ranging from components to subsystem

References

32

1. Delos, “RF Circuit Design References”, High Frequency Electronics, 2015

2. Longbrake, “True Time Delay Beamsteering for Radar”, IEEE, 2012

3. McClaning, Vito, “Radio Receiver Design”, New York, Noble Publishing, 2000.

4. O’Donnell, “Radar Systems Engineering” online lecture notes, http://aess.cs.unh.edu/radar%20se.html

5. “Fundamentals of RF and Microwave Noise Figure Measurements”, Keysight Application Note

6. “Phase Noise Characterization of Microwave Oscillators, Phase Detector Method”, Keysight Product Note 11729B-1.

7. “Practical Intercept Measurements and Cascaded Intermod Equations”, Keysight Application Note

8. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE, 1997

9. Delos, “Receiver Design Considerations In Digital Beamforming Phased Arrays”, Microwaves and RF, 2014

10. Henderson, “Mixers in Microwave Systems” WJ Tech-Note, 1990.

11. Delos, “Phase Locked Loop Noise Transfer Functions”, High Frequency Electronics, Jan 2016

12. Harris, “What’s up with Digital Downconverters” Part 1 and 2, Analog Dialogue, 2016

13. Kester, “Analog-Digital Conversion”, Analog Devices, 2004

14. Ali, “High Speed Data Converters”, IET, 2016

Conclusion

► Digital Beamforming Phased Array Concepts Reviewed

Architectures

Main Subsystems

Benefits / Challenges

Signal Chains

Analysis Considerations

► Proliferation of Phased Array Technology Emerging

Enabled by RF semiconductor technology developments

► Analog Devices looks forward to the future

33

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