Development of enhancement-mode GaN MOSFET on AlGaN/GaN ... · E-mode GaN MOSFET with the maximum...

Development of enhancement-mode GaN

MOSFET on AlGaN/GaN heterostructure

AlGaN/GaN ヘテロ構造上エンハンスメント型

GaN MOSFET の開発

王青鵬

Qingpeng Wang

徳島大学

Tokushima University

2015年 9月

I

Abstract

Compared with Silicon, GaN has great potential on the application of low power

consumption devices for its wide bandgap of 3.4 eV. GaN MOSFETs have become one

of the most attractive research areas. In my thesis, there are four parts will be

introduced, they are 1) device and process design of GaN MOSFET on AlGaN/GaN

heterostructure; 2) study of the accurate mobility and interface state density

characterization method of GaN MOSFET; 3) process optimization for GaN

MOSFETs on AlGaN/GaN heterostructure; and 4) device and process design of

gate-first GaN MOSFET, self-aligned GaN MOSFETs and GaN HEMTs.

In chapter 2, several possible structures of GaN MOSFETs are given an elaborate

comparison and analysis. Device design of GaN MOSFET on AlGaN/GaN

heterostructure is elaborately illustrated including the layout design and fabrication

process design. In the end of this chapter, some preliminary experiments on the dry

recess process are done including the etching gas flow rate, etching protection mask

and the etching chamber pressure. Atomic force microscope (AFM) was used to

investigate the etching profile, surface roughness etc. It is found that the etched

surface would be with higher gas flow rate will show higher roughness with granular

hillock with height of more than 20 nm. PR masked samples show stronger trenching

effect and rougher surface. Also, suspected deposition effect is found in the condition

of higher chamber pressure which is not beneficial to obtain a clean GaN surface.

Finally, a relatively optimum dry recess condition with SiO2 etching protection mask,

etching gas flow of 3 sccm, etching chamber pressure of 0.25 pa was confirmed.

In chapter 3, the problems in characterization of GaN MOSFETs were analyzed

based on our experiments. It is found that even in the same sample, the extracted

channel mobility will be quite different with different device pattern when using the

traditional C-Gm method. A phenomenon of parallel channel caused by worse field

isolation at the gate pad outside the channel was found in bar-type GaN MOSFETs

based on AlGaN/GaN heterostructure. It will result a phenomenon of two-piece

mobility and finally lead an overestimation on the mobility extracted by the C-Gm

method. Also, the variation of channel length extracted by electrical measurement was

found. It will lead an obvious underestimation on mobility, especially in the case of

short channel MOSFETs. To characterize the channel mobility precisely, we have

verified and analyzed these phenomena and presented several improved methods to

II

characterize the mobility of MOSFETs. The mobility of 130 cm2/Vs extracted by our

method agreed quite well with that extracted from a long channel ring type MOSFET

which was thought to be reasonable showing theses method are effective to obtain the

correct value of the channel mobility. In the end of this chapter, the interface state

density extraction method was given a brief introduction on both I-V method of

MOSFET and C-V method of MOS capacitor.

In chapter 4, process optimization including the etching gas, etching bias power,

etching protection mask, oxide type, oxide thickness of the GaN MOSFETs are

investigated and analyzed. The charges near the SiO2/GaN interface of the GaN

MOSFETs with different etching conditions were evaluated. It is found that stronger

bombard damages in dry process will bring more charges near the interface and

finally make the threshold voltage of the device becoming more negative. The effects

of nitrogen plasma treatment and ammonia water treatment were investigated. These

treatments are effective and can recover or remove the dry etching damaged layer. An

E-mode GaN MOSFET with the maximum field-effect mobility of 148.12 cm2/Vs

was realized by ammonia water treatment. GaN MOS capacitors were also prepared

to investigate the influence of these treatments on the interface state densities using

Terman method. The corresponding interface state density for the ammonia water

treated sample was around 3×1011

cm-2

eV-1

in the Ec-Et range from 0.2 to 0.6 eV.

In chapter 5, Low temperature ohmic process was developed on both SI-GaN,

n-GaN and AlGaN. Gate-first GaN MOSFET, self-aligned GaN MOSFET and

AlGaN/GaN HEMT were fabricated using the low temperature ohmic formation

process assisted by ICP dry etching system. Based on common lithography technology,

a narrow access space of 0.3-0.5 µm between schottky and ohmic electrodes was

realized. Based on a ICP dry-etching assisted room temperature ohmic process, the

gate-first GaN MOSFET with maximum channel mobility of 163.8 cm2/Vs was

realized. With 500 °C N2 annealing, ohmic contact on the ICP treated region and

schottky contact on the untreated region were realized at the same time on AlGaN or

SI-GaN. The self-aligned devices show good pinch-off characteristics. The maximum

output current and transconductance were 393 mA/mm and 100 mA/mm for the

self-aligned HEMT and MOSFET, respectively. The easier fabrication process made

these device very practical in fabrication of self-aligned devices.

Key words: GaN MOSFETs, ICP, parallel channel, overestimation, process dependency

III

Contents

Chapter 1 Introduction .................................................................................... 1

1.1 Research background ......................................................................... 1

1.1.1 From Silicon to Gallium Nitride ................................................ 1

1.1.2 Material advances of GaN ......................................................... 2

1.2 Current research status of GaN MOSFETs ........................................ 11

1.3 Difficult points and problems in GaN MOSFETs ............................. 14

1.4 Research motivation and purpose ..................................................... 15

1.5 Outline of the thesis ......................................................................... 15

Chapter 2 Fabrication process of GaN MOSFETs ......................................... 16

2.1 The selection of the device structure ................................................... 16

2.1.1 Key points in realizing the MOSFET ....................................... 16

2.1.2 GaN MOSFET with Ion implantation ...................................... 16

2.1.3 GaN MOSFET on AlGaN/GaN heterostructure ....................... 17

2.2 Process flow of GaN MOSFETs ......................................................... 21

2.2.1 Layout design .......................................................................... 21

2.2.2 Device patterns ....................................................................... 22

2.4 Detailed experimental conditions ....................................................... 23

2.4.1 Process flow of GaN MOSFET with recessed gate ................... 23

2.3.1 Investigation of different ICP recess condition ......................... 26

Chapter 3 Characterization methods of GaN MOSFETs ................................. 35

3.1 Test programs .................................................................................. 35

3.2 Measurement of field-effect mobility ............................................... 35

3.2.1 Mobility of the MOSFET ........................................................ 35

3.2.2 C-Gm method to extract the field-effect mobility ..................... 37

3.2.3 Problem of the C-Gm method ................................................... 38

3.3 Measurement of interface state density............................................. 54

3.3.1 Extraction Dit by MOSFET ...................................................... 54

3.3.1 Extraction Dit by MOS diode ................................................... 58

Chapter 4 Process dependency on GaN MOSFET on AlGaN/GaN

heterostructure ......................................................................................................... 68

IV

4.1 Etching protection mask dependency................................................ 69

4.2 Etching gas dependency ................................................................... 71

4.3 Etching bias dependency .................................................................. 75

4.4 Oxide type and oxide thickness dependency ..................................... 80

4.5 Negative threshold voltage and charges near the interface ................ 84

4.6 Surface treatment to realize the E-mode GaN MOSFET ................... 87

4.7 Summary of this chapter .................................................................. 90

Chapter 5 Fabrication of gate-first and self-aligned GaN FETs ...................... 91

5.1 Problems in ohmic-first MOSFET with recessed gate ...................... 91

5.2 The motivation of gate-first and self-aligned GaN FETs ................... 92

5.3 Process development of gate-first GaN MOSFETs ........................... 93

5.4 Characterization of the gate-first GaN MOSFETs ............................ 97

5.5 Process development of self-aligned GaN MOSFETs ....................... 98

5.6 Characterization of the self-aligned GaN MOSFETs .......................100

5.7 Process development of self-aligned GaN HFETs ...........................102

5.8 Characterization of the self-aligned GaN HFETs .............................104

5.9 Summary of this chapter .................................................................106

Chapter 6 Conclusion ...................................................................................108

Publications .................................................................................................... 110

Bibliography ................................................................................................... 113

Acknowledgement ..........................................................................................124

Development of Enhancement-mode GaN MOSFET on AlGaN/GaN Heterostructure

1

Chapter 1 Introduction

1.1 Research background

1.1.1 From Silicon to Gallium Nitride

Since the first germanium semiconductor transistor was invented John Bardeen

and Walter Brattain in 1940s, the semiconductor industrial has had a booming

development and become the foundation of human information society with a market

over $249 billion[1,2]

. From 1960s, silicon has become the dominated semiconductor

with the standard CMOS process[3,4]

. The major driving force for the growth of the

industry was scaling as described by the famous Moore’s law[5]

. 14-nm node

technology is currently commercialized and 10 nm and 5 nm node are predicted to

reach the market in 2016 and 2020[6]

. In this or the following decade, further scaling

will reach the limits[7]

. On the other hand, most silicon power devices are rated to

maximum junction temperature of 125-200 °C and this temperature was viewed as an

industry standard cutoff point at which a device can be designed to operate at elevated

temperature[8]

. Silicon material is limited for application in high temperature, high

power and high frequency situation for that all these processes tend to consume extra

power, generate heat and finally make the device failed at a rising temperature[9]

.

Hence, new semiconductor materials, GaAs, SiC, GaN and etc., and new transistor

architectures are necessary to replace or to complement silicon.

Gallium nitride (GaN) is a binary III/V direct bandgap semiconductor commonly

used in bright light-emitting diodes since the 1990s[10]

. As the third generation

semiconductor, GaN is a promising semiconductor for high-temperature,

high-frequency, and high-power electronic devices due to its wide band-gap, high

breakdown field, high thermal conductivity, and high carrier saturation velocity[11–14]

.

The compound is a very hard material that has a wurtzite crystal structure. Its wide

band gap of 3.4 eV affords it special properties for applications in optoelectronic[15][16]

,

high-power and high-frequency devices. For example, GaN is the substrate which

makes violet (405 nm) laser diodes possible, without use of nonlinear optical

frequency-doubling. Its sensitivity to ionizing radiation is low (like other group III

nitrides), making it a suitable material for solar cell arrays for satellites. Military and


2

space applications could also benefit as devices have shown stability in radiation

environments[17]

. Because GaN transistors can operate at much higher temperatures

and work at much higher voltages than gallium arsenide (GaAs) transistors, they

make ideal power amplifiers at microwave frequencies[10]

.

Due to these excellent properties, GaN has attracted extensive attention in the

application of power devices, especially in national defense, aerospace, smart grid and

etc.

1.1.2 Material advances of GaN

(1) Crystal and energy band structure of GaN

Basically, GaN has two kinds of crystal structures. They are cubic zinc structure

and hexagonal wurtzite structure and shown in Fig. 1.1[18][19]

.

Ga

N

Zinc Wurtzite

Fig. 1.1 Crystal structure of GaN.

The crystal structure is mainly dominated by its iconicity. In the crystal of a

compound semiconductor, both covalent bond and ionic bond exist. The more ionic

composition in the crystal, the stronger iconicity the crystal will be and the crystal is

more inclined to form a wurtzite structure. The iconicity of the nitride semiconductors

are commonly strong, hence the wurtzite structure is most common structure of the

GaN crystal and also the most stable structure in thermodynamics steady state at room

temperature and 1 atm. On the other hand, the zinc-blende structure is metastable

structure. Commonly, the GaN is in form of hexagonal wurtzite structure, but in

certain condition, zinc-blende structure is also exist. In normal condition, III-V nitride

material are more stable and representative in wurtzite structure[18]

. Hence most of the

GaN devices or researches are based on the wurtzite GaN.


3

The properties of GaN are directly determined by its crystal structure. Fig. 1.2

shows the Brillouin zone and the simplified band structure of the wurtzite GaN. The

lowest electron energy in conduction band and highest electron energy in valence

band were located in point Γ at the same time indicating that GaN has the direct-gap

with band gap of 3.4 eV. The conduction band has second and third energy valley in A

and M-L. Due to the symmetry of the crystal and spin-orbit interaction, the valence

band was split into three band, the heavy-hole, the light-hole and the split-off

band[20,21]

.

KZ

S

H

A

RL

S’

PT

U

Δ

Γ

T’ Σ

MK

KX

KY

Wurtzite Energy

A-valleyM-L valleyes

EAEg

Γ valleyEML

kz kxHeavy holes

Light holes

Split off band

Ecr

O

Fig. 1.2 Brillouin zone and the simplified band structure of the wurtzite GaN.

GaN has advanced physic and electrical property for fabricating high power,

high frequency and high temperature devices. The basic physic and electrical

parameters of GaN were listed in Table 1.1 along with Si, GaAs and 4H-SiC.

Compared to silicon-based power devices, devices made of GaN have superior

advantages as follows: 1) Energy bandgap: GaN has wider energy bandgaps, which


4

result in much lower leakage currents and higher operating temperatures; 2) Critical

electric field: GaN has higher critical electric fields so that devices can have higher

doping concentrations with thinner blocking layers, and resulting in lower specific

on-resistance. 3) Electron saturation velocity: GaN has higher electron saturation

velocity, which leads to higher operating frequencies compared to equivalent

silicon-based devices; 4) thermal conductivity: GaN has higher thermal conductivity

which improves heat spreading and allows operation at higher power densities. The

reason for these advantages of GaN based devices are discussed in following part in

detail.

Table 1.1 Properties of main semiconductors

GaN GaAs Si 4H-SiC

Bandgap (eV) 3.4 1.4 1.1 3.3

Electron mobility (cm2/Vs)

1200 (bulk)

2000 (2DEG) 8000 1400 1000

Electron saturation velocity (cm/s) 2.5107 210

7 110

7 2.010

7

Breakdown field (V/cm) 3.3106 410

5 310

5 3.010

6

Thermal conductivity (W/cmK) 2.1 0.5 1.5 4.9

Relative dielectric constant 9.0 12.9 11.8 9.7

BFOM (to Si) 870 15 1 587

BHFM (to Si) 104 12 1 71

TFOM (to Si) 1220 5 1 1920

(2) Advances of GaN in high power devices

Power devices are always accompanied with high voltage and high current. In

the power devices such as MOS and diodes devices, a n- drift region is often used to

withstanding the higher blocking voltage. However, when the device was turned on,

this N- drift region would become the main reason for the on-resistance. The

on-resistance would limit the on-current and lead extra power loss and finally lower

the power efficiency. Also, the power exhausted on the on-resistance will produce

heat and lead the rising of the device temperature which would be one of the main

reasons for the failure of the device.


5

Compared with Si, wide bandgap semiconductor, such as GaN, could effectively

solve this dilemma for its excellent property in the critical breakdown field. Taking

the simplest schottky diode in Fig. 1.3 for example, the least on-resistance could be

obtained at the condition of that the drift region could be just completely depleted at

the designed off-state blocking voltage. The electric field and potential distribution in

a uniform doped drift region are also shown in Fig. 1.3.

VB N-

Depletion RegionN+

ANODE CATHODE

WD

Em

WD

E (x)

V (x)

VB

X

X

Fig. 1.3 Device structure and the electric field distribution of a Schottky diode.

As shown in Fig 1.3, the maximum electrical field will be at the surface under

the schottky metal. This value is limited by the critical breakdown field of the

materials. The device will break down when the maximum electrical field is beyond

the critical breakdown field. The breakdown voltage (or off-state blocking voltage)

will be the area between the electrical field curve and the x-axis. It can be expressed

by Eq. 1.1[22]

.

, （1.1）

where EC is the critical breakdown field, WD the length of the drift layer ( or the

depletion region). The WD can be further expressed by Eq. 1.2 with VB.

DcB WEV2

1


6

, （1.2）

here, Nd is the doping density of the drift region, ε0εs the dielectric constant.

Substitute Eq. 1.2 into Eq. 1.1, the relation between Ec and VB can be finally

expressed by Eq. 1.3.

. （1.3）

From Eq. 1.3, it could be refer that GaN has breakdown voltage about 100 times

higher than that of Si with the same doping density for that the critical electrical field

Ec is 10 times larger than that of Si. Also, with the fixed designed breakdown

voltage, doping density of the GaN drift region could be 100 times larger than that of

Si. It not only makes the resistance of the drift region more smaller but also makes

the device much smaller when consider the WD-Nd relationship in Eq. 1.2. A simple

demonstration of this circumstance is given in Fig. 1.4.

EC (GaN)

EC (Si)

WD (GaN) WD (Si)

EC (GaN) x WD (GaN)

= Ec (Si) x WD (Si)

E

W

Fig. 1.4 Field distribution in a schottkey diode.

The on resistance of power devices are commonly determined by the resistance

of the drift region. The relationship between the on resistance and the breakdown

voltage can be simply derived as Eq. 1.4. It could be more clearly demonstrated in

Fig. 1.5, device based on GaN will have smaller on-resistance even at higher

breakdown voltage.

B

d

sD V

qN

εεW 02

20

2c

d

sB E

qN

εεV


7

3

0

24

cns

B

dn

Don

Eμεε

V

Nμq

WR

. （1.4）

Actually, the advances of semiconductor material can be described by a series of

figures-of-merit (FOM). Baliga figures-of-merit (BFOM) is widely used for the

evaluation of a unipolar power device in the condition described in Eq. (1.4) and Fig.

1.5 when the conduction loss dominates its total power loss[23]

.

on

B

Cns R

V

εEμεBFOM

2

0

34

== . （1.5）

The expression of BFOM is expressed in Eq. 1.5 and listed in table 1.1. The

larger the BFOM, the better the material will perform in unipolar power device at

low frequency. The BFOM value of GaN are much higher than SiC, GaAs and Si

demonstrating the superior advantages of GaN material for unipolar high power

device like MOSFET or schottky diode.

101

102

103

104

105

10-2

10-1

100

101

102

GaN Limit

SiC Limit

GaAs Limit

Ron (

m

cm

2)

Vbreak

(V)

Si

GaAs

SiC

GaN

Si Limit

Better

Fig. 1.5 On-resistance versus the breakdown voltage of different semiconductors.

(3) Advances of GaN in high frequency devices

In the region of power electronic devices, the power MOS devices are mainly

applied high frequency circuit, such as the high frequency switching circuit. Beside

the power loss on the on-resistance, the switching loss will become non-ignorable part

in the total power loss for the processes of on-state to off-state or off-state to on state

are accompanied by charging and discharging of the input capacitance. In this


8

condition the total loss P could be express by Eq. 1.6.

fAVCA

RIP Gin

on 22 +=, （1.6）

where I is the average on-current, A the gate area, Cin the input capacitance, VG the

gate voltage and f the frequency. Obviously, the power loss reach the minimum value

when A=I/VG [Ron/(Cinf)]1/2

, and can be expressed by Eq. 1.7[9]

.

fCRIVP inonG2=min , （1.7）

here, Cin can be further expressed as Eq. 1.8 when considering Eq. 1.1 and Eq. 1.2.

BG

Cs

G

Ds

inVV

Eεε

V

qNεεC

2=

2=

00

. （1.8）

Consider Ron expression in Eq. 1.4, Pmin will become a final form in Eq. 1.9.

BHFOM

fVVIP

BG

5.175.12

min

8=

, （1.9）

where BHFOM was defined as Baliga’s high-frequency figures-of-merit shown

in Eq. 1.10[24]

.

2= cnEμBHFOM . （1.10）

100

101

102

103

104

0

5

10

15

20

25

30

GaN

SiC

GaAs

Pm

in (

W)

f (MHz)

Si

GaAs

SiC

GaN

Si

Fig. 1.6 The minimum power consumption versus the frequency of different semiconductors.


9

Fig. 1.6 showed the curves of Pmin versus f. Clearly, GaN and SiC have much

lower power loss at higher frequency than that of Si. The corresponding BHFOM

values of these materials are all listed in table 1.1. The higher the BHFOM, the better

the material will perform in high frequency device. The BHFOM value of GaN are

much higher than Si, GaAs and SiC showing that GaN is excellent material for high

frequency device.

(4) Advances of GaN in high temperature devices

There are a number of factors both inside and outside the semiconductor that

limit the high-temperature operation of the semiconductor devices. One temperature

limitation relates to the concentration of free carriers that governs device operation.

Sufficient control of the local free carrier concentration is vital to operation of any

semiconductor device and is primarily accomplished during device fabrication

through the intentional introduction of doping impurities into various desired regions

of the device[25]

.

Basically, the intrinsic carrier concentration in a semiconductor are closely

related with its bandgap EG and temperature T as show in Eq. 11[26,27]

.

)2/exp(= kTENNn GVCi -, （1.11）

where NC and NV are, respectively, the effective electron and hole density of states for

the semiconductor. It should be mention that all of NC, NV and EG are functions of T

and the relationships between them and T are given in the book written by Micheal et

al.[20][28,29]

. Take these factors into account, Fig. 1.7 shows the curves of ni versus

1000/T.

From Eq. 11 and Fig. 1.7, it shows that the intrinsic carrier density would have

and exponential relationship with the item –EG/kT. The intrinsic carrier density would

rapidly increase at a rising temperature when EG is smaller, like Si and GaAs. Take the

doping density ND=1×1016

cm-3

, the intrinsic carrier density would reach the ND at

about 650 °C, 850 °C, 1550 °C and 1560 °C for Si, GaAs, SiC and GaN. These

temperatures are important, but it should be mentioned that it is not the only limitation

for the device worked at high temperature. The difference in intrinsic carrier

concentration between silicon and the wide bandgap semiconductors perhaps becomes

even more important when one considers the fundamental current-voltage (I-V)

properties of rectifying junctions in semiconductor devices. Actually, the device will

failure at much lower temperature by these leakages. For example, the off-state


10

leakage of a p-n junction can be expressed by Eq. 1.12[25][27][30]

.

)2

+(=τ

W

τ

D

N

nqAnI

P

D

i

i- , （1.12）

where A is the area of the junction (cm2), ND is the n-type doping density (cm

-3), W is

the width of the junction depletion region (cm), DP is the hole diffusion constant

(cm2/s), and τ is the effective minority carrier lifetime (seconds).

1 2 3 410

10

1012

1014

1016

1018

GaN

SiC

GaAs

ni (

cm

-3)

1000/T (K-1)

Si

GaAs

SiC

GaN

Si

Fig. 1.7 The intrinsic carrier density at different temperature.

From Eq. 1.12, it is easy to see that the leakage current of a reverse-biased

junction is fundamentally tied to the intrinsic carrier concentration of the

semiconductor. The exponential temperature dependence of ni in Eq. 1.11 dominates

the much smaller temperature variation of the other terms in Eq. 1.12. Thus,

reverse-bias junction leakage currents harmful to Device and circuit operation

increase exponentially with temperature. Because the wide bandgap semiconductors

have much lower intrinsic carrier concentrations (ni) than silicon (see Fig. 1.7), for

example, ni(GaN)/ni(Si)10-20

at room temperature, thus the leakage currents are

orders of magnitude smaller than silicon, provided that junctions are realized in

crystals of adequate structural quality. Therefore, wide bandgap semiconductor

devices, such as GaN and SiC devices are capable of much higher temperature

operation with respect to this fundamental limitation in excess of 600 °C while most

of the Si device could only work at temperature below 200 °C[31–35]

In most circumstances, the heat in the power devices is the ohm heat loss


11

produced the on-resistance and on-current. Hence, the increment of the junction

temperature could be expressed as Eq. 1.13[36–38]

.

ARJRAPRΔ T on2onthLth

, （1.13）

where A is the device area for heat dissipation. Rth is heat resistance and obviously Rth

is inversely proportional to heat conductivity λ as Eq. 1.14.

λ

1Rth∝

. （1.14）

Considering Ron expression in Eq. 1.4, the increment of the junction temperature

could be finally expressed as Eq. 1.15.

TFOM

VJTΔ

2

B

2

on∝ , （1.13）

Where the TFOM was define as the thermal figures of merit and shown

below[9][36][39]

.

3

Cns EμλεTFOM = . （1.13）

The TFOM of GaN, SiC, GaAs and Si are listed in table 1.1. The higher the

TFOM, the better the material will perform in high temperature device. The TFOM

value of GaN are much higher than Si, GaAs and SiC showing that GaN is excellent

material for high temperature device.

1.2 Current research status of GaN MOSFETs

As described in the previous section, GaN have its advantages for high power

high frequency application. Recent years, excellent results have been reported in

AlGaN/GaN heterostructure field-effect transistors (HFETs), but its normally-on

operation made it unsuitable for safe operation and low power consumption[40–49]

.

GaN MOSFETs with a buried channel with higher mobility of 350 cm2/Vs and 400

cm2/Vs had also been reported. But both the normally-on operation and the gate bias

depended smaller transconductance limited its application for power devices[50,51]

. For

safe operation and low power consumption, enhancement operation of the FETs is

required. Basically, enhancement mode operation requires 2 points, (1) positive

threshold voltage and (2) high current conduction at positive gate voltage. In case of


12

MOSFETs, the threshold voltage can be tuned by substrate doping, the positive

threshold voltage will be realized easily compared with other problems. In this

condition, GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with a

surface channel have attracted much attention from researchers.

The first GaN MOSFET with a gate oxide layer of Ga2O3 was reported by F. Ren

et al. in 1998[52]

. After that, there is a booming period of time for the research of GaN

MOS diode and MOSFET. R. Therrien et al. reported a microscopic mechanism for

low defect density interfaces in remote plasma processed MOS device in 1999[53]

. M.

Hong et al. reported a low Dit dielectric/GaN MOS system in 2000[54]

. K. Matoch

studied the positive flatband voltage shift in MOS capacitors on n-type GaN and

determines a pyroelectric charge coefficient of 3.7×109 cm

-2K

-1. J. Kim et al.

investigated the charge pumping in Sc2O3 gated MOS diodes and given a total surface

state density of 3.7×109 cm

-2 in 2002

[55,56]. K. Lee et al. reported a GaN MOSFET

with liquid phase deposited oxide gate from which peak transconductance of 48

mS/mm was obtained in 2002[57]

. H. Wu et al. reported the annealing effects on the

interfacial properties of GaN MOS prepared by photo-enhanced wet oxidation, the

results showed lower interface state density of 5×1010

cm-2

eV-1

and C. Lee et al.

reported a GaN MOS device using SiO2-Ga2O3 insulator grown by

photoelectrochemical oxidation method, the interface state density of theses device

are beyond 2×1011

cm-2

eV-1

in 2003[58,59]

.

The temperature dependence of MgO/GaN MOSFET performance was simulated

by H. Cho et al. in 2003, the results showed that the GaN MOSFET will be

well-suited for high temperature applications[60]

. C. Bae et al. investigated the

reductions in the interface defects by post-oxidation plasma-assisted nitridation in

MOS devices in 2004, Significant improvements are demonstrated by following an

RPAO process step that forms the device interface with an interface nitridation RPAN

step prior to the deposition of an SiO2 dielectric film by RPECVD[61]

. In 2005, a

normally-off GaN n-MOSFET with schottky-barrier source and drain on a p-GaN on

silicon substrate was reported by H. Lee et al., the fabricated device showed a peak

transconductance of 1.6 mS/mm[62]

. K. Abdullah et al. reported the electrical

characteristics of GaN-based MOS structure[63]

.

Si-diffused GaN for enhancement GaN MOSFET on Si applications was studied

by S. Jang et al. in 2006, however the device showed bad output characteristic with an

obvious threshold of the drain voltage[64]

. W. Huang et al. reported the asymmetric


13

interface densities on both n and p-type GaN MOS capacitors in 2006, an interface

state density of 3.8×1010

cm-2

eV-1

was obtained and the results showed that

asymmetric interface state density distribution are with lower density near the

conduction band and higher density near the valence band in GaN MOS system[65,66]

.

GaN MOSFET with gate insulator layer of SiO2 and mobility of 113 cm2/Vs was

reported by H. Kambayashi et al. in 2007[67]

. A 730 V lateral epilayer resurf GaN

MOSFET with the on-resistance of 34 mΩcm2 was reported by W. Huang et al. in

2009[68]

. T. Chow given a report on the similarities and differences between SiC and

GaN MOS interfaces and investigated GaN MOS capacitors and FETs on plasma

etched GaN surface in 2009, the results showed that both less channel electron

trapping and scattering take place in 2H-GaN MOSFETs [69,70]

.

Al2O3 was used to develop a normally-off operation GaN MOSFET with p-GaN

buffer layer was reported by D. Kim et al. in 2010, the device showed a subthreshold

swing of 365 mV/dec[71]

. A. Alam et al. given a comparison of GaN based MOS

structures with different interfacial layer treatment, C-V measures at different

temperatures were performed to analyze the pyroelectric effect in all the GaN

samples[72]

. In the same year, K. Im et al. reported a normally off GaN MOSFET

based on AlGaN/GaN heterostructure with extremely high 2DEG density grown on

silicon substrate which showed channel mobility of 225 cm2/Vs

[73]. In 2011, J.-P Ao et

al. reported GaN MOSFET with the gate oxide deposited by PECVD with silane, the

mobility reached 137 cm2/Vs

[74] and H. Kambayashi reported a high-power

normally-off GaN MOSFET, the fabricated device also exhibited good normally-off

operation and the breakdown voltage of over 600 V[75]

. H. Nakane et al. reported the

C-V characterization of n-GaN MOS diodes with an ALD Al2O3 dielectric layer

showing that the interface state density was significantly reduced compared to that

without (NH4)2S treatment, however, the best result of this paper showed a interface

state density beyond 1012

cm-2

eV-1

which was quite large[76]

. In the same year, GaN

n-MOSFET with MgO/MgO-TiO2 stacked gate dielectrics and a subthreshold swing

of 342 mV/dec was reported by K. Lee et al. and the effects of TMAH treatment on

Al2O3/GaN MOSFET was studied by K. Kim, the fabricated device showed a

mobility around 50 cm2/Vs

[77,78].

A high-performance GaN MOSFET with high-k LaAl2O3/SiO2 gate was reported

by C. Y. Tsai et al. in 2012, the device showed high transconductance of 136 mS/mm

[79]. In 2013, a self-terminating gate recess etching technique was used by Z. Xu et al.


14

to fabricate the GaN MOSFET showing a mobility around 80 cm2/Vs

[80]. In the same

year a MOSFET with peak channel mobility of 251 cm2/Vs was reported by Y. Wang

at al., however, the device showed strong hysteresis making the mobility results

suspicious[81]

. In 2014, S. Gu et al. reported the interface and border traps in ALD

Al2O3/GaN MOS capacitors with two step surface pretreatments on Ga-polar GaN ,

the results showed that a two-step pretreatment, which combined wet sulfide

passivation with in-situ cyclic trimethylaluminum and hydrogen plasma exposure,

was shown to be beneficial in reducing both interface and border traps for

Al2O3/GaN[82]

.

1.3 Difficult points and problems in GaN MOSFETs

A common problem in GaN devices is that the quality of p-type GaN was much

worse than n-GaN which is resulting from the spontaneous polarization effect in GaN

crystal and the low activation and ionization rate of the p-type dopant (usually Mg) in

GaN[83,84]

. Also, the ion implantation in GaN to form n-GaN or p-GaN usually need

much higher energy (usually 102 keV) and not easy to be realized in an ordinary clean

room. Compared with Si or SiC MOS, the native oxide of GaN, Ga2O3, has much

narrower bandgap (4.8 eV) which is not an ideal dielectric layer for the MOSFET[85]

.

As described above, the GaN MOSFET fabrication itself is difficult compared with

the traditional Si MOSFET. The structure and process design of the GaN MOSFET is

one of the study points. Actually, many researchers have been doing research about it

including the device structure, the realization of source and drain, the formation of the

gate oxide and so on[52,55,57-61,67,71,74,77-79]

.

Another problem in GaN MOSFET is the relatively lower mobility. This may be

caused by worse oxide/GaN interface, such as surface damage, surface contamination

and worse recess profile in the GaN MOSFET based on AlGaN/GaN

heterostructure[58,59,61,65,66,69,70,76]

. Thus, the fabrication process optimization to

enhance the device performance is another research region.

Beside the lower mobility, there also exist some problems in the characterization

method of GaN MOSFETs. For example, most of the results of mobility were

evaluated based on a capacitance-transconductance (C-Gm) method, in which the

carrier mobility is calculated from the measured gate capacitance and

transconductance in linear region. So to evaluate the electron mobility precisely, the


15

device structure and the definition of gate length and gate width should be evaluated

carefully for the effective channel length and width may not agree with the designed

size. This problem could be very serious especially in a MOSFET with relatively

narrow gate. However, it is found that this problem has been neglected by most of the

research papers. Thus, effective and accurate evaluation methods, such as the

evaluation method of the channel mobility, are very important issues and precondition

in confirmation of better process between each research paper.

1.4 Research motivation and purpose

As previously mentioned, lower channel mobility is one big problem that limits

the application of GaN MOSFETs. As we all know, the application of Si MOSFETs was

benefit from a mature process that took about 20 years by extremely hard work

contributed by lots of researchers. For GaN MOSFETs, this process is unavoidable. The

research of GaN MOSFETs is still in a primary level. To improve the mobility, there are

still lots of detailed work should be done in the fabrication process. On the other hand,

there are many phenomenon in GaN MOSFETs which is different from Si MOSFETs,

sometimes the characterization methods in Si MOSFETs is not proper for GaN

MOSFETs. How to characterize it correctly is an important item. These matter

described above is the main motivation of this research.

Generally speaking, the main purpose of this research is to realize the GaN

MOSFET, improve the performance of the device and characterize it in a proper way.

The detailed work is to try different device structure and fabrication process conditions.

For example, to try different ICP dry etching conditions to find a better ICP parameter

which can obtain a better recess profile, as a result, the mobility of the MOSFETs will

be improved. Study about the characterization method is also part of my work.

1.5 Outline of the thesis

There will be six chapters in this thesis. Chapter 1 is introduction while chapter 2

and chapter 3 are the fabrication process and characterization method of GaN

MOSFETs. The experimental results and the analysis will be introduced in chapter 4.

Chapter 5 introduces a new way to fabrication GaN MOSFET and HEMT. Finally,

chapter 6 will give the conclusion of this thesis.


16

Chapter 2 Fabrication process of GaN MOSFETs

2.1 The selection of the device structure

2.1.1 Key points in realizing the MOSFET

Commonly, to realize an MOSFET, there are several key points As shown in Fig.

2.1. They are, 1) a good dielectric layer with low leakage current, 2) a good channel

on the substrate semiconductor which could be controlled by the gate bias to realize

on and off state, 3) a good source and drain ohmic contacts connecting with the MOS

channel to conduct the current, and 4) a good interface between the dielectric layer

and substrate semiconductor with low interface states density.

Metal

Dielectric

Active region

Substrate

S G D

B

Channel

Fig. 2.1 A brief MOSFET structure.

In silicon MOSFETs, the gate dielectric layer is often formed by thermal

oxidation of the substrate, a channel was produced by an inversion layer near the

surface, and the off-state was realized by a back-to-back p-n junction structure, the

source and drain ohmic contacts are realized by heavy doping (different type with the

substrate to form p-n junction) by ion implantation and several method to control the

interface states.

2.1.2 GaN MOSFET with Ion implantation

A GaN MOSFET can be fabrication by similar process like the Si MOSFET. The

native oxide of Ga2O3 is not good enough for that the bandgap of it was not wide


17

enough so that the leakage was often very large. Instead of a thermal oxidation, the

CVD based dielectric layer is often utilized as the gate oxide.

Fig. 2.2 showed a GaN MOSFET structure with source and drain ohmic contact

formed by ion implantation. This is an traditional structure and have been realized in

several researchers[64,67,68,70,86]

, but the ion implantation or diffusion process make this

structure very difficult and complicated for fabrication. As the wide bandgap

semiconductor, GaN has very stable crystal structure and very hard. Also, the donor

and acceptor dopants are Si and Mg, making the implantation energy very high and

the efficiency very low. Furthermore, the activation process needs higher temperature

beyond 1200 °C. All these requirements make the process difficult, complicated and

expensive, especially in an ordinary laboratory for research.

SI or P-GaN

Substrate

S DG

N+ N+

Fig. 2.2 GaN MOSFET with ion implantation process.

2.1.3 GaN MOSFET on AlGaN/GaN heterostructure

To avoid the ion implantation and the high temperature activation process in the

structure of Fig. 2.2. GaN MOSFET with recess gate structure could be used[73,74,79,80]

.

This method is simple and the basic starting point is that the ohmic contacts could be

formed on a thin epitaxy layer, n-GaN or AlGaN, which was directly grown on the

substrate GaN while the thin epitaxy of the gate erea should be removed for forming a

channel on the GaN substrate[87–90]

. In this structure, a layer thin gate oxide film (most

situations, Tox ≤ 100 nm) will be deposited on the recessed gate. Hence, the gate recess

should not be so deep for that the coverage of the oxide would become worse on

sidewall of a deeper recess. The worse coverage of the oxide could lead to higher gate

leakage, or even result in the device failure in severe cases. Commonly, the recess


18

depth should less than the oxide thickness (for instance less than 100 nm) and the

thickness of the thin epitaxy layer (AlGaN or n-GaN) should be less than the recess

depth to insure that the MOS channel was formed on the substrate GaN but not on the

n-GaN or AlGaN epitaxy. A common design in our experiment is that the oxide

thickness are 60 to 100 nm, the gate recess depth are 40 to 50 nm, and the thin epitaxy

for forming ohmic contacts are 25 to 35 nm.

Fig. 2.3 showed the structure of GaN MOSFET on AlGaN/GaN heterostructure

with recessed gate. It should be mentioned that an n-GaN layer could also be used

instead of AlGaN, but there are several drawbacks. As discussed above, the n-GaN

layer could not be very thick (about 30 nm) and the doping density during epitaxial

growth is not able to be very high (usualy, ND ≤ 1019

cm-3

) so that the sheet resistance

(which would become part of the series resistance) will be much larger (about 2000

Ω/□) and finally increase the on-resistance of the device.

SI or P-GaN

Substrate

S DG

SiO2

2DEG

AlGaN

Fig. 2.2 GaN MOSFET on AlGaN/GaN heterostructure.

The using of AlGaN/GaN heterostructure to form source and drain is adoptable

for that the high density (usually ≥ 1013

cm-2

) of the two dimensional electron gas

(2DEG) produced by the AlGaN/GaN heterostructure makes the sheet resistance

(about 400 Ω/□) much lower than the corresponding epitaxy n-GaN. Actually, the

ability of the generation of 2DEG layer by heterostructure is also an very important

advantage which distinguished GaN from other semiconductors. Unlike the 2DEG

layer of AlGaAs/GaAs heterostructure in which the electrons are mainly provided by

the dopants in AlGaAs and GaAs, the 2DEG in AlGaN/GaN heterostructure is called

polarization-induced 2DEG. The built-in potential resulting from the polarization

effect can modulate the band structure of the heterostructure and form a very deep and


19

very narrow quantum well at the GaN side, which is beneficial for attracting free

electrons into the well and finally form the 2DEG[18]

.

Fig. 2.3 showed (a) the polarization conditions (SP: spontaneous polarization, PE:

piezoelectric polarization), (b) the distribution of polarization charges, and (c) the

modulated band structures of an AlGaN/GaN heterostructure.

AlGaN

GaN

Substrate

- - - - - - - - - - - - -

+ + + + + + + + + +- - - - - - - - - - - - - - -

+ + + + + + + + + +

σpol <0 σpol >0 EF EC

2DEG2DEG2DEG

PPE

PSP

(a) (b) (c)

PSP

Fig. 2.3 Polarization condition and charge distribution in a AlGaN/GaN wafer.

Fig. 2.3 showed (a) the polarization conditions (SP: spontaneous polarization, PE:

piezoelectric polarization), (b) the distribution of polarization charges, and (c) the

modulated band structures of an AlGaN/GaN heterostructure.

One problem for AlGaN/GaN heterostructure is the current collapse effect by the

electron injection at the source and drain surface[91,92]

. A virtual gate will appear

which could modulate the 2DEG of the access part and finally make the device

showing strong hysteresis[44]

.To eliminate the current collapse effect, n-type AlGaN

barrier layer and GaN cap layer with high doping density could be used [9]. Actually,

the use of n-type AlGaN barrier layer and GaN cap layer can not only eliminate the

current collapse effect but also lower the series resistance of GaN MOSFET. Unlike

the AlGaN/GaN HEMTs of which the gate leakage will become larger, highly doped

n-AlGaN could be used for the MOS channel was directly form on the recessed GaN

and the gate leakage would not change.

Another key point in GaN MOSFET on AlGaN/GaN structure is the substrate.

The substrate should be able to produce a channel at on-state and cut-off the channel

at off-state. Commonly, a p-type substrate could be used in a MOSFET, like Si

MOSFET, which produce a channel by inversion and cut-off the channel by


20

back-to-back p-n junction. However, for p-type GaN substrate in GaN MOSFET on

AlGaN/GaN structure, several drawbacks may exist, 1) the substrate p-GaN is not

beneficial to the formation of high density 2DEG and potential risk of increasing the

on-resistance exists. 2) The activation efficiency and ionization rate of the p-type

dopant (usually, Mg) are usually very low, so that the doping density have to be

sufficient high to maintain a lower free hole concentration. Higher doping density

would deteriorate the channel mobility by impurity scattering.

GaN with low carrier density and high resistive could also be used as the

substrate for that the high resistive could be utilized to cutting off the channel in the

GaN MOSFET on AlGaN/GaN heterostructure. Ideally, the intrinsic GaN is

preferable in this condition for that the intrinsic GaN has the carrier density of 10-10

cm-3

and has high resistive characteristic. However, the unintentional doped GaN

usually has very high n-type background doping density of 1015

~1017

cm-3

leaded by

shallow donors of substitutional Si, O impurities and the native N vacancies during

crystal growth. To obtain GaN with high resistance, the reduction of the background

doping and the introduction of compensatory p-type acceptor are commonly used.

After researching for decades of years, this high resistive GaN was already realized.

It is often called as the semi-insulating GaN (SI-GaN) and realized by introduce C

and Fe dopants[93–96]

. Both C and Fe are acceptor in GaN and can compensate the

background n-type doping to realize the SI-GaN. The high resistive GaN with values

upto 2×109 Ω∙cm and above has been reported

[95]. Fig. 2.4 lists the important

impurity levels in a GaN.

Ec Si VN VN O Fe Fe C Mg Vga EV

0

1

2

3

Ei

Accepter

Donor

VGa

MgGa

CN

Fe

Fe

ON

VN

ET-E

V (

eV

)

SiGa

VN

Conduction Band

Valence Band

Fig. 2.4 Main dopants level in GaN crystal.

Beside the selection of the substrate and surface epitaxy layer, the gate recess


21

process is another important issue in fabrication GaN MOSFET on AlGaN/GaN

heterostructure. There are several basic requirements in the gate recess process, 1) the

etching rate should be controllable for that the recess depth has to be controlled to

around 45 nm, 2) the recessed surface should be flat and with lower surface roughness

which will potentially affect the channel mobility by surface scattering, and 3) the

etching damage and contaminations should be as less as possible for that the damage

or contaminations could affect the interface quality and lower the channel mobility by

impurity scattering.

2.2 Process flow of GaN MOSFETs

2.2.1 Layout design

As described above, GaN MOSFETs could be fabricated by ion implantation

ohmic process or ohmic contacts on AlGaN/GaN heterostructure. Hence, a set of

process compatible photolithography mask of both ion implantation ohmic process

and heterostructure ohmic process is designed by L-EDit provided by Tanner EDA.

The layout of the GaN MOSFET on AlGaN/GaN is shown in Fig. 2.4. Nine

layers of the photolithography masks were designed. They are MARK, ION, MESA,

RECESS, OXIDE, SD, GATE, HOLE and PAD. The mask was designed with

minimum channel length of 2 μm and the mask to mask redundancy space of 3μm.

The function of each mask was listed in table 2.1 in detail.

Table 2.1 Mask list for GaN MOSFETs.

Color Name Mask type Purpose

MARK + Alignment MARK

ION + Ion implantation in active region

MESA - Device isolation

RECESS + Gate recess

OXIDE - Oxide etching

SD + Sour and drain ohmic window

GATE + Gate window

HOLE + Seed layer for electroplate pad

PAD + thick electroplate pad


22

Long

channel

ring-type

MOSFET

short

channel

ring-type

MOSFET

MOS diode

High-

frequency

MOSFET

Short

channel bar

type

Long

channel bar

type

TLM

patterns

Mark

pattern

Breakdown

test pattern

Fig. 2.5 Layout of GaN MOSFET.

It should be mentioned that not all of these masks were used in the fabrication

process. The ION mask should be only used in fabrication of GaN MOSFET with ion

implanted ohmic contact instead of MESA mask in the GaN MOSFET on

AlGaN/GaN heterostructure with recessed gate. The OXIDE mask could be omitted

when the oxide in the active region could be removed by SD mask. The HOLE and

PAD masks are not necessary when the measurement frequency is not very high.

2.2.2 Device patterns

Basically, 4 kinds of GaN MOSFETs pattern were designed in the experiments.

They are long channel ring type, long channel bar type, short channel ring type and

short channel bar type device and shown in Fig. 2.6 (a) ~ (d), respectively. They are

used to evaluate the performance of the GaN MOSFETs, including the output

characteristics, the transfer characteristics and the capacitance-voltage characteristics.

Finally, the channel mobility, interface state density and other basic parameter of the

MOSFET can be calculated by these measurements.

Beside the MOSFET pattern, several auxiliary test structures are also designed in


23

the mask including the (e) Mark pattern, (f) MOS diode pattern, (g)

Breakdown-Testing pattern, (h) TLM pattern, and (i) High-Frequency MOSFET

patterns. All of the patterns from (a) to (i) were labeled in the layout of Fig. 2.5.

(a) Long channel ring type (b) long channel bar type

(c) short channel ring type (d) short channel bar type

Fig. 2.6 Four types of the fabricated MOSFETs

2.4 Detailed experimental conditions

2.4.1 Process flow of GaN MOSFET with recessed gate

The fabrication process of GaN MOSFET was based on the standard

photolithography and lift-off technologies. Firstly, mark trench with depth of around

400 nm was done by ICP dry etching mask with photoresist. Then device isolation

with depth about 100 nm was done by ICP etching with SiCl4 gas. After that the

2DEG layer in the channel region was recessed for 40 nm by controlling etching time

for different etching condition, such as etching gas, etching power. In this process

both photoresist and 500 nm SiO2 etching mask was used to investigate the recess

profile. After gate recess, samples were treated in HNO3 : HF = 1 : 1 solution to

remove the possible contamination of Si on the etched surface. Also, some of the

samples were given special surface treatments, such as N+ plasma treatment and

NH4OH treatment to remove or eliminate the etching damages. Then gate insulators,

such as SiO2, Al2O3, with thickness from 30 nm to 100 nm were deposited using


24

plasma-enhance chemical vapor deposition (PECVD) (PD-220LC, SAMCO). The

ohmic contact was formed using Ti/Al/Ti/Au (50 nm/200 nm/40 nm/40 nm) at

annealing temperature of 850°C for 1 minute in N2 ambient. Evaluation by

transmission line model (TLM) shows that the contact resistance is around 0.3 Ωmm.

Finally, Ni/Au (70 nm/30 nm) was deposited as the gate metal and Ti/Au (30 nm/70

nm) was further deposited on both ohmic and gate electrodes to eliminate the

resistance of the electrodes. The main process steps are shown in Fig. 2.7 and Fig. 2.8,

they are alignment mark, mesa isolation, gate recess, surface treatment, gate oxide

deposition, oxide annealing, source and drain ohmic electrode formation and the gate

metal deposition. Fig. 2.9 shows the photo of the fabricated MOSFET samples.

MARK

MESA

GATE RECESS

SURFACE TREATMENT

SiO2 DEPOSITION

OXIDE ANNEAL

SD FORMATION

GATE FORMATION

depth：40 nm

mask：SiO2, Photoresist

ICP/BIAS:

100/20,100/40,100/60

Etching gas:

SiCl4, Cl2,BCl3

AFM Scan

HNO3/BHF, N+ plasma,

NH4OH

TEOS-based

Silane-based

Fig. 2.7 Process flow of GaN MOSFET on AlGaN/GaN MSOFETs.

It should be mentioned that these process are common but not fixed process.

Actually, a lot of different process condition are tried to investigate the process

dependency on the device performance, (see chapter 4 and 5). Also, The device

structure and process sequences are also changed for some purposes, such as

MOSFET with the gate first process and self-aligned MOSFET and HEMT (see

chapter 6).


25

SI-GaN

Sapphire

AlGaN

SI-GaN

Sapphire

SI-GaN

Sapphire

30 nm

~2 µ m

~40 nm

(a) starting epi

(c) gate recess (d) gate oxide deposition

SI-GaN

Sapphire

(b) MESA isolation

SI-GaN

Sapphire

(e) ohmic electrodes deposition

SI-GaN

Sapphire

(f) gate deposition

Ni/Au

70/30 nm

100 nm

100 nm

Ti/Al/Ti/Au

50/200/40/40 nm

AlGaN

SI-GaN

Sapphire

(g) gate deposition

S

D

G

(h) device pattern

r1

r2r1= 89 µm

r2=183 µm

S DG

Fig. 2.7 Sectional view of the process flow of GaN MOSFET on AlGaN/GaN MOSFETs, (a)

starting epitaxy, (b) mesa isolation, (c) gate recess, (d) gate oxide deposition, (e) source and drain

ohmic electrodes formation, (f) the gate metal deposition, (g) final structure in sectional view, and

(h) final structure in top wiew.


26

Fig. 2.9 A Photo of the fabricated GaN MOSFETs samples

2.3.1 Investigation of different ICP recess condition

As described above, one of the most special parts of the GaN MOSFET on the

AlGaN/GaN heterostructure is the recessed gate. The recess process is very important

for several reasons. 1) the oxide was directly deposited on the recessed surface. Thus,

the properties of the recessed surface partially affect the interface of the MOS

structure and finally determined the interface state density; 2) The worse profile is

important reason for the failure of the MOSFET, for that a shallow recess with AlGaN

remained will make the channel formed on AlGaN while a deep recess would bring

risk of higher gate leakage resulting from worse oxide coverage on the sidewall; 3)

the etching damage and the roughness on the etching surface would affect the electron

transport in the final MOSFET channel by surface scattering and impurity scattering.

Therefore, the recess process in this experiment is one of the most important factors

which finally determine the performance of the GaN MOSFET on AlGaN/GaN

heterostructure with a recessed gate.

A good recess should be with several features, 1) a controllable etching rate, 2) a

good recess profile with uniform etching depth, 3) low etching damage, and 4) low

surface roughness.


27

In order to find a good recess condition, dry recess experiment with different

etching conditions was firstly done using ICP system (RIE-200-iPG, SAMCO, Fig.

2.10) and AFM scanning of the samples was also done to compare the etching rate,

recess profile, surface roughness and so on. The AlGaN/GaN heterostructure for

etching is grown on sapphire substrate with AlGaN thickness of 30 nm and GaN

thickness of 2 μm. During the experiments, the following set of conditions was used as

standard etching conditions: etching gas of SiCl4, pressure of 0.25 Pa, gas flow rate of 3

sccm.

ICP plasma

ICP

coil

ICP power

Sample

Cl2, SiCl4

Gas

Cl2, SiCl4

Gas

He gasto turbo molecular

pump

Bias power

Fig. 2.10 ICP dry etching system

Before etching, all the samples were given SPM and organic cleaning to obtain a

clean surface. Then the PR mask was form directly by lithography while SiO2 mask

was formed by BHF wet etching with PR protection mask. The PR mask on the SiO2

was removed by remover and the sample was cleaned again by organic solution

before dry etching. After the dry etching, the SiO2 mask was removed by HNO3/BHF

solution and the PR mask was removed by remover and organic solution in sequence

to ensure that the surface is clean before the AFM measurement. The detailed

conditions of the dry etching experiments are shown in Table 2.2, including the

etching gas flow rate, etching mask, etching bias power, etching ICP power, and

etching chamber pressure. The etching patterns are with length of 10 μm and width of

60 μm. The AFM detectable range was 20 μm × 20 μm and The surface roughness

was obtain in the recessed part.


28

Table 2.2 Experiment condition of the dry recess process.

No. 1 2 3 4 5 6

Etching Mask SiO2 SiO2 SiO2 PR SiO2 SiO2

Gas Flow (sccm) 3 4 6 3 3 3

Pressure (Pa) 0.25 0.25 0.25 0.25 0.5 1

ICP Power (W) 100 100 100 100 100 100

Bias Power (W) 20 20 20 20 20 20

Etching Time (min) 40 60 60 40 60 60

*PR =photoresist, SiO2 = 500 nm SiO2

(a) Gas flow rate

With the other etching condition remained as the standard condition, the gas flow

rate of 3, 4 and 6 sccm are adjusted to compare the etching image. Fig. 2.11 showed

the AMF height images and amplitude images of the etched samples. The height

images are shown in left side while the amplitude images are shown in right side.

From the amplitude images, it is found that rougher surface is obtained when the

etching gas flow rate is higher.

The detailed etching results are calculated from the AFM data including the

etching profile, surface roughness, etching depth etching rate and so on. Fig. 2.12

showed the etching profiles, etching rate and surface roughness (RRMS) with different

etching gas flow rate. The rougher surface roughness and lower etching rate were

obtained when higher etching gas flow was used, especially when the gas flow rate

reached 6 sccm, granular hillock with height of more than 20 nm could be observed.

The device has potential risk of higher gate leakage when gate oxide was deposited on

such surface with these hillocks. As a result, smaller gas flow rate (3 sccm) is more

adoptable in the gate recess process.

(b) Etching mask

Etching mask is another important factor in the dry recess process. For easy

fabrication, the PR mask was often used as the protection mask in the dry process. In

this experiment, the etching protection mask of 2 μm PR and 500 nm SiO2 are utilized

to investigate the effect of different etching mask. Fig. 2.13 showed the AMF height

images and amplitude images of the etched samples. The height images are shown in

left side and the amplitude images are shown in right side. From the amplitude images,

it is found that rougher surface are obtained in sample was masked by PR. Also, the


29

slop of the sidewall is smaller in the PR masked sample.

The detailed etching results are calculated from the AFM data including the

etching profile, surface roughness, etching depth etching rate and so on. Fig. 2.14

showed the etching profiles, etching rate and surface roughness (RRMS) with different

etching gas flow rate. The rougher surface roughness and higher etching rate were

obtained when PR etching mask was used. It is interesting that the sidewall of the PR

mask sample has much smaller slop than that of the SiO2 mask sample. Also, the

trenching effect near the sidewall and the surface roughness of the recess region of PR

masked sample was more serious than that of the SiO2 mask sample.

(a) 3 sccm

height image amplitude image

(b) 4 sccm

(c) 6 sccm

Fig. 2.11 AFM images of samples recessed with different etching gas flow rate.


30

0 5 10 15 20

-50

0

50

100

150

200

250

300

6 sccm

4 sccm

3 sccm

Depth

(nm

)

Length (m)

hillock

3.0 3.5 4.0 4.5 5.0 5.5 6.00.7

0.8

0.9

1.0

1.1

Gas Flow (sccm)R

MS

(nm

)

1.3

1.4

1.5

Etc

hin

g R

ate

(nm

/min

)

Fig. 2.12 Etching profile, rate and surface roughness of samples recessed with different etching

gas flow rate.

(a) SiO2


(b) PR

Fig. 2.13 AFM images of samples recessed with different etching protection masks.


31

0 5 10 15 20

-50

0

50

100

150

200

250

300

PR

Depth

(nm

)

Length (m)

trentching

effect

SiO2

SiO2 PR

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

Etching Mask

RM

S (

nm

)

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

Etc

hin

g R

ate

(n

m/m

in)


protection masks.

PR Mask

SiO2

Mask

Deposition(a) (b)

2µm

500nm

Fig. 2.15 Schematic graph of the reasons of trenching effect at the bottom of the sidewall

The trenching effect at the bottom of the sidewall was a serious problem in this

structure. This effect had also been observed in ion-milled samples and results from

enhanced sputtering caused by the energetic ions which are reflected at low angles

from the sidewalls[97,98]

. Also, a deposition effect will probably lower the etching rate

in the center of the recess. Carbon from the photoresist also possibly accelerated the

etching rate at the bottom of the sidewall to form such a profile. Furthermore, other

effect, such as the surface charging effect, may also change the profile[99–101]

. But it

often shows a bowling or barreling shape which are quite different form profile with

the trenching effect.

The possible reason for the trenching effect in our dry recess experiment are

considered to be the combination of the plasma concentration resulting from ion

reflection from the sidewalls and the lower etching rate in the center resulting from

the deposition effect[87]

. Fig. 2.15 shows that how the profile of both PR and SiO2

mask. Photoresist mask often shows a ladder-like shape caused by post bake. The ion


32

reflection from the sidewalls is often quite strong because the thickness of the

photoresist is as thick as 2 μm (Fig. 2.15 (a)). On the other hand, SiO2 mask could be

thinner because of the higher dry etching selectivity[102]

. In our samples, the thickness

of the SiO2 etching mask is about 500 nm. The reflection area is quite small, and

angle of the etched side wall is nearly 90° and the trenching effect is quite small (Fig.

2.15 (b)). In general, etching condition of SiO2 mask with proper higher ICP power

would get a good recess profile with uniform depth.

(c) Chamber pressure

With the other etching condition remaining as standard condition, the chamber

pressure of 0.25, 0.5 and 1 pa are adjusted to compare the etching image. Fig. 2.16

showed the AMF height images and amplitude images of the etched samples. The

height images are shown in left side and the amplitude images are shown in right side.

From the amplitude images, it is found that the surface roughness could become

smaller when higher chamber pressure was adjusted. However, the trenching effect

will become stronger at a chamber pressure of 0.5 pa. Also, the etching rate could be

much slower at higher chamber pressure. Actually, an etching rate of 0.3 nm/min is

not preferable for that it will take more than 2 h to obtain a recess of 40 nm.

It seems contradictory that the trenching effect become stronger at 0.5 pa but

become weaker at 1 pa. The possible explanation may come from the deposition

effect. Usually, both etching effect and deposition effect exist in the dry etching

process. At higher pressure, the density of the ions become higher, the mean free

length of the ions may become shorter and the average energy of the ions becomes

lower. The higher density of the ions may enhance the etching effect while the lower

energy of the ions lowers the etching effect. Also, both the higher density and lower

energy will be beneficial for the deposition effect. Thus, the deposition effect become

stronger while etching effect becomes weaker at a higher chamber pressure. The result

of lower etching rate at higher chamber pressure has proved it to some extent. At 0.5

pa, the deposition effect is more obvious in the center of the recess, combined with

the etching effect at the sidewall, the trenching effect may possibly become stronger

than that at 0.25 pa. At 1 pa, the deposition effect is sufficient strong so that it is

obvious both in the recess center and near the sidewall, also the etching effect become

weaker. Finally, the trenching effect near the sidewall may possibly become not

obvious.


33

(a) 0.25 pa


(b) 0.5 pa

(c) 1 pa

Fig. 2.16 AFM images of samples recessed with different etching chamber pressure.

Another evidence for the strong deposition effect is that clearer steps could be

observed on sample prepared by lower chamber pressure in Fig. 2.18. These steps are

usually related with the orientation of the crystal (usually determined by the off-axis

angle)[103,104]

. Usually, the clearer steps demonstrate a better crystal formation. When

deposition effect becomes stronger, these steps may be merged by the deposited

sediment which may be in polycrystalline or non-crystal form. In a MOSFET, It is

more preferable that the MOS channel was on the substrate GaN with better crystal

quality instead of the deposited sediment.


34

0 5 10 15 20

-50

0

50

100

150

200

250

300

1 pa

0.5 pa

0.25 pa

De

pth

(n

m)

Length (m)

trentching

effect

0.0 0.5 1.00.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Pressure (pa)

RM

S (

nm

)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Etc

hin

g R

ate

(nm

/min

)


chamber pressure.

P=0.25 pa P=0.5 pa P=1 pa

Fig. 2.18 Detail surface condition of samples recessed with different etching chamber pressure.

In general, etching condition of chamber pressure of 0.25 pa would be better

condition for the controllable etching rate, better recess profile with less trenching

effect, clean and flat surface with lower roughness and less deposition effect.


35

Chapter 3 Characterization methods of GaN MOSFETs

The characterization method of GaN MOSFETs will be introduced in this chapter.

Generally speaking, there will be three parts. They are the characterization programs,

characterization methods of field effect mobility and interface states density.

3.1 Test programs

AFM test for samples of dry recess experiment.

TLM test to extract the contact resistance and sheet resistance

Current-Voltage (I-V) measurement with Semiconductor Parameter Analyzer.

Drain current versus Drain voltage (Id-VD) test.

Drain current versus Gate voltage (Id-VG) test.

Gate current versus Gate voltage (Ig-VG) test.

Capacitance-Voltage measurement with LCR meter.

Capacitance-Frequency (C-f) test.

Capacitance-Voltage (C-V) test.

3.2 Measurement of field-effect mobility

3.2.1 Mobility of the MOSFET

The channel mobility is one of the most important parameters in the MOSFET

for that it directly determines the on resistance of the channel. Therefore, the power

loss is directly affected by the channel mobility. For high frequency applications, at

low electric fields the carrier velocity is proportional to the mobility with higher

mobility material leading to higher frequency response, because carriers take less time

to travel through the device. Second, higher mobility devices have higher currents that

charge capacitances more rapidly resulting in a higher frequency response.

There are several mobilities in use[105]

. The fundamental mobility is the

microscopic mobility, calculated from basic concepts. It describes the mobility of the

carriers in their respective band. The conductivity mobility is derived from the

conductivity or the resistivity of a semiconducting material. The Hall mobility is

determined from the Hall effect and differs from the conductivity mobility by the Hall

factor.


36

In the MOSFET, the current is mainly dominated by channel current formed by

drift of the minority carrier in the surface channel. The drift mobility refers to the

mobility when minority carriers drift in an electric field. It should be mentioned that

all of the mobility are mobility at low electric field. The mobility at high electric field

is meaningless for that the electron drift velocity will not be proportional to the

electric field and will have a maximum value (electron saturation velocity)[27]

.

Two kinds of mobility are commonly used to evaluate the channel mobility in a

MOSFET, namely, the effective mobility μEFF and the field-effect mobility μFE[105]

.

While the effective mobility is derived from the drain conductance, the field-effect

mobility is determined from the transconductance. Both of the two kind of channel

mobility could be calculated from the transfer characteristic of the MOSFET with a

low drain to source electric field. Fig. 3.1 shows the schematic graph of extracting

these two kinds of channel mobilities[106]

. The field-effect mobility is generally lower

than the effective mobility[105]

. This is rather disturbing, since it is the same device

measured under identical bias conditions. This discrepancy between μEFF and μFE is

due to the neglect of the electric field dependence of the mobility. Intuitively, the

effective mobility shows the average mobility of all the channel electrons while the

field effect mobility shows the mobility of the additional electron resulting from the

varying gate electric field. Since the μFE is better to reflect the influence of electric

field provided by gate bias in the field effect transistors (FETs), μFE is more preferable

to be used in characterization of the channel mobility of the MOSFETs.

O Vg

Id

Vt

A

B

μFE

μEFF

Fig. 3.1 The typical transfer characteristics of the MOSFET.


37

3.2.2 C-Gm method to extract the field-effect mobility

Field-effect mobility is often extracted by the gate capacitance-transconductance

method (C-Gm) from the transfer characteristics of a MOSFET. The detailed derivation

steps were shown below.

The MOSFETs operation model presented by Chih-Tang (Tom) Sah is shown in

Eq. 3.1[27]

,

2

DDThGox

D V2

1VVVμ

L

WCI . (3.1)

In low electric field condition, namely, the condition which is appropriate for the

gradual channel approximation (GCA) model, VD is small enough, for example

VD<<VG－Vth. VD was often set to be 0.1 V, the approximated Id will become Eq. 3.2

DThGox

D VVVμL

WCI . (3.2)

According to the definition of the gate transconductance showed in Eq. 3.3

G

D

m V

IG

∂

∂= . (3.3)

Substitute Eq. 3.3.2 into Eq. 3.3.3, Gm will become Eq. 3.4

Dox

m VL

WCG . (3.4)

From Eq. 3.3.4, the field-effect mobility µFE can be calculated as Eq. 3.5

Dox

m

FE WVC

LGμ = , (3. 5)

here Gm is the transconductance which can be extracted from Id-VG characteristics , L is

the gate length Cox is the gate oxide capacitance which can be extracted from the C-V

measurement and VD is the drain voltage.

In the case of ring-type MOSFET, the value W can’t be obviously obtained from

the designed size. People used to calculate the equivalent value of L/W. Consider a

ring-type pattern like Fig. 3.2, The total channel resistance could be calculated as

Eq.(3.6). Then, with the same channel sheet resistance, the equivalent L/W could be

expressed by Eq. 3.7[87]

.


38

W

LR)

r

rln(

π

R

rπ

drRR

sqaresqarer

r

sqare=

2=

2=

1

22

1

∫,

(3.6)

)ln(2

1

in

out

r

r

W

L

, (3.7)

dox

m

FE VCπ

rrGμ

2

)/ln(=

12

.

(3.8)

Finally, the field-effect mobility can be expressed by Eq. 3.8. Here, r1, r2 are the

inner and outer radii of the ring-type channel.

r1

r2

O

r

dr

W

L

equivalent current

curren

t

Fig. 3.2 Ring-type pattern and bar-type pattern of the MOS channel.

3.2.3 Problem of the C-Gm method

The C-Gm method was commonly used to characterize the channel mobility of a

MOSFET. In a GaN MOSFET on AlGaN/GaN heterostructure with a recessed gate, it

is found some problems may exist if the C-Gm method was directly used without

careful consideration. The following part will give a careful analysis of these problem

and put forward a series of more precise method to characterized the field-effect

mobility of the GaN MOSFET on AlGaN/GaN heterostructure with recessed gate.

(a) Mobility of LR device by C-Gm method.

Based on the gradual channel approximation (GCA), a long channel MOSFET

was firstly utilized for device evaluation in which the effects from the series resistance

and the discrepancy of gate dimension between the design and fabrication can be

minimized[87–90]

. Instead of bar-type one, a long channel ring-type device with outer


39

and inner gate recess radii of 89 μm and 183 μm, respectively, was used to avoid the

leakage current from the isolation region.

0 5 10 15 20

0

1x10-3

2x10-3

3x10-3

4x10-3

5x10-3

I d (

A)

Vg (V)

Vg from -4 V to 10 V

step = 2 V

Fig. 3.3 Current-voltage characteristics of a long channel ring-type MOSFET.

The current-voltage (I-V) characteristics of the long channel ring-type MOSFET

with only mesa isolation is shown in Fig. 3.3. Device operation up to gate voltage of

10 V was confirmed. Fig. 3.4 shows the C-V characteristics, transfer characteristics

and the field-effect mobility under VD=0.1 V. The field-effect mobility of 140 cm2/Vs

is directly obtained by Eq. 3.8, which we call “C-Gm” method.

-10 -5 0 5 100

5p

10p

15p

20p

25p

30p

35p

C forward

C reverse

G forward

G reverse

Vg (V)

C (

F)

(a)

0

2x10-6

4x10-6

6x10-6

8x10-6

1x10-5

G (

S)

-10 -5 0 5 10

0

1x10-5

2x10-5

3x10-5

4x10-5

5x10-5

6x10-5

Id

EF

Vg (V)

I d (

A)

(b)

0

20

40

60

80

100

120

140

160

180

200

E

F(

cm

2/V

s)

Fig. 3.4 (a) C-V characteristic (b) Transfer and mobility characteristics

This field-effect mobility value is considered to be credible value of mobility for

that the influences of the series resistance and dimensional variation on the extraction

of the mobility are small.

(b) Mobility of SB and SR devices by C-Gm method.

In our experiment SB and SR type device with series sizes are prepared.


40

Furthermore, SR type devices can be divided into two groups, SRI for the common

SR and SRII for the special SR devices. The sizes of SB group, SRI group and SRII

group are shown in table 3.1 to table 3.3.

Table 3.1 Device dimensions of SB group

No. 1 2 3 4 5 6 7 8

L (μm) 2 3 4 5 6 10 20 40

W(μm) 56 56 56 56 56 56 56 56

Table 3.2 Device dimensions of SRI group

No. 1 2 3 4 5

r1 (μm) 89 89 89 89 89

r2 (μm) 94 95 99 104 109

L (μm) 5 6 10 15 20

Weff (μm) 575 578 590 605 620

Table 3.3 Device dimensions of SRII group

No. 1 2 3 4 5

r1 (μm) 63 60 57 54 51

r2 (μm) 73 77 83 90 100

L (μm) 9.8 17 26 36 49

Weff (μm) 426 429 434 443 457

ln(r2/r1) 0.14 0.25 0.37 0.51 0.67

The mobilities of MOSFETs of the SB group with only mesa isolation extracted

by C-Gm method with the designed dimensions are shown in Fig. 3.5 (a). Fig. 3.5 (b)

gave a comparison of mobilities of LR, SB, SR type devices on the same chip.

Obvious discrepancy of the field-effect mobility was observed depending on

both the device type and channel length. Mobilities of SR type were much lower than

LR and will increase and close to LR type in region of longer channel length. In the

situation of SB type device, the mobility is larger than that of LR in the region of

longer channel and obviously decreased and closed to SR in the region of short

channel.

Since the mobility should be with little difference on the same wafer, take the

mobility of LR type as standard, the mobility of SB type with longer channel were


41

obviously overestimated and the mobility of SR type were obviously underestimated.

-10 -5 0 5 100

40

80

120

160

200

0 5 10 15 20 25 30 35 40 45 50

60

80

100

120

140

160

180

-5 -4 -3 -20

20

(a)

E

F (cm

2/V

s)

Vg (V)

SB type L (m)

2

3

4

5

6

10

20

40(b)

E

F (cm

2/V

s)

Lmask

(m)

SB

SRI

SRII

LR

Fig. 3.5 (a) Mobility characteristics of SB type. (b) Comprision of mobilities of LR,SB and SR

type.

(c) Variation of Channel width in SB type devices

To explain the mobility overestimation, SB type devices were carefully

investigated. A phenomenon of parallel channels was presented here. As showed in

Fig. 3.6, parallel channels may exist under the redundant gate in the isolation region

with only mesa process, thus the true channel width of the bar-type MOSFET may

larger than the designed one. Finally, the mobility calculated with the designed size

directly by C-Gm method would be larger than the standard value.

S D

Gparalell channel in field

isolation region

main channel in recess

region

boundary of field

isolation region

Fig. 3.6 Current flow paths in bar-type MOSFET with mesa isolation.

Theoretically, phenomenon of parallel channels could not be directly observed if

the threshold voltages have no difference between the parallel channel and main

channel in Fig. 3.6. It is reported that the threshold voltage may change with the dry

recess conditions, especially the bias power of ICP system[87,107,108]

. Parallel channels


42

may be observed when the etching condition between mesa isolation and gate recess

are with differences. In our samples, as showed in enlarged graph of Fig. 3.5(a), “tails”

are observed below the threshold in the mobility characteristics. Furthermore, if the

difference of the threshold between parallel channel and main channel is big enough,

instead of the “tails”, a phenomenon of “two-piece” mobility will appear. As showed

in Fig. 3.7, our previous work in showed two-piece mobility in the bar-type

devices[88,109]

.

-10 -5 0 5 100

40

80

120

160

200

240

F

E (

cm

2/V

s)

Vg (V)

Bar-type

Ring-type

two pieces

Fig. 3.7 Mobility characterization of bar-type and ring type devices.

The differences in the threshold were due to the different etching condition. It

should be mentioned that this effect will be not obvious but still exist when the etching

conditions between the mesa isolation and recess etching are nearly the same. Also, it

will become weaker in devices with extremely shorter channel. Consequently, the

actual gate width would be larger than designed size, thus unintentional

over-estimation of the mobility will happen if C-Gm method is used.

(d) Field isolation with Boron ion implantation

The original idea for mesa process is to remove the 2DEG layer for isolation

between devices. However, for field-effect devices, the resistance will change with the

gate bias even in the mesa region. Thus, the parallel channel introduced above will

appear. To overcome this problem field isolation is necessary.

In our experiment, boron ion implantation was used for field isolation (Fig. 3.8

(a)). Two steps ion implantation were done. The implantation energy, dose were 110

keV, 7×1014

cm-2

and 30 keV, 5×1014

cm-2

, respectively. The mask for implantation

was the double layers of 2 μm positive photoresist (HPR 1183L, Fuji film) and 500


43

nm SiO2 [110,111]

. The following discussion are all based on devices with boron ion

implantation as field isolation.

Fig. 3.8 (b) and Fig. 3.9 (a) showed the current-voltage (I-V) and transfer

characteristics of LR type. The mobility of LR type was about 131 cm2/Vs

characterized by C-Gm method, in table IV, it was labeled as LR method. Fig. 9 (b)

showed the comparison of mobility of devices with different type and dimensions.

We can see that all of the SB, SR type showed similar trend on the relationship

between mobility and channel length. There is no overestimation on the mobility SB

type. It demonstrates that boron implantation is effective way cutting off the parallel

channel. Also, the underestimation of mobilities in short channel devices still exist.

0 5 10 15 200

1x10-3

2x10-3

3x10-3

4x10-3

5x10-3

(b)

I d

(A

)

Vg (V)

Vg from -4 V to 4 V

step = 2 V

(a)

i-GaN

Sapphire

Buffer

2DEGi-GaN

S G

AlGaN

MESA +

B+ implantaiton

Fig. 3.8 (a) Device structure with boron ion implantation. (b) current-voltage characteristics.

0 5 10 15 20 25 30 35 40 45 50

60

80

100

120

140

160

-10 -5 0 5 100

1x10-5

2x10-5

3x10-5

4x10-5

5x10-5

6x10-5

(a)

Id

EF

Vg (V)

I d (

A)

(b)0

40

80

120

160

200

F

E (

cm

2/V

s)

F

E (

cm

2/V

s)

Lmask

(m)

SB

SRI

SRII

LR

Fig. 3.9 (a) Transfer and mobility characteristics. (b) Comprision of mobilities of LR, SB and

SR type.

(e) Variation of Channel length

The mobility underestimation was commonly observed in SR and SB type

devices. In silicon MOSFET, this underestimation was commonly considered to be


44

caused by the series resistance. In GaN MOSFET on AlGaN/GaN heterostructure with

recessed gate, it may be also caused by the variation of channel length due to

over-etching in ICP dry recess process. As showed in Fig. 3.10, the length of recessed

part reached more than 41 μm with its designed size of only 40μm.

Fig. 3.10 Recessed gate part viewed from microscope

It should be mention that except for the visible extension, invisible variation of

the channel length also exists. Here, a rough method to calculate the variation of

channel length and the true channel mobility is presented. Assuming the

underestimation of the mobility are all caused by the extension of the channel length,

according to Eq. 3.5 and Eq. 3.8, the true mobility μtrue and the extracted mobility

μtest may have relationship like Eq. 3.9 and Eq. 3.10 in bar-type and ring-type devices,

respectively.

masktruetruetest L

L 111

, (3.9)

Xr

truetruetest

11 , (3.10)

here

maskeff LLrL 2 , (3.11)

12

21 11

r/rln

r/r/X

, (3.12)

here, ΔL is the difference between the effective channel length Leff and the designed

channel length Lmask. As the test value of mobility is already known, if we plot the

1/μtest versus 1/L or 1/μtest versus X (Fig. 3.11), the μtest can be extracted from the

intercept of y axis while ΔL and Δr from the x axis.

Mesa

region

Recess

region

S

D


45

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60.0

2.0x10-3

4.0x10-3

6.0x10-3

8.0x10-3

1.0x10-2

1.2x10-2

1.4x10-2

1.6x10-2

-1.2 -0.8 -0.4 0.0 0.4 0.80.0

2.0x10-3

4.0x10-3

6.0x10-3

8.0x10-3

1.0x10-2

1.2x10-2

SR type

1/

te

st (

Vs/c

m2)

1/L (m-1)

(a)

SB type

(b)

1/

te

st (

Vs/c

m2)

X (m-1)

Fig. 3.11 (a) 1/μtest versus 1/L characteristic in SB devices. (b) 1/μtest versus X characteristic

The extracted μtrue , ΔL , Δr are about 130 cm2/Vs, 1.9 μm, and 0.94 μm,

respectively. It should be mentioned that this method is rough for the neglect of the

series resistance and also the test mobility value which is the maximum mobility

extracted by C-Gm method may not fully represent the mobility at different gate bias.

More accurate method to extract the effective channel length and channel mobility

should be studied.

(f) Methods to extract the effective channel length and mobility

Method to extract effective channel length in SB type with effective field

isolation was presented by J.G.J. Chern at al. long years ago[112]

, we call it Chern

method for simplicity in the following discussion. But in GaN MOSFET, especially

device with worse field isolation, it may not be proper for the change of both channel

length L and channel width W. Avoiding the variation of channel width by worse field

isolation, Ring-type MOSFET can be used. But the Chern method above was no

longer proper in ring-type device for the effective channel width Weff and series

resistance will changed with the device dimensions so that uniform slops and intersect

point could not be obtained. In this condition, detailed relationship between the

resistances and device dimensions in ring-type devices should be carefully

investigated.


46

Rc

Rext Rh Rch

6 μm 3 μmGS

Fig. 3.12 Detailed sizes of the device structure.

Fig. 3.12 showed the detailed device structure in sectional view. From drain to

source, four kind of resistance existed in the GaN MOSFET, they are Ohmic contact

resistance (Rc) of source and drian Ohmic electrodes, extent resistance (Rext),

MISHEMT resistance (Rh) and the channel resistance (Rch). As the sheet resistance of

MISHEMT formed on highly doped n-GaN/n-AlGaN structure with 100 nm thick

oxide layer would almost not change with the positive bias due to the deeper threshold

and current saturation at positive bias. In later deduction process, Rh=Rext could be

taken for simplicity.

In the situation of Ring-type MOSFET, effective channel width Weff can be

calculated by Eq. 3.7. Similar with Chern method, the total resistance Rt from source

to drain can be obtain from the I-V data by Eq. 3.13. Rs, and Rch are the series

resistance and channel resistance. Different from that in bar-type devices, they will

change with the device dimensions. Detailed relationship between the resistance and

designed device dimensions showed as Eq. 3.14 and Eq. 3.15, proper approximation

was done according to the tailor’s expansion.

)()( g21ch21s

d

dt ,V,rrR,rrR

I

VR

, (3.13)

rr

rln

r

rrln

R

rr

RR extc

s

2

2

1

1

21

9

929

1

9

1

2

21

1

21

11

29

11

2

1

rr

RRrR

rr

s

extc

, (3.14)

tgoxFEmask

maskch

VVCWW

LLR

tgoxFE VVCrr

rr

rln

2

11

211

2 , (3.15)


47

here Wmask, Lmask, Δr and ΔL are the designed channel width and length and the

variation of radii and channel length between the designed and actual ones. Obviously,

ΔL=2Δr can be known. µFE, Cox, VG, Vt and VD are the field-effect mobility, gate oxide

capacitance, gate voltage, threshold voltage and drain-source voltage.

tgoxFEst VVCrr

rr

rlnRR

2

11

211

2 . (3.16)

From Eq. 3.13 ~ 3.15, Eq. 3.16 can be obtained. Different from the Chern

Method, according to the equation above, Rt would have a linear relationship with

the item ln(r2/r1) if the device was specially designed in Eq. (10): 1/r1+1/r2 = constant.

The field-effect mobility µFE can be extracted from the slops of the line. The variation

of the channel length ΔL=2Δr can be extracted from the intersect point of lines of Rt ~

ln(r2/r1) at different gate bias (VG-Vt). VG-Vt was used instead of VG to avoid the

influence of smaller variation of Vt. In our samples, SRII type devices were just

specially designed for this method with 1/r1+1/r2 = 0.0296 μm-1

. For this reason, we

call this method the SRII method for simplicity.

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0

1x103

2x103

3x103

4x103

5x103

6x103

7x103

8x103

9x103

1x104

-0.06 -0.04 -0.02-200

-100

0

100

200

Vg-Vt (V)

3

4

5

6

7

8

9

10

Rt (

)

Ln(r2/r

1)

Fig. 3.13 Rt versus ln(r2/r1) at VG-Vt from 3 V to 10 V for SRII MOSFETs.

Fig. 3.13 are series of Rt ln(r2/r1) plots under VG-Vt from 3 to 10 V for SRII

type MOSFETs with ln(r2/r1) from 0.1 to 0.7. ΔL of about 2 ~ 2.7 µm were obtained.

The field-effect mobility µFE was around 130 cm2/Vs under VG-Vt = 3 V, which agreed

quite well with that of the LR MOSFET.


48

To use SRII method, the devices should be specially designed. Actually, method

to extract mobility and ΔL from ordinary ring-type device is more preferred for its

generality. Since the major influencing factor for the using of Chern method with

ring-type devices is the variation of Weff with channel length. It seems that this

problem can be easily solved by using the resistance per unit channel width instead of

the total one. We call it SRI method. But detailed analysis found that limitation would

appear in SRI method.

There are two problems: (1) the true channel width is not known due to the

uncertainty of Δr. (2) unit series resistance are still function of device dimensions and

not constant. ΔW and RsW as a function of designed dimensions are shown in Eq. 3.17

and Eq. 3.18.

2

1

2

1

2

2

1

1

2 lnln2ΔΔ

r

r

r

r

r

r

r

rrW , (3.17)

1

1

2

2

1

1

21 2ln ssmaskss R

r

r

r

r

r

rRWRR

. (3.18)

Design of r2/r1 = constant can make Rs’ constant, but similar with SRII method,

to apply this method the device should be specially designed. Actually, the relative

error between Wtrue ~ Wmask and Rs’~ 2Rs1 can be obtained as ER=(Rs’-2Rs1)/2Rs1 and

EW=ΔW/Wmask, which were shown in Fig. 14 as a function of L and r1. We can see that

the limitation from ΔW is weak and can be omitted in the L range of 0~100μm. The

relative error between Rs’~ 2Rs1 would be much large when the item L/r1 is large. In

this condition SRII type device is not proper for this method.

0 20 40 60 80 1000%

5%

10%

15%

20%

25%

ER

L

r1 (m)

50

89

0 20 40 60 80 100

-0.14%

-0.12%

-0.10%

-0.08%

-0.06%

-0.04%

-0.02%

0.00%r

1 (m)

50

89

EW

L

0 5 10 15 20 250.0%

0.5%

1.0%

Fig. 3.14 ER and EW as a function of L.


49

For all ring-type devices in our exeriment, in normal condition: r1 ≥ 50 μm, L ≤

150 μm and Δr ≤2 μm, then ΔW ≤1μm, EW < 0.32%, so Wtrue ≈ Wmask can be taken.

Detailed in SRI type devices, r1 = 89 μm, L ≤ 20 μm, then ER < 0.75%.

Consider the small relative error, this method is acceptable for SRI type device. Eq.

3.19 is the mathematical expression of this method,

)-(

Δ++2′+′=′ 1

tgoxFE

mask

schsmasktt VVCμ

LLRRRWRR ≈≈ . (3.19)

Fig. 3.15 showed the Rt’~Lmask plots at VG-Vt from 3 V to 10 V. The variation of the

channel length and series resistance can be extracted from the intersect point of these

lines. ΔL of about 1.7 ~ 2.4 µm were obtained. The field-effect mobility was 131

cm2/Vs under VG-Vt = 3 V, which agreed quite well with that of the long channel

ring-type MOSFET.

-5 0 5 10 15 20 25 30

0.0

2.0x105

4.0x105

6.0x105

8.0x105

1.0x106

1.2x106

1.4x106

1.6x106

1.8x106

2.0x106

-2.4 -2.0 -1.6-3x10

4

-2x104

-1x104

0

1x104

2x104

3x104

Vg-V

t (V)

3

4

5

6

7

8

9

10

Rt'

(

m)

Lmask

(m)

Fig. 15 Rt’ versus Lmask at VG-Vt from 3 V to 10 V for SRI MOSFETs.

Although SRII method and SRI method can extract the correct mobility, one

common problem is that it is difficult to obtained the specific ΔL for that the intersect

point was not common. This may be caused by the approximation in the equation

above, especially, Rs or Rs’ are not constant but varied with the device dimensions.

Also the variations of Cox and field-effect mobility with gate bias are important factors.

Furthermore, SRII have to be specially designed for 1/r1+1/r2 = constant. And SRI

devices have to be designed with larger inner radii and smaller channel length, namely

the item L/r1 should be small enough.


50

(g) Improved Methods to extract mobility and effective channel length

Single value of the ΔL and µFE are preferred in characterization of GaN

MOSFET. To obtain single value of ΔL and µFE, the variation of Rs and gate bias

dependent mobility are main problems. To eliminate the influence of discrepant Rs,

dRt/d[1/(VG-Vt)], namely the first derivative of Rt with respect to 1/(VG-Vt), can be

used instead of Rt since Rs is not a function of 1/(VG-Vt). In the linear region of the

Id-VG curve, the value dRt/d[1/(VG-Vt)] seems to be constant. But actually,

dRt/d[1/(VG-Vt)] will have small variations with 1/(VG-Vt) which is due to the variation

of uFE with respect to the gate bias. To overcome this problem, slopes k from the

fitting line of the Rt~1/(VG-Vt) curve could be used instead a series value of

dRt/d[1/(VG-Vt)]. Finally mobility can be extracted from the slope and incept of the

line of k~ln(r2/r1) of SRII type device. The mathematical expression is shown in Eq.

3.20, in Table 3.4, it was labeled as SRII method.

( )[ ]1

+1

Δ+2

1=

1 211

2

rrr

r

rln

CπμVV

Rk

oxFEtg

t

∂

∂≈ , (3.20)

here should be mention that, while extract the slop value, to avoid the nonlinear effect,

it is proper to take Id-VG data in the range of VG-Vt > 3 V.

SRII type was first used, from Fig. 3.16 (a) the slops k was obtained. Fig. 3.16

(b) showed the linear fitting of these slops. Field-effect mobility of 130 cm2/Vs was

obtained from the slop. ΔL=2Δr of 2.36 µm was obtained from the intercept of the

horizontal axis.

0.00 0.05 0.10 0.15 0.20 0.25 0.300

1x103

2x103

3x103

4x103

5x103

6x103

7x103

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

5.0x103

1.0x104

1.5x104

2.0x104

2.5x104

(a)

SRS-1

SRS-2

SRS-3

SRS-4

SRS-5

Rt (

)

1/(Vg-V

t) (/V)

(b)

k

k (V

)

Ln(r2/r

1)

Fig. 3.16 (a) Rt~1/(VG-Vt) characteristices of SRII devices. (b) k~ln(r2/r1) plot of SRII devices.


51

Similar method can be apply to Eq. 3.19, which can be described as Eq. 3.20. Very

similar method in bar-type devices have been presented by De La Moneda at al. in

[113],

oxFE

mask

tg

t

C

LL

VV

Rk

1 . (3.21)

It should be mention that for the existence of ΔL, the true channel width could

not be known, we can use the design one for that they are very close as describe in Eq.

3.17.

0.0 0.1 0.2 0.30.0

5.0x105

1.0x106

1.5x106

-5 0 5 10 15 20 250

1x106

2x106

3x106

4x106

5x106

(a)

SRC-1

SRC-2

SRC-3

SRC-4

SRC-5

R' t

(

m)

1/(Vg-V

t) (/V)

(b)

k'

k' (

mV

)

Lmask

(m)

Fig. 3.17 (a) Rt’~1/(VG-Vt) plots of SRI type. (b) k’~L plot of SRI type.

Fig. 3.17 (a) showed curve of Rt~L of SRI type. The slops k’ obtained from the

fitting lines are shown in Fig. 3.17(b). Field-effect mobility of 132.51 cm2/Vs was

obtained from the slop. ΔL of -2.2 µm was obtained from the intercept of the

horizontal axis. In Table 3.4 , it was labeled as SRI’ method.

To verify the effect of these methods, similar means can be ultilized to the SB

devices (boron ion implanted) as described as Eq. 3.21.

0.0 0.1 0.2 0.30.0

5.0x105

1.0x106

1.5x106

2.0x106

2.5x106

3.0x106

3.5x106

-5 0 5 10 15 20 25 30 35 40 45 500.0

2.0x106

4.0x106

6.0x106

8.0x106

1.0x107

1.2x107

(b)

SRS-1

SRS-2

SRS-3

SRS-4

SRS-5

Rt'

(

m)

1/(Vg-V

t) (/V)

(a)

k'

k' (

mV

)

Lmask

(m)

Fig. 3.18 (a) Rt’~1/(VG-Vt) plots of SRII type. (b) k’~L plot of SRII type.


52

Similar results from SRII type was shown in Fig. 3.18 (a) and (b). Fig. 3.18 (a)

showed curve of R’t~L of SRII type. The slops k’ obtained from the fitting lines are

shown in Fig. 3.18 (b). Field-effect mobility of 129.5 cm2/Vs was obtained from the

slop. ΔL of 2.32 µm was obtained from the intercept of the horizontal axis.

Similar results from SB type was shown in Fig. 3.19. Fig. 3.19 (a) showed curve

of R’t~L of SB type. The slops k’ obtained of the fitting lines are shown in Fig. 3.19

(b). Mobility of 132.46 cm2/Vs was obtained from the slop. ΔL of 2.29 µm was

obtained from the intercept of x axis.

0.0 0.1 0.2 0.30.0

5.0x105

1.0x106

1.5x106

2.0x106

2.5x106

-5 0 5 10 15 20 25 30 35 40 450

1x106

2x106

3x106

4x106

5x106

6x106

7x106

8x106

9x106

1x107

SB-1

SB-2

SB-3

SB-4

SB-5

SB-6

SB-7

SB-8

R' t (

m)

1/(Vg-V

t) (/V)

k'

k' (

mV

)

Lmask

(m)

(a)

(b)

Fig. 3.19 (a) Rt’~1/(VG-Vt) plots of SB type. (b) k’~L plot of SB type.

(h) Discussion and Comparison

The variation of the channel length ΔL may came from the over exposure of

positive type photoresist and over-etching in wet process of SiO2 etching mask, also

the sidewall etching during the ICP etching. Furthermore, etching damage which may

destroy 2DEG layer near the side wall and the parasitic MOSHFET may bring

invisible extension to the channel length. Since the effective channel width Weff were

very large in our samples, series resistance Rs obtained from the intersect point in both

SRII and SRI method was close to 0 Ω. It demonstrates that the underestimation of

field-effect mobility of GaN MOSFET on AlGaN/GaN heterostructure is mainly

caused by the extension of the channel length rather than the series resistance.

Several methods above were used to calculate the ΔL and mobility, the extracted

ΔL and mobility were listed in table IV. Mobility of LR type by C-Gm method was

listed as standard value for comparison. SRI’ method in table IV are with SRI type

devices.


53

Table 3.4 Results of serveral methods

LR SRII SRI SRII' SRI'

Slop - - - 34557 218046

Intercept - - - -0.04 -2.32

Δr (μm) - 1.01~ 1.35 - -1.18 -

μFE (cm2/Vs) 131 129~132 129~133 130.00 129.50

ΔL (μm) - 2.0~ 2.7 1.7~ 2.4 2.36 2.32

SRII and SRI method can not get a single value of both mobility and ΔL. SRII’

method need special designed SRII type devices. Thus SRI’ method are most proper

one among these methods.

Since SRI’ method can be applied in all of SRI, SRII and SB type devices,

comparison of SRI, SRII, SB type devices can be given in Fig. 3.20. Little difference

was found in intercepts and small variation of the slops are due to the inhomogeneity

of the wafer.

-5 0 5 10 15 20 25 30 35 40 45 50

0.0

2.0x106

4.0x106

6.0x106

8.0x106

1.0x107

1.2x107

SB

SRS

SRC

k' (

mV

)

Lmask

(m)

Fig. 3.20 Comparision of SB, SRI and SRII type with SRI’ method

(I) Conclusion

GaN MOSFETs based on AlGaN/GaN heterostructure were fabricated and

characterized. It found that both the channel length and width could be different from

the designed dimensions. Channel width would become wider with only mesa as the

field isolation process. It will lead a phenomenon of parallel channel in the field

region of the bar type MOSFETs which would finally lead to over-estimation on the


54

mobility. Filed isolation with boron ion implantation can solve this problem effectively.

Also, channel length may be different from the designed size due to ICP dry recess

process. The variation of it will bring underestimation on the mobility, especially the

mobility of devices with relatively shorter channel. To avoid the misestimate caused

by dimensional deviation and characterize the mobility and channel length precisely,

several methods to characterize the short channel MOSFETs are presented and

analyzed. Correct field-effect mobility and ΔL can be extracted by these methods.

3.3 Measurement of interface state density

There are several methods to obtain the interface state information in a MOS

system. The capacitance-voltage method, including the Terman method, Hi-Lo

method, conductance method and etc., are commonly used in a MOS diode. In a

MOSFET, the interface state information can be measured by current-voltage method.

In the following part, the important methods and there problem will be studied in

detail.

3.3.1 Extraction Dit by MOSFET

In the subthreshold region of the MOSFET, the drain-to-source electric field is

very weak and the density of the channel carrier is also very low. Thus, in this

condition, the drift current in the channel could be neglected and the drain-to-source

current is almost dominated by the diffusion current leaded by the gradient of the

carrier density in the channel. Theoretically, this current could be expressed by Eq.

3.22[27]

.

L

LNNWqD

dy

yNdWqDI nnd

)()0()(

, （3.22）

here, N’ is the carrier density per unit area under the gate. N’(0) is the carrier density

near the source and could be expressed as Eq. 3.23, while N’(L) is the carrier density

near the drain.

p

W

pp

D

s

dndxxnN

0

0

0 )exp()()0( , （3.23）

The potential distribution of the depletion region of the MOSFET could be

calculated. Hence, Eq. 3.17 could be further expressed as Eq. 3.24.


55

)exp(2

1)0( 0 sp

As

s nNq

N

. （3.24）

Also, the carrier density near the drain could be expressed by Eq. 3.25 for that

the carrier density will have an exponential relationship with the drain voltage.

)exp()0()( dVNLN . （3.25）

Substitute Eq. 3.23 and 3.24 into Eq. 3.22, the drain current could be further

express as below.

)]exp(1)[exp(2

2

2 ds

A

i

s

Asn

d VN

nNq

L

WI

,

)exp(2

2

2 s

A

i

s

Asn

N

nNq

L

W

.

（3.26）

In the MOS structure, the surface potential of the semiconductor and the gate

bias have relationship as Eq. 3.27.

ox

Ass

sfbgC

qN2εVV

, （3.27）

Hence, Eq. 3.28 could be obtaind.

ox

dox

s

As

oxs

g

C

CCqN

Cd

dV

2

11 , （3.28）

According to the definition of the subthreshold swing of the MOSFET, the

expression of the subthreshold swing could be further deduced into Eq. 3.29.

ox

dox

s

g

d

g

C

CC

q

kT

d

dV

Id

dVS )10(ln

)()10(ln

)(ln)10(ln

. （3.29）

Considering the interface state at the interface, the equivalent circuit of the MOS

structure can be expressed as the oxide capacitance COX connected in series with a

parallel connection of the depletion capacitance CD and the interface-related

capacitance as shown in Fig. 3.21.


56

Cox

CitCd

Cox

Cd Cit

G

Fig. 3.21 Capacitance in MOS structure

In this case, the sub-threshold swing can be calculated as Eq. 3.30.

αq

kT)(ln

C

C

C

C

q

kT)(ln

Ilogd

dVS

ox

it

ox

d

d

g10=++110== , （3.30）

here, α is defined as below,

ox

it

ox

d

C

C

C

C1

,

（3.31）

where k is the Boltzmann constant, T is the absolute temperature, and q is the electron

charge. At room temperature (300 K), the minimum value of S will be 59.6 mV/dec

by assuming the gate oxide has no thickness. The interface state will not affect the

subthreshold swing very much when the interface state density is less than 1010

cm-2

eV-1

.

Lo

g Id

Vg

VT

0

Subthreshold

region

Fig. 3.22 Subthreshold characteristic of a MOSFET

In the situation of GaN MOSFET formed on the SI-GaN, the effective doping


57

density in the substrate was very low, so that the depletion capacitance could be

neglected for that the depletion width will be very large and the value of it will be

very small. Hence, the subthreshold swing was mainly determined by the interface

state capacitance resulting from the interface state.

When the subthreshold swing S was extracted from the log Id -VG characteristic

showed in Fig. 3.30, α can be calculated from Eq. 3.31. Then by the previous

assumption that Cd equals 0 in the MOSFET, the capacitance Cit related to the interfaces

states can be calculated. Finally, the interface states density Dit can be extracted by Eq.

3.32.

2=q

CD

it

it . (3.32)

When extracting interface states density from the curve of the log Id -VG, there

faced some specific problems as showed in fig. 3.23. One problem is that bar type

MOSFETs have an average source-to-drain leakage current of 10-7

~10-6

A so that the

extracted S can be over estimate. The other one is that the curve of ring type is usually

not absolutely linear. Also the source-to-drain leakage and fewer test points brings

uncertainty to the determination of S[74,87–89,114]

.By these reason, there is no uniform

standard to give a comparison.

-10 -5 0 5 10

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

I d (

A)

Vg (V)

条形器件环形器件

Fig. 3.23 Subthreshold characteristics extracted from bar-type and ring-type GaN MOSFETs

To avoid these problems, 2 steps was utilized. One is that smaller test step of VG

was taken at the linear region as showed in Fig. 3.24. The second one is that S was

extracted by fitting the linear region with the drain current from 10-10

to 10-9

A as


58

showed in Fig. 3.25. By doing these steps, the interface states density extracted from

the forward and reverse curve and the same chip but different location showed well

uniformity.

As one of the most important parameters in the MOSFET, Dit will be used to

characterize the performance of the GaN MOSFET in the latter chapters.

-6 -5 -4 -3 -210

-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

I d (

A)

Vg (V)

Id

} To extract swing in this region

Fig. 3.24 Subthreshold characteristic with smaller steps of VG

-4.90 -4.88 -4.86 -4.84 -4.82 -4.80 -4.78 -4.76

-10.4

-10.2

-10.0

-9.8

-9.6

-9.4

-9.2

Log Id

log I

d （

log A）

Vg (V)

Fig. 3.25 Linear fitting of the subthreshold region.

3.3.1 Extraction Dit by MOS diode

Beside the interface state extraction method from the MOSFET, C-V methods


59

from a MOS diode are often used in extraction of the interface state density.

Compared with the I-V method in the MOSFET, C-V method can not only extract the

value of the interface state density but also obtain the distribution of the interface state

in the forbidden band. The C-V methods consist of several specific techniques in

extraction of Dit, including the low-frequency method (quasi-static method),

high-frequency method (Terman method), high-low frequency method (Hi-Lo

method), conductance method, Gray-Brown method and so on[105]

. Each method has

its advantages and disadvantages in extraction of the interface state density.

(a) Terman method

The room-temperature, high-frequency capacitance method developed by

Terman was one of the first methods for determining the interface trap density. The

method relies on a high frequency C-V measurement at a frequency sufficiently high

so that interface traps are assumed not to response. They should, therefore, not

contribute any capacitance.

)1

+1

(=Sox

hf CCC

.

(3.33)

How can one measure interface traps if they do not response to the applied AC

signal? Although interface traps do not respond to the ac probe frequency, they do

respond to the slowly varying dc gate voltage and cause the hf-CV curve to stretch out

along the gate voltage axis as interface trap occupancy changes with gate bias

illustrated in Fig. 3.26[105]

.

In other words, for an MOS-C in depletion or inversion additional charge placed

on the gate induces additional semiconductor charge QG= −(Qb+ Qn+ Qit). With

oxSFBG VΦVV ++= . (3.34)

It is obvious that for a given surface potential φs, VG varies when interface traps

are present, leading to the C-V “stretch-out” in Fig. 3.26. The stretch-out produces a

non-parallel shift of the C-V curve. Interface traps distributed uniformly through the

semiconductor band gap produce a fairly smoothly varying but distorted C-V curve.

Interface traps with distinct structure, for example peaked distributions, produce more

abrupt distortions in the C-V curve.


60

-3 -2 -1 0 10.0

0.2

0.4

0.6

0.8

1.0

Dit =

C/C

ox

Vg (V)

Dit

Fig. 3.26 Ideal and measured hf-CV characteristics for a typical MOS capacitor[105]

The relevant equivalent circuit of the hf MOS-C is that in Fig. 3.26 with Cit= 0,

that is Chf= CoxCS/(Cox+ CS) where CS= Cb+ Cn. Chf is the same as that of a device

without interface traps provided CS is the same. The variation of CS with surface

potential is known for an ideal device. Knowing φs for a given Chf in a device without

Qit allows us to construct a φs versus VG curve of the actual capacitor as follows: From

the ideal MOS-C C-V curve, find φs for a given Chf. Then find VG on the experimental

curve for the same Chf, giving one point of a φs versus VG curve. Repeat for other

points until a satisfactory φs-VG curve is constructed. This φs-VG curve contains the

relevant interface trap information. The experimental φs versus VG curve is a

stretched-out version of the theoretical curve and the interface trap density is

determined from this curve by Eq. 3.35.

S

GoxSGox

it d

Vd

q

C

q

C

sd

dV

q

CD

Φ

Δ=)1-

Φ(= 222 , (3.35)

where ΔVG= VG–VG(ideal) is the voltage shift of the experimental from the ideal curve,

and VG the experimental gate voltage.

The method is generally considered to be useful for measuring interface trap

densities of 1010

cm-2

eV-1

and above, and has been widely critiqued[105]

. Its limitations

were originally pointed out to be due to inaccurate capacitance measurements and

insufficiently high frequencies. Theoretical study concluded that Dit in the 109

cm−2

eV-1

range can be determined provided the capacitance is measured to a precision

of 0.001 to 0.002 pF.


61

(b) The calculation of ideal C-V curve

Terman method is one of the most widely used methods to calculate the interface

state density in GaN MOS diode. According to measuring instrument condition of our

lab, Terman method is selected to characterize the interface state density of the GaN

MOS diode. The measurement is very easy for that only high-frequency measurement

is necessary and the measuring instrument is relatively simple. The difficult point of

Terman method lies in the calculation of the ideal C-V curve. In the following part,

the calculation of the ideal C-V curve and comparison between ideal C-V and hf-CV

of Terman method will be introduced in detail. The detailed derivation process could

be found in the Nicollian’s book entitled “MOS physics and technology”[115]

.

Interface

WD

SemiconductorOxide

EC

EF

Ei

EV

qψS

EC-ET

qΦB

Eg/2

x

qΦs

qΨ(x)

qΦ(x)

Depletion layer edge

Fig. 3.27 Band diagram of the MOS system in depletion mode.

An ideal energy band diagram of a n-type semiconductor in depletion region is

shown in Fig. 3.27. The potential qΦ(x) is defined by equation 3.36.

)()(Φ xEExq iF -≡, (3.36)

where EF is the Fermi level and Ei(x) is the intrinsic energy level at x. It is easy to find

that Φ(0)= Φs (defined as surface potential) and Φ(∞)= ΦB (defined as bulk potential).

The band bending ψ(x) is defined by Eq. 3.37.


62

BΦ-Φ(x)Ψ(x) = . (3.37)

In particular, the total band bending or the barrier height ψS =Φs-ΦB could be find.

To make the derivation process easier, the dimensionless potentials u(x) and v(x)

could be defined as Eq. 3.38.

kT

xqxu

)(Φ=)(

, kT

xqxv

)(Ψ=)(

. (3.38)

Thus, the carrier density n(x) can be expressed as Eq. 3.39.

)](exp[=)](exp[=)( xvNxunxn Di ,

and )](exp[=)](exp[=)( xvNxunxp Ai -- . (3.39)

At the surface, u(0)=us and v(0)=vs. The carrier density could be defined as

ns=n(0) and ps=p(0). In the bulk (x→∞), ND-NA=n(∞)-p(∞) could be obtained. Thus,

Eq. 3.40 could be obtained.

)( BiAD usinh=2n-NN ,

)]([)()( xusinh=2nx-pxn i . (3.40)

Based on the depletion approximation, the Poisson equation in one dimension

could be expressed as Eq. 3.41.

s

2

2 )(-=

)(Φd

ε

xρ

dx

x , (3.41)

where,

)+)()([=( x ) AD NNxnxpqρ -- . (3.42)

Substitute Eq. 3.36, 3.37, 3.38 and 3.42 into Eq. 3.41, a dimensionless form of

the Poisson’s equation could be expressed in Eq. 3.43.

})()([{=)(

2

2

2

Bi u-sinhxusinhλdx

xud

, (3.43)

where λi is the intrinsic Debye length, defined as,


63

i

s

i nq

kTελ 22

=

.

(3.44)

Define Fs as the field at the semiconductor surface, where dus/dx=(q/kT)Fs, The

following relationship could be obtained.

∫-0 2)(=)(

sE

S

dx

dud

kT

qF

∫∫ -B

s

B

s

u

u Bi

u

uduuxuλ

dx

udd

dx

du]}sinh[)]({sinh[2=2= 2

2

2

. (3.45)

By solve this equation, Fs could be finally expressed as Eq. (3.46).

),()(= Bs

i

SBs uuFλq

kTuuSgnF -

, (3.46)

where,

)]}cosh()[cosh()sinh(){(2=),( SBBSBBs uuuuuuuF --- . (3.47)

Considering the Gauss’s law, the total charge per unit area in the semiconductor

could be obtained as,

),()()(== BsosBSSs uuFq

kTCuuSgnFεQ - ,

(3.48)

where Co=εs/λi is the effective semiconductor capacitance per unit area. For n-type

GaN, a graph of Qs versus ψs with doping density ND from 1×1015

cm-3

to 1×1019

cm-3

is shown in Fig. 3.28.

The depletion capacitance CD can be obtained by the derivative of Qs with

respect to ψs and shows in Eq. 3.49.

s

s

s

s

s

s

D ψ

u

kT

q

ψ

u

u

Q=C

∂

∂

∂

∂

∂

∂-=

),(

)sinh()sinh()(=

Bs

BsS

sB uuF

uu

λ

ε-uuSgn )(

i . (3.49)

Further, the relationship between VG and ψS, CG and CD is show in Eq. 3.50 and

3.51 respectively.


64

S

i

S

S

i

oxS

SoxG ΨC

QΨ

ε

tQΨVV +=+=+=

,

(3.50)

)/( DiDiG +CCC=CC . (3.51)

Since the relationships among QS, CD and ψS have already be given in Eq. 3.49

and Eq. 3.50. The relationships among CG, ψS and VG could be obtained. Graphs of CG

vs VG and ψS vs VG with ND=1×1017

cm-3

and different oxide thickness are shown in

Fig. 3.29 and Fig. 3.30.

-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.510

-9

10-8

10-7

10-6

10-5

10-4

1019

1018

1017

1016

1015

Qs(q

/cm

2)

S (V)

1014

ND/cm

-3

Fig. 3.28 Qs versus ψs with different substrate doping density

-15 -10 -5 0 50

1

100

20406080100

CG/C

ox

S (V)

tox/nm

Fig. 3.29 CG vs VG with different oxide thickness.


65

-15 -10 -5 0 5

-3

-2

-1

0

S (

V)

20406080100

VG (V)

tox

/nm

Fig. 3.30 ψS vs VG with different oxide thickness.

2.0

2.5

3.0

3.5

-20 -15 -10 -5 0 5 10-3

-2

-1

0

(3)

(2)

(1)

Vg

s(V

g)

C (

F/c

m2)

hf-CV

ideal-CV

x10-8

CG(V

G)

(4)

(3)

Vg-ideal

Vg(V

g)

S (

V)

Vg (V)

hf- s

ideal-s

(1)

Fig. 3.31 Steps to find the relationship between ΔVG ~ φs.

(c) The calculation of ideal C-V curve

Another difficult point is to determine the correspondence between VGtest and φs.

From Eq. 3.49, 3.50 and 3.51, it is easy to calculate CG and VG by a given φs. However,


66

for a given CG or VG, the calculation of φs is difficult for that explicit formulation of φs

with respect to CG was difficult to be obtained. In this paper, a VBA program was

used to find φs and VG for the given CG. The schematic diagram of this program is

shown in Fig. 3.5.3. For a VG, the corresponding measured CG could be obtained by

process (1). Then find the corresponding CG in the idea C-V curve by process (2). The

corresponding ideal VG and φs could be determined by step (3) and (4). Finally, the

ΔVG could be calculated by VG-ideal -VG test and the corresponding relationship

between ΔVG and φs could be construct. From Eq. 3.31 and the constructed ΔVG ~ φs

relationship, Dit is calculated and shown in Fig. 3.32.

0.0 0.2 0.4 0.6 0.8 1.010

10

1011

1012

1013

1014

1015

Dit (

cm

-2eV

-1)

Ec-E

t (eV)

Fig. 3.32 The typical interface state density distribution extracted by Terman method.

(d) The effective range for Terman method

As the Terman method relies on a hf C-V measurement at a frequency

sufficiently high that interface traps are assumed not to respond. Also, another

assumption is that the interface traps could easily catch up with the DC signal to give

a stretch out along the gate voltage which implies the interface state information.

Hence, the effective range in Terman method was determined by the response time τe

(namely, the electron emit time) of the interface state and the frequency of ac small

signal. The electron emit time could be calculated by Read-Shockley-Hall (RSH)

model as Eq. 3.52.

1exp( )C

e

e T C

E E

N kT

,

(3.52)


67

where σe is the electron capture cross section, νT the thermal velocity of the electro, Nc

the effective state density of the conduction band, k the Bolzman constant and T is the

temperature, E the trap level energy.

The figure τe with respect to Ec-Et was shown in Fig. 3.33. With the low

frequency limit for DC signal (such as 1 Hz) and the high frequency limit for AC

signal (such as 1 MHz), the detectable rang (Ec-Et) of Terman method is about 0.2 eV

to 0.6 eV at 300 K, and 0.5 eV to 1.25 eV at 600 K.

0.0 0.5 1.0 1.5 2.010

-10

10-8

10-6

10-4

10-2

100

102

104

600 K500 K400 K300 K

0.6 eV1 Hz

HF limit

e (

s)

Ec-E

t (eV)

LF limit

1 MHz0.2 eV

Fig. 3.33 τe versus Ec-Et at different temperature.


68

Chapter 4 Process dependency on GaN MOSFET on

AlGaN/GaN heterostructure

In the research of MOSFET, one of the most important problems is how to

improve the channel mobility. The channel mobility directly determines the

on-resistance of the device so that the high power and high frequency performance are

finally related with it. It is known to all that it takes several decades of years for the

commercialization of the Si MOSFET and most of the effects are focus on the

elimination of the interface state (or trap) density. Similarly in the GaN MOSFET,

there are still lots of work which should be done to eliminating interface state density

and improve the channel mobility since the research about GaN MOSFETs is still in

preliminary state. Many factors may affect the channel mobility, such as impurity

scattering, interface trap scattering, surface scattering and so on. In the GaN MOSFET

on AlGaN/GaN heterostructure with a recessed gate, the interface was formed on the

dry recessed surface, thus the dry recess process is one of the most important factors

which determines the property of the interface. Specifically, the dry recess process

may bring damage, contaminates etc. into the interface. It not only increases the

interface state density but also changes the threshold voltage of the device. Other

factors which affect the interface property are the surface roughness, oxide type and

the surface treatment and annealing process.

In this chapter, the fabrication process dependency on the device performance

was given an elaborate investigation, including the etching protection mask, etching

gases, etching power, oxide type and oxide thickness, surface treatment and so on.

Also, the reasons for the negative shifts of the threshold voltages were analyzed and

X-ray photoelectron spectroscopy (XPS) experiment was done to confirm the possible

surface damages and contaminates on the dry etched GaN surface. Finally, the

interface state information of device with the surface treatment was investigated with

an GaN MOS diode. In the following part, they will be introduced respectively. It

should be mentioned that the fabrication process with SiO2 etching protection mask,

etching gas of SiCl4, etching bias power of 20 W, dielectric layer with 100 nm


69

silane-based SiO2, surface treatment with only HNO3/BHF solution was set as the

standard conditions. Also, the long-channel ring-type (r1= 89 µm, r2 =183 µm,

Weff=819 μm, L=94 μm) GaN MOSFET (Fig. 2.6) was designed for device evaluation

basing on a gradual channel approximation (GCA) model in order to characterize the

device performance correctly as described in chapter 3. Basic parameters, such as the

field-effect mobility and the interface stated density were used to evaluate the

performance of the device. The calculation processes of these parameters are

described in detail in chapter 3.

4.1 Etching protection mask dependency

Etching protection mask is important in dry recess process. A good etching

protection mask should be with higher selectivity and bring less contaminates. In this

experiment, both 2 μm photoresist mask and 500 nm SiO2 mask were used as the

etching protection mask. The photoresist protection mask was directly produced by

standard lithography with hard bake at 115 °C for 8 min while the SiO2 mask was

deposited by the TEOS based PECVD and give a wet etching by BHF with PR as the

wet etching mask. In the fabrication of the MOSFETs in this part, except for the

etching mask, other processes are standard process.

0 5 10 15 200

1

2

3

4

5

Dra

in C

urr

ent (m

A)

Drain Voltage (V)

SiO2

PR

Fig.4.1 Output characteristics of GaN MOSFET masked by different etching mask.

Fig. 4.1 shows the output characteristics of the GaN MOSFET with gate recess

masked by both PR and SiO2. Both of the devices show good pinch-off characteristics


70

and operation up to gate voltage VG of 10 V was confirmed. The drain current of SiO2

masked device was a little higher than that of the PR masked one showing better

performance.

-10 -5 0 5 10

0

10

20

30

40

50

60

Id

(

m)

Vg (V)

Drain Current

SiO2

PR

-10 -5 0 5 10

0

20

40

60

80

100

120

140

160

180

200

Mobility

SiO2

PR

F

E (

cm

2/V

s)

Fig.4.2 Transfer and mobility characteristics of GaN MOSFET masked by different etching

protection mask.

Fig. 4.2 shows the transfer characteristics of the GaN MOSFET with gate recess

masked by both PR and SiO2 at a drain voltage VD=0.1 V. The corresponding

field-effect mobility were calculated from the transfer characteristics. The field-effect

mobility are 140.16 and 132.41 cm2/Vs for device with SiO2 masked and PR masked

devices, respectively. The field-effect mobility of SiO2 masked device was a little

higher than that of the PR masked one showing better performance.


masked by both PR and SiO2 at a drain voltage VD=0.1 V in the form of

semi-logarithmic scale. From Fig.4.3, the corresponding subthreshold swing of 93.5

and 126.5 mV/dec were extracted showing that the device masked by SiO2 will

cut-off more quick with the gate voltage. From the subthreshold swing, the interface

state density of the MOSFET could be calculated as 1.26×1011

and 2.49×1011

cm-2

eV-1

, respectively. Similarly, the interface state density of SiO2 masked device

was a little lower than that of the PR masked one showing better performance.

Compared the the AFM result in chapter 2, the lower interface state density and

higher field-effect mobility of the 500 nm SiO2 masked devices are quite reasonable


71

since in the SiO2 masked sample, the recess profile is better, the trenching effect is not

so obvious, the contaminates is less and the surface roughness is smaller. The lower

field-effect mobility in PR mask device may be related with higher surface scattering

and impurity scattering.

In general, SiO2 is better etching protection mask compare with PR in the gate

dry recess process.

-7 -6 -5 -4 -3 -21x10

-7

1x10-5

1x10-3

1x10-1

1x101

Id (

uA

)

Vg (V)

SiO2

PR

Fig.4.3 Subthreshold characteristic of device masked by different etching mask.

4.2 Etching gas dependency

Unlike the wet chemical etchants used in wet etching, the dry etching process

typically etches directionally or anisotropically. In dry etching process, the

semiconductor material was often exposed the material to a bombardment of ions that

dislodge portions of the material from the exposed surface.

For GaN related materials, chlorine based gases, such as Cl2, BCl3, SiCl4 etc., are

often used as the etching gases. Different etching gas may have different etching rate,

etching damages, different surface roughness and so on. In this experiment, Cl2, BCl3

and SiCl4 are used as the etching gases. The recess depth is about 40 nm to 100 nm

for all of the devices. In the fabrication of the MOSFETs in this part, except for the

etching gas, other processes are standard process including the etching bias power.


72

-10 -5 0 5 100

10

20

30

40

50

60

Dra

in C

urr

ent (

A)

Gate Voltage (V)

SiCl4

BCl3

SiCl4-Cl

2

Fig.4.4 Transfer characteristics of device etched by different etching gas.

-10 -5 0 5 100

10

20

30

40

50

60

2

I d (

A)

Vg (V)

1 Cl2

2 SiCl4

3 Cl2+SiCl

4

1

3

Fig.4.4 Transfer characteristics of device etched by different etching steps.


etched by SiCl4, BCl3 and two step etching of SiCl4+Cl2. Fig. 4.4 shows the transfer

characteristics of the GaN MOSFET with gate recess etched by Cl2, SiCl4 and two

step etching of Cl2+SiCl4. The drain voltage of both Fig. 4.3 and Fig. 4.4 is 0.1 V. The

threshold voltages of device recessed by Cl2 and two steps etching (SiCl4+Cl2) are a

little deeper while the threshold voltage of device recessed by SiCl4 and BCl3 are

nearly the same, as around -3 V. The corresponding field-effect mobility were

calculated from the transfer characteristics. Fig. 4.5 and Fig. 4.6 show the field-effect


73

mobility of device with different etching gas. The field-effect mobility are 116.4,

136.9 and 140.16 cm2/Vs for device recessed by Cl2, BCl3 and SiCl4, respectively,

while 137.9 and 127.2 cm2/Vs for device recess by two step etching with Cl2+SiCl4

and SiCl4+Cl2. The field-effect mobility of SiCl4 recessed devices is the highest while

two step etching process could improve the channel mobility from the Cl2 etched one

to the SiCl4 etched one.

-10 -5 0 5 100

20

40

60

80

100

120

140

160

Fie

ld-E

ffect M

obili

ty (

cm

2/V

s)

Gate Voltage (V)

SiCl4

BCl4

Cl2

Fig.4.5 Field-effect mobility characteristics of device etched by different etching gas.

-10 -5 0 5 100

32

64

96

128

160

21 Cl2

2 SiCl4

3 Cl2+SiCl

4

F

E (

cm

2/V

s)

Vg (V)

1

3

Fig.4.6 Field-effect mobility characteristics of device etched by different etching steps.

Fig. 4.7 and Fig. 4.8 showthe transfer characteristics of the GaN MOSFET with

gate recess masked by both PR and SiO2 at a drain voltage VD=0.1 V in the form of


74

semi-logarithmic scale. From Fig. 4.7 and Fig. 4.8, the corresponding subthreshold

swing of 152.0, 136.3 and 93.5 mV/dec were extracted for device recessed by Cl2,

BCl3 and SiCl4, respectively, and 115.7 and 116.9 cm2/Vs for device recess by two

step etching with Cl2+SiCl4 and SiCl4+Cl2 showing that the device recessed by SiCl4

will cut-off more quick with the gate voltage. From the subthreshold swing, the

interface state density of the MOSFET could be calculated as 3.44×1011

, 2.85×1011

,

1.26×1011

, 2.09×1011

and 2.13×1011

cm

-2eV

-1 for device recessed by Cl2, BCl3, SiCl4,

Cl2+SiCl4 and SiCl4+Cl2, respectively. Similarly, the interface state density of SiCl4

and BCl3 recessed device was a little lower than that of the Cl2 masked one showing

better performance.

-7 -6 -5 -4 -3 -210

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

Dra

in C

urr

ent (

A)

Gate Voltage (V)

SiCl4

BCl3

SiCl4-Cl

2

Fig.4.7 Subthreshold characteristics of device etched by different etching gas.

The mechanism of why the SiCl4 etched sample has better performance was

investigated. The possible reason is that the AlGaN surface usually has native oxide

Al2O3 or Ga2O3 and the thickness distribution of them are nonuniform[116–118]

. These

oxide act as the etching protection mask which prevent the etch of AlGaN. Due to this

reason, Cl2 etched sample showed rougher surface. When SiCl4 was used, the Si in

SiCl4 is with reducibility which can react with the native oxide so that the etched

surface is with lower roughness. The corresponding AFM images are shown in Fig.

4.10.

In general, SiCl4 is better etching gas compared with BCl3 and Cl2 in the gate dry


75

recess process.

-7 -6 -5 -4 -3 -210

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

I d (

A)

Vg (V)

1 Cl2

2 SiCl4

3 Cl2+SiCl

41

Fig. 4.8 Subthreshold characteristics of device etched by different etching gas.

Fig. 4.9 AFM image of samples etched by Cl2 and SiCl4[116]

4.3 Etching bias dependency

Another important factor in the dry recess process is the etching bias power. As

described above, in dry etching process, the semiconductor material was often

exposed the material to a bombardment of ions that dislodge portions of the material

from the exposed surface. Thus, the energy of the ions will directly determine the

bombardment energy and finally determines the etching rate. Unlike the wet etching,

the higher ion bombardment energy in dry etching will bring higher dry etching

damages. The ion bombardment energy is mainly determined by the bias power of the

ICP dry etching system. To investigate the ion bombardment damages, etching bias


76

power from 20 W to 60 W was adjusted in fabrication of the GaN MOSFET. Except

for the etching bias condition, the other condition in the fabrication are standard

conditions.

-15 -10 -5 0 5 100

10

20

30

40

50

60

100/60100/40

D

rain

Curr

ent (

A)

Gate Voltage (V)

Silane SiO2 100 nm

ICP/Bias

100/20

100/40

100/60

100/20

Fig.4.10 Transfer characteristics of the GaN MOSFET with gate recess with etching bias power

-15 -10 -5 0 5 100

20

40

60

80

100

120

140

160

Fie

ld-E

ffect M

obili

ty (

cm

2/V

s)

Gate Voltage (V)

SiCl4

BCl4

Cl2

Fig.4.11 Field-effect mobility characteristics of the GaN MOSFET with gate recess with etching

bias power


with etching bias power of 20, 40 and 60W at a drain voltage VD=0.1 V. The threshold


77

voltage VT are -3.0, -4.1 and -11.4 V for device with etching bias power of 20, 40 and

60 W. It is interesting that the threshold voltage VT become deeper when the etching

bias power become higher. The corresponding field-effect mobilities were calculated

from the transfer characteristics (Fig. 4.11). The field-effect mobility are 140.16,

122.8 and 113.8 cm2/Vs for devices with etching bias power of 20, 40 and 60 W,

respectively. The field-effect mobility become lower when higher etching bias power

was used. It is reasonable that higher etching bias power brings more etching

damages.

-15 -10 -5 0 510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

Silane SiO2 100 nm

100/60

100/40

Dra

in C

urr

en

t (

A)

Gate Voltage (V)

ICP/Bias

100/20

100/40

100/60

100/20

Fig.4.12 Subthreshold characteristics of the GaN MOSFET with gate recess with etching bias

power


with etching bias power from 20 to 60 W at a drain voltage VD=0.1 V in the form of

semi-logarithmic scale. From Fig.4.12, the corresponding subthreshold swing of 93.5,

148.9 and 196.8 mV/dec were extracted showing that the device etched by lower

etching bias power will cut-off more quickly with the gate voltage. From the

subthreshold swing, the corresponding interface state density of the MOSFET could

be calculated as 1.26×1011

, 3.32×1011

and 5.10×1011

cm-2

eV-1

, respectively. Similarly,

the interface state density will become higher when higher bias power was used in the

dry etching process.

In this experiment, it is found that the threshold voltages showed strong


78

dependence on the bias power of ICP system. Theoretically, the threshold voltage of

an ideal MOSFET formed on SI-GaN surface should be around 0 V. In the experiment

above, threshold voltages among -12 V to -2 V were observed. These negative

threshold voltages may result from at least two possible reasons, (1) the unavoidable

silicon contamination from the etching gas of SiCl4 and nitrogen-vacancy resulting

from surface damage in the dry recess process work as n-type dopants in GaN, and by

this reason the substrate GaN become weak n-type, and (2) positive charges often

exist in the unideal SiO2 layer of the MOS system and they will lead an negative shift

on the threshold voltage. In Fig. 4.10, the deeper threshold voltage at higher bias

power possibly demonstrates the first reason because higher bias power will possibly

bring more surface damage and silicon contamination.

Si contaminates and dry etching damages (such as VN) are both possible reasons

for the negative threshold voltages for Si ( EC-Et=0.012~0.02 eV) and VN (EC-Et=0.03,

0.1 eV) are both shallow donor impurities in GaN crystal. In room temperature, the

impurities ionized and the dry etched surface layer become n-type and finally make

the device showing negative threshold voltages.

It was quite reasonable that deeper threshold voltage was obtained in device

etched by higher bias power of the ICP system for that higher bias power will made the

ion with higher energy and finally lead stronger ion bombard damages. To investigate

that weather it is Si contaminates or the dry etching damage which was mainly

responsible for the negative threshold voltages, xperiment of XPS was done for dry

etched samples. Fig. 4.14 (a) and Fig. 4.14 (b) showed N 1s and Ga 3d spectrum.

The N 1s peak shows obvious decrease with higher bias power while Ga 3d peaks are

with little variation. The decrease of N 1s and Ga 3d peak may be partially related

with nitrogen vacancies (VN) and gallium vacancies (VGa), which are shallow donors

(Ec-Ed= 0.03, 0. 1 eV) and relatively deep acceptor ( EA-Ev = 0.14 eV) [20]

. The

obvious decrease in N 1s demonstrates that instead of VGa, VN is more likely to be

generated in dry etching process. Also, the higher bias power in ICP dry process will

lead more damages (VN). Similar results are also reported in[119]

. It is reported that the

etching damages may reached a depth less than 20 nm from the GaN surface. It

demonstrates that VN caused by dry etching damages may be much important reason

for the negative threshold voltages.


79

404 402 400 398 396 394

w/o ICP

ICP 100/20

ICP 100/40

ICP 100/60

Inte

nsity

Binding Energy (eV)

N 1s

24 22 20 18 16 14 12 10 8

w/o ICP

ICP 100/20

ICP 100/40

ICP 100/60

Inte

nsity

Binding Energy (eV)

Ga 3d

Fig. 4.13 XPS with different etching bias power (a) N 1s (b) Ga 3d.

112 108 104 100 96

bNo

rma

lize

d In

ten

sity

Binding Energy (eV)

a: SiCl4 w/o HNO

3/HF

b: SiCl4-Cl

2 w/o HNO

3/HF

c: SiCl4+HNO

3/HF

a-c

b-c

Ga 3p 1/2Si 2p

a

ca-c

b-c

540 536 532 528

with clean

O 1s

(Ga2O

3)

Inte

nsity

Binding Energy (eV)

SiCl4 100/20 w/o HNO

3/HF

SiCl4-Cl

2 100/20 w/o HNO

3/HF

SiCl4 100/20 with HNO

3/HF


3/HF


3/HF

O 1s

(SiO2)

~1.5 eV

w/o clean

Fig. 4.14 XPS with different etching and surface treatment (a) Si 2p (b) O 1s.

The Si 2p and O 1s spectrum are also investigated. As showed in Fig. 4.14 (a), in

the Ga 3p 1/2 spectrum (106 eV) is overlap with Si 2p spectrum (103 eV, Si-O).

Compared with the sample with HNO3/HF treatment, samples without HNO3/HF


80

treatment show peak at the energy of 103 eV. It can be more obviously observed by

giving a subtraction between the non-cleaning samples and the samples cleaned with

HNO3/HF. As showed in Fig. 4.14 (a), a-c and b-c show obvious Si 2p (Si-O) peaks.

Also, in the O 1s spectrum, samples without HNO3/HF treatment show strong peak at

533 eV which may be related with O 1s (O-Si) [120]

. After cleaned by HNO3/HF, the

peak was become much lower and shift for about 1.5 eV to the low energy side which

may be related with O 1s (O-Ga) [121]

.

From Fig. 4.14 (a) and (b), it demonstrates that Si contaminates exist even in the

SiCl4-Cl2 two steps etching when surface treatment was not done. However, it could be

easily removed by HNO3/HF treatment. Also the Si contamination is more likely to be

in the form of SiO2 and the native oxide of Ga2O3 seems inevitable as long as the

surface was exposed in the air. As a result, it can be referred that Si contaminates in dry

recess process are not an important factor for the negative threshold voltages for all of

the GaN MOSFETs samples were given an HNO3/HF treatment after dry recess

process.

Also, if we go back to see Fig. 3.23 in chapter 3, it can refer that the higher leakage

current at the off-state of the bar-type MOSFET may be caused by

etching-damage-induced n-type surface layer. So, to obtain E-mode operation and

higher on-off ration in recessed GaN MOSFET on AlGaN/GaN heterostructure,

method to remove the dry etching damages would be very important.

In general, lower etching bias power is preferred since lower bias power brings

less bombardment etching damages and make the threshold voltages be more close to

0 V. However, in the dry etching process, lower bias power will lead lower etching

rate. Actually, we even found that etching bias power below 20 W could not etch the

substrate GaN material. Thus etching bias of 20 W is the most proper etching

condition in dry recess process.

4.4 Oxide type and oxide thickness dependency

In the MOS structure, beside the semiconductor side, the oxide is another

important factor which directly affect the performance of the MOSFET. In this paper,

GaN MOSFET with both silane- and TEOS-based oxide layer was used in fabrication

process. Also, the oxide thickness from 30 to 100 nm are adjusted to investigated the

oxide thickness dependency on the device performance. In this part, except for the


81

oxide type and its thickness, all of the other fabrication process of the GaN MOSFETs

are based on the standard process described in beginning of chapter 4.

-10 -5 0 5 100

10

20

30

40

50

60

70

4

5

3 2

Dra

in C

urr

en

t (

A)

Gate Voltage (V)

1 100 nm Silane

2 60 nm Silane

3 30 nm Silane

4 100 nm TEOS

5 30 nm TEOS 1

Fig. 4.15 Transfer characteristics of device with different oxide type and thickness.

-10 -5 0 5 100

20

40

60

80

100

120

140

160

Fie

ld-E

ffect M

obili

ty (

cm

2/V

s)

Gate Volgtage (V)

Silane 100 nm

Silane 60 nm

Silane 30 nm

TEOS 100 nm

TEOS 30 nm

Fig. 4.16 Field-effect mobility characteristics of device with different oxide type and thickness.

Fig. 4.15 shows the transfer characteristics of the GaN MOSFET with different

gate oxide type and oxide thickness at a drain voltage VD=0.1 V. The threshold voltage

VT are 0.0, -1.1 and -3.0 V for silane-based device with oxide thickness of 30, 60 and


82

100 nm, respectively, while the threshold voltage VT are 0.0 and -3.1 V for

TEOS-based devices with oxide thickness of 30 and 100 nm, respectively. It is

interesting that the threshold voltage VT will be close to 0 V when the gate oxides

become thinner.

The measured field-effect mobility values of the devices are shown in Fig. 4.16.

Electron field-effect mobility values of around 140 cm2/Vs are obtained from the

silane-based devices while 65-80 cm2/Vs are obtained from the TEOS-based devices.

The lower mobility values of TEOS-based devices may be mainly caused by the poor

SiO2/GaN interface with high interface state density[122][114]

.

-10 -8 -6 -4 -2 0 2 410

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

4

5

3 2

Dra

in C

urr

en

t (

A)

Gate Voltage (V)

1 100 nm Silane

2 60 nm Silane

3 30 nm Silane

4 100 nm TEOS

5 30 nm TEOS 1

Fig. 4.17 Subthreshold characteristics of device with different oxide type and thickness

Fig. 4.17 shows the transfer characteristics of the GaN MOSFET with with

different oxide type and oxide thickness at a drain voltage VD=0.1 V in the form of

semi-logarithmic scale. From Fig.4.17, the corresponding subthreshold swings of the

silane-based devices are around 80-100 mV/dec, while for the TEOS-based devices,

the subthreshold swings are around 120-140 mV/dec showing that the device with

silane-based oxide will cut-off more quickly with the gate voltage compare with the

TEOS-based one. From the subthreshold swing, the corresponding interface state

density of the MOSFET could be calculated as aound 0.8×1011

-1.5×1011

cm-2

eV-1

and

2.3×1011

-3.0×1011

cm-2

eV-1

for silane and TEOS-based devices, respectively.

Fig. 4.18 shows the typical oxide breakdown properties of both silane- and


83

TEOS-based oxide layers. Since a vertical MOS structure is difficult to realize on the

wafer with sapphire substrate, a lateral MOS structure (Fig. 4.18) was measured in

strong accumulation condition. The results show that the breakdown electrical fields

of both kinds of oxide are around 8 MV/cm and the silane-based oxide is a little

higher than that of TEOS. This value may be underestimated for that the oxide was

deposited on the recessed region and the oxide on the sidewall of the trench may be a

little thinner than the planar region.

0 2 4 6 810

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

Curr

ent

den

sity (

A/c

m2)

Electrical Field (MV/cm)

Silane 100 nm

TEOS 100 nm

SiO

2

SI-G

aN

2D

EG

n

-AlG

aN

n-GaN

Ca

tho

dA

nod

e

Normal Breakdown

Anode

Cathod

Fig. 4.18 Oxide breakdown characteristics

Fig. 4.19 shows the typical on- and off-state breakdown characteristics of a

short-channel bar-type MOSFET with 100 nm silane-based gate oxide. The on-state

(VG = 10 V) and off-state (VG = -10 V) breakdown voltages are 92 and 69 V,

respectively. Since the device in our experiment is the basic MOSFET structure

without special withstand voltage design, such as a drift region or field plate in the

common vertical and lateral power MOSFETs, the high drain voltage is just withstood

by the MOS channel and the gate oxide. When a high voltage is applied in the drain

electrode, the gate oxide may be firstly broken down for it is much thinner than the

distance between the drain and the source electrode. It could be confirmed by the

photo in Fig. 7 that the oxide between the gate and the drain was broken down rather

than the region between the drain and the source. Also, the corresponding breakdown


84

fields from the drain to the gate agree quite well with the results in Fig. 4.18. It

demonstrates that the gate oxide dominates the on- and off-state breakdown voltage in

this simple MOSFET structure.

0 20 40 60 80 10010

-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

GGGG

Dra

in C

urr

en

t (A

)

Dain Voltage (V)

Silane 100nm

W/L=56 m/20m

Off-state Vg=-10 V

On-state Vg=10 V

Normal

Break downD S

G

Fig. 4.19 On- and off-state breakdown characteristic of a short-channel bar-type device with 100

nm silane-based oxide.

In general, silane based oxide is more preferred in fabrication of GaN MOSFETs

compare with TEOS-based devices. Also, device with thinner oxide layer (such as 30

nm SiO2) would show nearly enhancement-mode (E-mode) operation although dry

etching damages exist in the semiconductor side.

4.5 Negative threshold voltage and charges near the interface

It is quite interesting that the threshold voltage become deeper then oxide

become thinner. Fig. 4.20 shows the plot of threshold voltage versus oxide thickness.

Figure 4.21 shows the energy band diagram at the just threshold condition with oxide

thickness from 30 to 100 nm based on the data from the silane-based GaN MOSFET.

It describes the situation of a just threshold condition in which the gate metal is biased

with threshold voltage obtained from Fig. 4.15. Near the interface, an n+ GaN layer

may exist and be depleted at the just threshold condition. As described in section 4.3,

the origin of this n+ layer may be the dry etching damages ( such as the VN).


85

0 20 40 60 80 100120

-12

-10

-8

-6

-4

-2

0

2

60 W40 W

Vth

(V

)

Tox

(nm)

20

40

60

20 W

0 20 40 60 80

1

2

3

maximum

minimum

Qp

(q

/cm

2)

Pbias (W)

x1012

Fig. 4 .20 (a) VT versus Tox, (b) equivalent charge density at different etching bias power.

tox= 100 nm

60 nm

30 nm

0 nm

~10 nm

n+ region

Just threshold

condition

+1.36 V

0 V

-1.1 V

Vt E0

Ec

Ef

Ev

SI-GaN ~2 um

-3.0V

Vg

Fig. 4.21 Energy band diagram at just threshold condition

It was quite reasonable that deeper threshold voltage was obtained in device

etched by higher bias power of the ICP system for that higher bias power will made the

ion with higher energy and finally lead stronger ion bombard damages[119]

. Furthermore,

the threshold voltages obtained from devices with different oxide thickness are helpful

to calculate the equivalent charge quantity near the interface. Consider Qeq as the


86

equivalent charge quantity which may include the fixed charges near interface or in the

oxide and the ionized space charges in the depletion region under the threshold

condition, the threshold voltage VT should have relationship with the oxide thickness

Tox described in Eq. 4.1.

schox

r

eq

T VTεε

QV +=

0

, (4.1)

here,

qV ms

sch

, (4.2)

where Φms is the work function difference between the Ni/Au gate and dry etched GaN

surface, ε0 the permittivity in vacuum, εr the relative permittivity of SiO2.

Fig. 4.20 shows the Tox-Vt curves. From the fitting line of data obtained from

devices etched by 20 W and Tox of 30, 60, 90 nm, a Qeq of 0.9×1012

q/cm2 and Vsch of

1.36 V were obtained. Considering the possible negative bulk charge in undoped GaN,

this value would be a little larger[123]

. Also from Fig. 4.20, it can be estimated that the

threshold voltage would be 1.36 V when oxide thickness is close to 0. Theoretically,

this Vsch value equals the barrier height of the Ni Gate on SI-GaN surface etched with

the bias power of 20 W. The typical value of barrier height of the Ni/GaN Schottky

diode are from 1.0 eV to 1.5 eV showing that the method here was quite

reasonable[124,125]

.

Although the samples etched by 40 and 60 W in section 4.4 have only one oxide

thickness (100 nm) in our experiment, the Qeq of them can still be approximately

estimated. It is reasonable that the Vsch values for samples etch by 40 and 60 W should

be in the range from 1.05 V (WNi-χGaN) to 1.36 V for that higher bias power will lead

higher n-type defects density (such as VN) making the surface Fermi level be more

closed to and not beyond the conduction band Ec[119][126]

. Thus the range of the fitting

line of these two conditions should lie in the range shown in Fig. 4.20(a). Finally, the

Qeq value of the three etching condition will lie in the range shown in Fig. 4.20(b).

The charge density resulting from the dry etching damage would be 1.1-1.2×1012

and

2.7-2.75×1012

cm-2

for samples etched by 40 and 60 W, respectively.

Based on the analysis above, it demonstrates that ion bombard damage is


87

dominant reason for these Qeq for much larger density are obtained in samples etched

by higher bias power. It is believed that the dry-etching-induced donor levels (such as

VN) made the surface SI-GaN become n-GaN[126]

. Part of them ionized, depleted and

left the positive ionized space charges at the threshold condition. These charges will

contribute most in the final Qeq. Thus, the recovery or remove of the damaged layer is

key point to realize E-mode operation in the GaN MOSFET with dry recessed gate.

4.6 Surface treatment to realize the E-mode GaN MOSFET

Commonly, two ways to eliminate the damages in the etched surface could be

used, (1) recover the damaged layer by providing enough nitrogen to eliminate the VN

(nitrogen plasma treatment), and (2) remove the damaged layer by wet etching

(NH4OH treatment). In our experiments, nitrogen plasma treatment was done using

ICP system for 5 minutes with bias power of 0 W and ICP power of 100 W. Also,

NH4OH treatment was done for 15 minutes at 100 °C. Except for the surface

treatment process, the other process are based on the standard process described at the

beginning of chapter 4.

-10 -5 0 5 100

10

20

30

40

50

60

70

I D (

A)

VG (V)

1 NH4OH

2 N plasma

3 w/o treatment

12

3

Fig. 4.22 Transfer characteristics of device with different surface treatment condition.

Figure 4.22 shows the transfer of samples with different treatment conditions.

Positive threshold shifts were observed in both N+ plasma and NH4OH treated

samples. The samples treated by NH4OH solution shows E-mode operation with the

threshold voltage of 0 V. The output characteristics are shown in Fig. 4.23,


88

enhancement operation up to VG of 10 V is confirmed.

0 5 10 15 200

1x103

2x103

3x103

4x103

5x103

6x103

7x103

20 W etching bias power

100 nm SiO2

NH4OH treated

Dra

in C

urr

en

t (

A)

Drain Voltage (V)

Vg from -1 V to 15 V step = 2V

Fig. 4.23 Current-Voltage characteristics of the GaN MOSFET.

-10 -5 0 5 10

0

50

100

150

200

etching only

with NH4OH

with N+ plasma

Fig. 4.24 Field-effect mobility characteristics of devices with different surface treatment

condition.

Fig. 4.24 shows the field-effect mobility characteristics of devices with different

surface treatment. The maximum mobilities are 148.12, 146.36 and 141.16 cm2/Vs for

device treated with NH4OH, N+ plasma treatment and without treatment, respectively.

The channel mobilities were improved by both NH4OH and N+ plasma treatment. The


89

NH4OH treatment process is more adoptable for the higher mobility and E-mode

operation.

-20 -15 -10 -5 0 50.4

0.6

0.8

1.0

1.2

1

C/C

ox

Vg (V)

1 ideal curve

2 non-etching

3 etch only

4 with N+ plasma

5 with NH4OH

Cfb

2

5

3

4

Fig. 4.25 high frequency C-V characteristics of devices with different surface treatment

condition.

0.0 0.2 0.4 0.6 0.8 1.010

10

1011

1012

1013

1014

Dit (

cm

-2eV

-1

EC-E

t (eV)

non-etching

etch only

with NH4OH

with N+ plasma

Fig. 4.26 Interface state distribution of devices with different surface treatment condition.

To investigate the detailed interface state distribution information of the device

with these etching and treatment conditions, simple GaN MOS capacitor was

fabricated with on 1×1017

cm-3

Si doped n-GaN. Figure 4.25 shows the high

frequency C-V (HFCV) characteristics of different etching and treatment conditions.

This measurement was tested by HP4284 LCR meter at frequency f = 1 MHz with the


90

small AC single VAC of 25 mV, DC voltage VDC from 5 V to -20 V (accumulation to

depletion) and sweep rate of 0.2 V/s. The interface state density distributions were

calculated by Terman method as shown in Fig. 4.26. In the room-temperature

detectable range of Ec-Et from 0.2 to 0.6 eV calculated from SRH model, the

interface states are increased by dry etching and recovered or removed by both N+

plasma and NH4OH treatment. The NH4OH treatment is still the most adoptable

process for eliminating the higher interface state density of the etched GaN in our

experiment.

In general, the effect of nitrogen plasma treatment and ammonia water treatment

were investigated. These treatments are effective and can recover or remove the dry

etching damaged layer. E-mode GaN MOSFET with the field-effect mobility of 148.12

cm2/Vs was realized by ammonia water treatment. GaN MOS capacitors were used to

investigate the influence of these treatments on the interface state densities by Terman

method. The corresponding and interface state density for the ammonia water treated

sample was around 3×1011

cm-2

eV-1

in the range Ec-Et from 0.2 to 0.6 eV.

4.7 Summary of this chapter

In this chapter, the fabrication process dependency on the performance of the

device were elaborate investigated, including the etching gas, etching bias power,

etching protection mask, oxide type, oxide thickness. The charges near the SiO2/GaN

interface of the GaN MOSFETs with different etching conditions were evaluated. It is

found that stronger bombard damages in dry process will bring more charges near the

interface and finally make the threshold voltage of the device becoming more

negative. The effects of nitrogen plasma treatment and ammonia water treatment were

investigated. These treatments are effective and can recover or remove the dry etching

damaged layer. An E-mode GaN MOSFET with the maximum field-effect mobility of

148.12 cm2/Vs was realized by ammonia water treatment. GaN MOS capacitors were

also prepared to investigate the influence of these treatments on the interface state

densities using Terman method. The corresponding interface state density for the

ammonia water-treated sample was around 3×1011 cm-2

eV-1

in the Ec-Et range from

0.2 to 0.6 eV.


91

Chapter 5 Fabrication of gate-first and self-aligned GaN

FETs

5.1 Problems in ohmic-first MOSFET with recessed gate

In this paper, elaborate research has been done on the GaN MOSFETs on

AlGaN/GaN heterostructure with a recessed gate as shown in Fig. 5.1. As it has been

discussed in chapter 2, this structure is beneficial for the Ohmic electrodes formation

due to the replacement of ion implantation process by the Ohmic formation process

on the heterostructure with high density 2DEG. However, the indispensable gate dry

recess process will bring unavoidable dry etching damages into the MOS interface

and these defects finally affect the performance of the device including the threshold

voltage, the field-effect mobility and the interface state density[87,108]

. These problems

have been investigated detail in chapter 3 and chapter 4.

Series resistance

9 μmGS

Dry etching

damages

OXIDEAlGaN

SI-GaN

Fig. 5.1 Detailed sizes of the device structure.

One problem in both the ion-implantaion-process and the gate-recess-process

based GaN MOSFETs is that the spaces between the ohmic electrodes and the the

electrode have to be large enough to ensure the success of the lithography. The space

is particularly large (9 μm) in the GaN MOSFET on AlGaN/GaN heterostructure with

a recessed gate[88]

. The large spaces will unavoidably act as series resistance and

finally deteriorate the performance of the device by increasing the on-resistance of the

MOSFETs especially when the channel of the MOSFET is relatively short. Also, in an

AlGaN/GaN based HFET, this is may become one of the most important problem

since the channel resistance is relatively low compared with the MOSFET


92

channel[41,45]

.

Also, to fabricate the ohmic electrodes with low contact resistance on the

AlGaN/GaN heterostructure, annealing process at temperature around 800-900 °C is

often necessary. It has been verified that some kinds of oxides, such as Al2O3, would

deteriorate at such a temperature. Al2O3 will recrystallize and become very leaky

when annealing temperature is beyond 800 °C.9) Also, the interface trap density will

become higher than that without annealing.10) Although an ohmic-first process is

adoptable to avoid the annealing process on the gate oxide, it will lead some new

problems. Surface cleaning before oxide deposition will become limited due to the

existence of the ohmic metals, especially in the case that acid and alkali solutions

should be used. The ohmic metal could probably affect the deposition process itself.

There is also a risk to deteriorate the ohmic contact during the oxide deposition

process. To avoid these problems, a gate-first process is required. The gate-first

process is also promising to fabricate self-aligned gate FETs. The key point in

traditional gate-first process is that the gate metal (such as TiN) and oxide should

withstand high temperature (>800 °C) in ohmic annealing process.11) To solve these

problems, development of a gate-first process with non-annealing ohmic process is

necessary.

5.2 The motivation of gate-first and self-aligned GaN FETs

As described in section 5.1, dry etching damage in gate recess process and larger

series resistance resulting from the larger spaces between ohmic and gate electrodes

are two main problems in the GaN MOSFET with recessed gate. The larger spaces

between ohmic and gate electrodes are also one of the main limitation of the drain

current in GaN HFETs[127]

.

For the first problem, new ohmic formation method or undamaged etching

process (such as wet etching) could be help[80]

. To solve the second problem, the

self-aligned process is often adoptable. The traditional self-aligned process required a

high temperature resistant schottky gate since the anneal temperature for ohmic

contacts are usually very high (Fig. 5.2). The degradation of the schottky gate at high

temperature will lead high gate leakage and finally makes this process very

challenging for realizing self-aligned FETs[128]

. To solve this problem, two basic

method could be used, (1) using an high temperature-resisted gate which can bare


93

high temperature in the ohmic annealing process[129]

, and (2) developing a low

temperature ohmic process which could realize the ohmic contact at low

temperature[130]

.

Substrate

Dielectric

Gate

n+

Ion implantation

Fig. 5.2 A typical sef-aligned process for the MSOFET.

In this paper, we select the latter one to develop the gate-first and self-aligned

GaN devices. The low temperature ohmic contacts were simply realized by

plasma-dry-etching assist ohmic process. As described in chapter 4, the dry etching

induced damage can make the etched GaN surface becomes n-type. In the GaN

MOSFET with recessed gate, this phenomenon is harmful for that it will make the

channel mobility lower and the threshold voltage deeper. However, under an extreme

condition of which the dry etching damages was strong enough, the ohmic contact

could directly realized on the dry etched surface without annealing or with annealing

at very low temperature[126]

. Thus, to solve these two problems, the gate-first and

self-aligned process with low-temperature ohmic process could be developed.

5.3 Process development of gate-first GaN MOSFETs

As described above, the gate-first process is necessary part in developing the

self-aligned FETs. Furthermore, to realize the gate-first device with low gate leakage,

the low-temperature ohmic process will be very important. In this section, a gate-first

GaN MOSFET technique on an n+-GaN/semi-insulating (SI)-GaN wafer will be

proposed. In this process, a Ni/Au gate is firstly formed by standard lift-off process.

Then treatment by inductively coupled plasma (ICP) dry etching is conducted. Finally,

ohmic metal of Ti/Al/Ti/Au is deposited to realize ohmic contact.

Before device fabrication, a transmission line model (TLM) structure was firstly


94

investigated to find a proper ICP-dry-etching-assisted non-annealing ohmic process.

In this experiment, four kinds of epitaxial layers deposited on a sapphire substrate,

SI-GaN, n--GaN, n

+-GaN/SI-GaN, and AlGaN/SI-GaN, were used. Metal stack of

Ti/Al/Ti/Au (50 /200/ 40/ 40 nm) was used as the ohmic metal. The doping density of

the SI-GaN, n--GaN, n

+-GaN are <10

14, 1×10

16, and 1×10

19 cm

-3 while the thickness

are 2 μm, 2 μm, and 30 nm, respectively. The AlGaN was unintentionally doped with

thickness of 25 nm. Also, a 5 nm thick GaN cap layer on the AlGaN was designed to

alleviate the current collapse effect when it was used in the AlGaN/GaN HFETs. All

of the n-GaN layers were doped with Si. Different from the unintentionally-doped

GaN which usually shows n-type with doping density of around 1016

cm-3

, the SI-GaN

are C-doped with relatively high resistivity and low free carrier density. Figure 5.3 (a)

shows current-voltage (I-V) characteristics of two electrodes with space of 5 μm on

ICP dry treated n--GaN. The current becomes lager and tends to be with ohmic feature

when higher etching bias power was used in the ICP dry etching system. However,

even with the etching power of 200 W, the linearity of the I-V curve seems not good

enough. Figure 5.3 (b) shows the I-V characteristics of two electrodes on different

wafer treated by the ICP system with etching power of 100 W. Contacts on 1×1019

cm-3

n+-GaN/SI-GaN wafer shows good ohmic property with good linearity while

contacts on n--GaN, SI-GaN and AlGaN show Schottky features with low current.

From the results above, it could be referred that beside the higher etching power, a

higher substrate doping density is also necessary to form the non-annealing ohmic

contact.

Figure 5.3 (c) shows the I-V characteristics of a group of TLM structure formed

on the n+-GaN/SI-GaN sample etched by etching power of 100 W. The corresponding

resistance values are shown in Fig. 5.3 (d) from which contact resistance of 0.48

Ωmm and sheet resistance of 1570 Ω/square are obtained. For comparison, TLM

results on n+-GaN/SI-GaN and AlGaN/SI-GaN sample with 850 °C annealing-ohmic

process are also shown in Fig. 5.3 (d) and the contact resistances are 0.52 and 0.70

Ωmm, respectively. Obviously, the non-annealing ohmic process is competitive to the

traditional annealing ohmic process.

With the non-annealing ohmic process investigated above, a gate-first GaN

MOSFET was fabricated on an n+-GaN/SI-GaN epitaxy deposited on sapphire

substrate. The wafer structure is shown in Fig. 5.4 (a). The n+-GaN is 30 nm thick


95

with a doping density of 1×1019

cm-3

while the SI-GaN is about 2 μm thick. In this

device, the SI-GaN layer is used to form the channel and the n+-GaN layer is used to

form ohmic contacts and reduce the series resistance between the ohmic electrodes

and the MOS channel.

-1 0 1-60

-30

0

30

60

C

urr

en

t (m

A/m

m)

Voltage (V)

200W

100W

0 W

n- GaN

d=5m

etching power

(a)

-1 0 1-60

-30

0

30

60

Cu

rre

nt

(mA

/mm

)

Voltage (V)

AlGaN/SI-GaN

n+ GaN/SI-GaN

n-GaN

SI-GaN

d=5 m

(b)

etching power

= 100 W

-2 0 2-60

-30

0

30

60

Cu

rre

nt

(mA

/mm

)

Voltage (V)

d 5m

10 m

15 m

20 m

25 m

(c)

0 5 10 15 20 25 300

10

20

30

40

50

60

n+-GaN/SI-GaN

dry ethcing

AlGaN/SI-GaN

anneal

n+-GaN/SI-GaN

anneal

RTW

(m

m)

d (m)

(d)

Fig.5.3 I-V and TLM characteristics of different ohmic formation process

The fabrication process was based on a standard photolithography technology.

After device isolation by ICP etching with SiCl4 gas was done with etching depth of

100 nm, the n+-GaN layer in the channel region was recessed for 40 nm with a low

etching rate using ICP with lower etching bias power 20 W to avoid etching damage

(Fig. 5.4 (b)). After the etching, the samples were treated by HNO3 : BHF = 1:1


96

solution to remove the possible Si contamination on the etched surface. Then a

silane-based SiO2 insulator with thickness of 100 nm was deposited using a

plasma-enhanced chemical vapor deposition (PECVD) system (PD-220LC, SAMCO)

and annealed at 1000 °C for 10 minutes in N2 ambient. This annealing temperature

was reported as an optimum condition for the SiO2/GaN MOS sysem. Ni/Au (70/30

nm) was deposited as the gate electrode followed by annealing at 300 °C in N2

ambient (Fig. 5.4 (c)). After that, the oxide layer of the ohmic region was removed by

BHF solution with the gate region covered by photoresist mask. Then treatment of

ICP dry etching system with etching time of 1 minutes was directly done to make

enough damages (mainly nitrogen vacancy) in the contact region to form an ohmic

contact (Fig. 5.4 (d)). The detailed conditions of the dry etching treatment were with

etching gas of SiCl4, chamber pressure of 0.25 Pa, gas flow rate of 3 sccm, ICP power

of 100 W and bias power of 100 W. The estimated etching depth is less than 30 nm

with the two-dimensional electron gas layer remained. Finally, Ti/Al/Ti/Au

(50/200/40/40 nm) ohmic electrodes were deposited by magnetron sputtering at room

temperature (Fig. 5.4 (e)).

n+GaN

SI-GaN

Sapphire

n+GaN

SI-GaN

Sapphire

n+GaN

SI-GaN

Sapphire

SI-GaN

Sapphire

SI-GaN

Sapphire

S

D

G

S DG

Ni/Au

70/30 nm

ICP

etchingPhotoresit

100 nm

SiO2

30 nm

~2 µ m

Dagmaged

layer

~40 nm

Ti/Al/Ti/Au

50/200/40/40 nm

(a) starting epi (b) gate recess

(c) gate deposition (d) ICP treatment

(e) ohmic deposition (f) device pattern

r1

r2r1= 89 µm

r2=183 µm

Buffer layer

Fig.5.4 Key process steps of the gate-first GaN MOSFET flow


97

5.4 Characterization of the gate-first GaN MOSFETs

Considering the gradual channel approximation (GCA) model, a long-channel

ring-type MOSFET (r1 = 89 µm, r2 = 183µm) with channel length L = 94µm and

effective channel width Weff = 819 µm was used for device evaluation (Fig. 5.4 (f)).

The photo of this device is shown in the inset of Fig. 5.5 (b). The surface of the

electrodes is very smooth owing to the non-annealing process.

Fig. 5.5 (a) shows the I-V characteristics of the device with gate voltage Vg from

-4 to 10 V. Good pinch-off characteristics with gate bias up to 10 V are confirmed. Fig.

5.5 (b) shows the transfer characteristics with drain voltage Vd from 0 to 20 V. The

linear curve with constant channel mobility at small Vd and parabolic curve with

pinch-off effect at higher Vd are clearly demonstrated.

0 5 10 15 200

1

2

3

4

5

6

7

(a)

Dra

in C

urr

ent (m

A/m

m)

Drain Voltage (V)

Vg : -4 to 10 step = 2 V

-5 0 5 10 150

1

2

4

5

6

7

(b)

Vd=20 V

Vd=0 V

Dra

in C

urr

ent (m

A/m

m)

Gate Voltage (V)

Vd

step = 1 V

Fig.5.5 Output and transfer characteristics of the gate-first GaN MOSFET.

Fig. 5.6 (a) shows the transfer characteristics of both gate-first and ohmic-first

device. The corresponding field-effect mobility characteristics of the devices at Vd =

0.1 V are shown in Fig. 5.6 (b). The corresponding capacitance-voltage characteristics

are also shown in the inset figure of Fig. 5.6 (b). Due to the dry etching damage in the

gate recess process, the threshold voltages of both devices are about -3 V. The

nitrogen vacancy (VN) caused by the dry etching damage would form an n-type


98

surface layer on the etched surface and should be responsible for the negative

threshold voltage. The gate-first device shows a maximum field-effect mobility of

163.8 cm2/Vs which is relatively higher than that of the ohmic-first device on the

same n+-GaN/SI-GaN wafer.

-10 -5 0 5 100

2x10-2

4x10-2

6x10-2

8x10-2

2

1

Gate-first

RT ohmic

2

Ohmic-first

850C ohmic

V

d=0.1 V

Gate Voltage (V)

Dra

in C

urr

ent (m

A/m

m)

(a)

1

0 10

0

25

50

75

100

125

150

175

-10 -5 0 5 100

10

20

30

Gate Voltage (V)

(b)

1 2

Fie

ld-E

ffect M

obility

(cm

2/Vs)

2

CG (

pF

)

VG (V)

1

Fig.5.6 Transfer, field-effect mobility and C-V characteristics of the gate-first GaN MOSFET.

This novel gate-first GaN MOSFET exhibits not only good performance but also

capability of solving the problem of the leaky gate, such as the Al2O3 gate dielectric，

which has to be annealed at high temperature in the ohmic-first process. Also, the

easier fabrication process makes it available to be used in device fabrication process.

5.5 Process development of self-aligned GaN MOSFETs

Here we propose a novel self-aligned GaN MOSFETs technique. The device is

formed on SI-GaN. The gate formation process is using wet etching process with

negative photoresist and gate metal of Al or Ni. With the negative photoresist

remained, source and drain formation process is using lift-off process with positive

photoresist and ohmic metal of Al or Ti/Au. In this process, the active region was

automatically defined by the combination of positive and negative photoresist, thus

the space between the gate and ohmic electrodes can be minimized, namely the active

region was self-aligned by the gate. Also, treatment of ICP dry etching system with

bias power of 100 W for 30 second before ohmic metal deposition was done which


99

can realize ohmic contact at low temperature and finally make the self-aligned GaN

MOSFET process possible.

(b)

(c)

(a)

(e)

(d)

S G D

SI-GaN/Sapphire

negative PR

positive PR

ICP treatment

damaged

layer

SiO2

SiO2Al gate

S

G

G

D

Fig. 5.7 Process steps of the self-aligned GaN MOSFETs.

The devices are fabricated on the AlGaN/GaN heterostructure wafer with

sapphire substrate. This substrate is original prepared for AlGaN/GaN HEMT device.

From top to bottom, the u-GaN, u-AlGaN and SI-GaN are 5, 20 and 8000 nm,

respectively. To fabricate the MOSFET, the AlGaN layer was firstly removed totally

by using ICP dry etching. The fabrication process was based on the standard

photolithography technologies. The key process steps are shown in Fig. 5.7. After the

gate oxide of 100 nm was deposited by TEOS based PECVD system, 120 nm Al was

sputtered on the whole surface. Then negative photoresist (image reversible 5200E)

was used to define the gate region. The Al pad etchant (70% H3PO4, 20% H2O, 5%

HNO3, 5% HAc) was used to remove the redundant metal. In this process, a T-shape

gate could be automatically formed by negative PR and the gate metal since the wet


100

etching of Al is isotropic (Fig. 5.7 (a)). After that, positive PR was used to define the

active region with the negative PR remained on the gate region (Fig. 5.7 (b)). In this

process, positive PR on the gate was removed but the negative photoresist still remain

for that the UV exposure made the negative PR more difficult to be dissolved by the

developing solution. Then treatment of ICP dry etching system with bias power of 100

W, ICP power of 100 W, gas of SiCl4 time of 30 seconds was done to make enough

damages (mainly nitrogen vacancies) in the active region (Fig. 5.7 (c)) [126]

. Finally,

the ohmic electrodes were formed using Al (120 nm) by lift-off process followed by

500 °C post annealing (PA) in N2 for 1 minute (Fig. 5.7 (e)). A photo of the fabricated

devices is shown in right side of Fig. 5.7 (e).

5.6 Characterization of the self-aligned GaN MOSFETs

Since the most important processes in this device is the low-temperature ohmic

process, the ohmic formation process was firstly investigated including the effect of

ICP treatment and post annealing. Figure 5.8 shows the I-V characteristics between

two Al pad with gap of 5, 10, 15, 20, 25µm. Good linearity was obtained from the I-V

curves showing that the ohmic contacts were realized by this process. Based on the

TLM model, the contact resistance and sheet resistance for this sample are 4.8×10-6

Ωcm2 and 2.33×10

4 Ω/□ calculated from the TLM measurement in Fig. 5.8.

-6 -4 -2 0 2 4 6

-4

-3

-2

-1

0

1

2

3

4

Cu

rre

nt

(mA

)

Voltage (V)

25 m

20 m

15 m

10m

5 m

(a)

0 10 20 30

0

2

4

6

8

Resis

tance (

)

Length (m)

Fig. 5.8 I-V and TLM characteristics


101

0 5 10 15 200

20

40

60

80

100

120

Dra

in C

urr

en

t (m

A/m

m)

Drain Voltage (V)

Vg from -10 to 30 V

step=5 V

-20 -10 0 10 200.0

0.5

1.0

1.5

2.0

Dra

in C

urr

en

t (

A/m

m)

Gate Voltage (V)

Vd=0.1 V

Fig. 5.9 (a) Output characteristics and (b) transfer characteristics of the self-aligned GaN

MSOFET.

-20 -10 0 10 20

0.2

2

Dra

in C

urr

en

t (

A/m

m)

Gate Voltage (V)

-15 -10 -5 0 5 10 1510

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

Ga

te C

urr

en

t (m

A)

Gate Voltage (V)

Fig. 5.10 (a) Subthreshold (b) gate leakage characteristics of the self-aligned GaN MSOFET.

With the ohmic contact formed on ICP treated wafer with 500 °C PA process, the

self-aligned GaN MOSFETs (Fig. 5.7(e)) were fabricated and evaluated. Figure 5.9(a)


102

shows the current-voltage (I-V) characteristics with good pinch-off characteristic of the

device with channel length of 4 µm and gate bias from -3.5 to 30 V. The maximum

drain current of 100 mA/mm was obtained. Figure 5.9 (b) shows the transfer

characteristics at drain voltage of 0.1 V. The threshold voltage of -5 V were obtained.

Figure 5.10 (a) shows the transfer characteristic in semi-log form. The gate leakage

characteristics are shown in Fig. 5.10 (b). The gate leakage of 10-6

mA were obtained

indicating a good dielectric property.

It should be mentioned that the formation of ohmic contact in this device could be

further optimized or replaced by the method of plasma assisted room-temperature

ohmic[126]

. Once the ohmic was further optimized, the performance of this device could

be further improved. Consider the easier process, it is much practical compared with the

the high-temperature self-aligned technique.

5.7 Process development of self-aligned GaN HFETs

In this section, we propose a much practical self-aligned AlGaN/GaN HEMTs

technique. By using both negative and positive photoresist, the ohmic region can

automatically defined making the access space very narrow. Also, by using ICP

treatment, a low temperature ohmic contact (500 °C) and a good schottky gate can be

realized at the same time and finally make this self-aligned HEMT possible.

The devices are fabricated on the AlGaN/GaN heterostructure wafer with

sapphire substrate. A GaN cap layer on the AlGaN was used to eliminate the possible

current collapse effect. From top to bottom, the u-GaN, u-AlGaN and SI-GaN are 5,

20 and 8000 nm, respectively.

The fabrication process was based on the standard photolithography technologies.

The key process steps are shown in Fig. 5.11. After the mesa isolation of 100 nm was

done, 120 nm Al was sputtered on the whole surface. Then negative photoresist

(image reversible 5200E) was used to define the gate region. The Al pad etchant (70%

H3PO4, 20% H2O, 5% HNO3, 5% HAc) was used to remove the redundant metal. In

this process, a T-shape gate could be automatically formed by negative PR and the

gate metal since the wet etching of Al is isotropic (Fig. 5.11 (a)). After that, positive

PR was used to define the active region with the negative PR remained on the gate

region (Fig. 5.11 (b)). In this process, positive PR on the gate was removed but the

negative photoresist still remain for that the UV exposure made the negative PR more


103

difficult to be dissolved by the developing solution. Then treatment of ICP dry etching

system with bias power of 100 W, ICP power of 100 W, gas of SiCl4 time of 30

seconds was done to make enough damages (mainly nitrogen vacancies) in the active

region (Fig. 5.11 (c))[89,119,126]

. Finally, the ohmic electrodes were formed using Al

(120 nm) by lift-off process followed by 500 °C post annealing (PA) in N2 for 1

minute (Fig. 5.11 (e)). A photo of the fabricated devices is shown in Fig. 5.11 (f).

negative PR

(a) (b)

(c)

Ohmic metal

Al 120 nm

(d)

(e)

S G D

positive PR

gate metal

Al 120 nm

AlGaN

ICP treatment

S G D

(f)

S

GD

SI-GaN/Sapphire

2DEG

GaN/AlGaN


104

Fig.5.11 Key process steps of the self-aligned GaN HEMTs.

5.8 Characterization of the self-aligned GaN HFETs

Since the most important processes in this device are the double-layer PR and

low-temperature ohmic process, the lithography status was investigated at first. Figure

5.12 (a) shows a Al gate formed by wet etching with the negative PR masked on the

metal. Due to the isotropic etching, the Al gate edge is a little smaller than the PR

pattern. Figure 5.12 (b) shows that the active region was opened and defined by a

combination of a new layer of positive PR and the existing negative gate PR pattern.

Figure 5.12 (c) shows the electrodes after lift-off process. We can see that the spaces

between ohmic and schottky electrodes are very narrow. It could be more clearly

observed in Fig. 5.12 (d) and (e) with microscope in transmission light mode. The

gate length and the access spaces are about 4 µm and 0.3-0.5 µm, respectively.

Fig. 5.12 Status of the process detail

The low-temperature ohmic formation process was also investigated including

the effect of ICP treatment and post annealing. Figure 5.13 shows the I-V

characteristics between two Al pad with gap of 25µm. The current of sample without

ICP treatment is around 10-8

and 10-4

mA for samples without and with PA. It is low

enough to be used as a schottky gate in HEMT device. For the ICP treated sample, the

current was 1 mA without PA. After the post anneal at 500 °C in N2 for 1 minute, the

I-V characteristic become linear with the current of 10 mA at 1 V. The contact

resistance and sheet resistance for this sample are 2.59×10-4

Ωcm2 and 377.67 Ω/□

calculated from the TLM measurement in the inset figure in Fig. 5.13.


105

-5 -4 -3 -2 -1 0 1 2 3 4 5-10

-5

0

5

10

0 1 2 310

-9

10-5

10-1

103

0 10 20 30

100

200

300

I (

mA

)

V (V)

w/o ICP w/o PA

w/o ICP 500 C PA

with ICP w/o PA

with ICP 500 C PA

R (

)

d (m)

Fig. 5.13 I-V and TLM characteristics

0 2 4 6 8 100

100

200

300

400

500

Vd (V)

I d (

mA

/mm

)

Vg

from -3.5 V to 2 V

step=0.5 V

-5 -4 -3 -2 -1 0 1 2

Vg (V)

Vd=8 V

0

50

100

Gm

(m

s/m

m)

Fig. 5.14 Output and ransfer characteristicsof the self-aligned GaN HEMT

With the ohmic contact formed on ICP treated wafer with 500 °C PA process, the

self-aligned AlGaN/GaN HEMTs (Fig. 1(f)) were fabricated and evaluated. Figure 5.14

(a) shows the current-voltage (I-V) characteristics with good pinch-off characteristic of


106

the device with channel length of 4 µm and gate bias from -3.5 to 2 V. The maximum

drain current of 393 mA/mm was obtained. Figure 5.14 (b) shows the transfer and

transconductance characteristics at drain voltage of 8 V. The threshold voltage of -3 V

and maximum transconductance of 85 mS/mm were obtained. Figure 5.15 (a) shows

the transfer characteristic in semi-log form. The maximum on-off ratio of 105 and

off-state current of 10-3

mA were obtained. The schottky gate characteristics are shown

in Fig. 5.15 (b). The on-voltage of 2.1 V and off-state leakage of 10-4

mA were obtained

indicating a good on-off performance.

-10-8 -6 -4 -2 0 2 4 6 8 1010

-10

10-8

10-6

10-4

10-2

100

102

104

Vd (V)

I g (

mA

)

0

5

10

15

20

25

30

I g (

mA

)

Fig. 5.15 Current-Voltage characteristics of a long channel ring-type MOSFET

It should be mentioned that the formation of ohmic contact in this device could be

further optimized or replaced by the method of a nitrogen plasma assisted

room-temperature ohmic or Mo/Al/Mo/Au 500C ohmic[130,131]

. Once the ohmic was

further optimized, the performance of this device could be further improved. Consider

the easier process, it is much practical compared with the regrown self-aligned

technique.

5.9 Summary of this chapter

Low temperature ohmic process was developed on both SI-GaN and AlGaN.

Self-aligned GaN MOSFET and AlGaN/GaN HEMT were fabricated with a

-6 -5 -4 -3 -2 -1 0 1 2 310

-3

10-2

10-1

100

101

102

103

Vd (V)

I d (

mA

/mm

)

Vd=8 V


107

double-layer photoresist process and low temperature ohmic formation process assisted

by ICP dry etching system. Based on common lithography technology, a narrow access

space of 0.3-0.5 µm between schottky and ohmic electrodes was realized. With 500 °C

N2 annealing, ohmic contact on the ICP treated region and schottky contact on the

untreated region were realized at the same time on AlGaN or SI-GaN. The device

shows good pinch-off characteristics. The maximum output current and

transconductance were 393 mA/mm and 100 mA/mm for the self-aligned HEMT and

MOSFET, respectively. Potential optimization process is adoptable to improve the

performance. The easier fabrication process made these device very practical in

fabrication of self-aligned devices.


108

Chapter 6 Conclusion

In this thesis, a series of research were done to realize, characterize and optimize

the GaN MOSFET. The detail contents are including four basic parts, they are 1)

selection of device structure and realization of GaN MOSFET on AlGaN/GaN

heterostructure; 2) analysis of the problems in the mobility characterization process

and proposing the accurate methods to characterize channel mobility of the GaN

MOSFETs; 3) optimization of the process of GaN MOSFETs on AlGaN/GaN

heterostructure to realized GaN MOSFET with E-mode operation and high

performance; and 4) Attempt of realization self-aligned GaN MOSFET and HEMT in

a new way.

In part one, several possible structures of GaN MOSFETs are given an elaborate

comparison and analysis. GaN MOSFET on AlGaN/GaN heterostructure are designed

and fabricated. Also, some preliminary experiments about the dry recess process are

done including the etching gas flow rate, etching protection mask and the etching

chamber pressure. Finally, a relatively optimum dry recess condition with SiO2

etching protection mask, etching gas flow of 3 sccm, etching chamber pressure of

0.25 pa was confirmed.

In part two, the problems in characterization of GaN MOSFETs were analyzed

based on our experiments. It is found the characterized mobility will be over- or

underestimated by several problems in GaN MSOFET. A phenomenon of parallel

channel caused by worse field isolation at the gate pad outside the channel was found in

bar-type GaN MOSFETs based on AlGaN/GaN heterostructure. Also, the variation of

channel length extracted by electrical measurement was found. It will lead an obvious

underestimation on mobility, especially in the case of short channel MOSFETs. we

have verified and analyzed these phenomena and presented several improved methods

to characterize the mobility of MOSFETs. The mobility of 130 cm2/Vs extracted by our

method agreed quite well with that of the long channel ring type MOSFET which was

thought to be reasonable showing theses method are effective..

In part three, in order to obtain an E-mode GaN MOSFET with high performance,

such as higher channel mobility and lower interface state density, process


109

optimization including the etching gas, etching bias power, etching protection mask,

oxide type, oxide thickness of the GaN MOSFETs are investigated and analyzed. The

charges near the SiO2/GaN interface of the GaN MOSFETs with different etching

conditions were evaluated and analyzed. It is found that stronger bombard damages in

dry process will bring more charges near the interface and finally make the threshold

voltage of the device becoming more negative. To solve this problem, the nitrogen

plasma treatment and ammonia water treatment were used. It is found that these

treatments are effective and can recover or remove the dry etching damaged layer.

Finally, an E-mode GaN MOSFET with the maximum field-effect mobility of 148.12

cm2/Vs was realized by ammonia water treatment. In the Ec-Et range from 0.2 to 0.6

eV, the interface state density for the ammonia water treated sample was around

3×1011

cm-2

eV-1

by using Terman method.

In part four, the drawbacks of the ohmic-first GaN MOSFET with recessed gate

were analyzed and a new way to fabricate the gate-first GaN MOSFET, self-aligned

GaN MOSFET and AlGaN/GaN HEMT were put forward by using the

room-temperature and low temperature ohmic formation process assisted by ICP dry

etching system. The fabricated gate-first GaN MOSFET shows higher performance

with channel mobility of 163.8 cm2/Vs. By using the common lithography technology,

a narrow access space of 0.3-0.5 µm between schottky and ohmic electrodes was

realized. Ohmic contact on the ICP treated region and schottky contact on the untreated

region were realized at the same time by the ICP assisted low temperature ohmic

process. The fabricated self-aligned devices show good pinch-off characteristics. The

maximum output current and transconductance were 393 mA/mm and 100 mA/mm for

the self-aligned HEMT and MOSFET, respectively, showing that these processes are

promising in fabrication of self-aligned GaN FETs.

Although strenuous efforts have been done during the experiments and the

completion of the thesis, some results of these experiments may not outstanding or

even debatable. What I hoped is that it could do a little help or significance to people

who need them.


110

Publications

1 Qingpeng Wang, Ying Jiang, Liuan Li, Dejun Wang, Yasuo Ohno and Jin-Ping Ao.

Characterization of GaN MOSFETs on AlGaN/GaN heterostructure with variation in

Channel Dimensions. Electron Devices, IEEE Transactions on, 2014, 61(2): 498.

2 Qingpeng Wang, Ying Jiang, Jiaqi Zhang, Liuan Li, Kazuya Kawaharada, Dejun Wang,

and Jin-Ping Ao. Gate-first GaN MOSFET with dry-etching-assisted non-annealing Ohmic

process. Applied Physics Express, 2015, 8: 046501.

3 Qingpeng Wang, Ying Jiang, Takahiro Miyashita, Shin-ichi Motoyama, Liuan Li, Dejun

Wang, Jin-Ping Ao and Yasuo Ohno. Process dependency on threshold voltage of GaN

MOSFETs on AlGaN/GaN Heterostructure. Solid State electronics, 2014, 99: 59.

4 Qingpeng Wang, Ying Jiang, Jiaqi Zhang, Kazuya Kawaharada, Liuan Li, Dejun Wang

and Wang, Jin-Ping Ao. Effects of recess process and surface treatment on the threshold

voltage of GaN MOSFETs fabricated on a AlGaN/GaN heterostructure. Semiconductor

Science and Technology, 2015, 30(6): 065004.

5 Qingpeng Wang, Ying Jiang, Jiaqi Zhang, Kazuya Kawaharada, Liuan Li, Dejun Wang

and Wang, Jin-Ping Ao. A self-aligned gate GaN MOSFET using ICP-assisted

low-temperature ohmic process. Semiconductor Science and Technology, 2015, 30.7

(2015): 075003.

6 Qingpeng Wang, Kentaro Tamai, Takahiro Miyashita, Shin-ichi Motoyama, Dejun Wang,

Jin-Ping Ao and Yasuo Ohno. Influence of dry recess process on enhancement-mode GaN

metal-oxide-semiconductor field-effect transistors. Japanese Journal of Applied Physics.

2013, 52: 01AG02.

7 Qingpeng Wang, Ying Jinag, et al., GaN MOSFETs on AlGaN/GaN heterostructure with

recessed gate, Frontiers of Materials Science. vol. 9, no. 2, pp. 151-155.

8 王青鹏, 江滢, 敖金平, 王德君. GaN MOSFET的设计制作及其表征. 电力电子技术,

2012, 46: 81-83. (In Chinese)


111

9 Qingpeng Wang, Ying Jiang, Takahiro Miyashita, Shin-ichi Motoyama, Liuan Li, Dejun

Wang, Jin-Ping Ao and Yasuo Ohno. Process dependency on threshold voltage of GaN

MOSFETs on AlGaN/GaN Heterostructure, 10th

Topical Workshop on Heterostructure

Microelectronics. Hakodate, 2013, Sep. 2-5.

10 Qingpeng Wang, Ying Jiang, Kentaro Tamai, Takahiro Miyashita, Shin-ichi Motoyama,

Dejun Wang, Jin-Ping Ao and Yasuo Ohno. Oxide Thickness on threshold voltage of GaN

MOSFETs on AlGaN/GaN Heterostructure. 60th

JSAP spring meeting, 2013,

28p-G11-16.

11 Qingpeng Wang, Kentaro tamai, Takahiro Miyashita, Shin-ichi Motoyama, Dejun Wang,

Jing-ping Ao, Yasuo Ohno. The 4th

International Symposium on Advanced Plasma Science

and its Applications for Nitrides and Nanomaterials, 2012, 54-54.

12 Qingpeng Wang, Kentaro tamai, Takahiro Miyashita, Shin-ichi Motoyama, Dejun Wang,

Jing-ping Ao, Yasuo Ohno. The 59th JSAP spring meeting, 2012, 17p-E3-6.

13 Ying Jiang, Qingpeng Wang, Kentaro Tamai, Satoko Shinkai, Takahiro Miyashita,

Shin-ichi Motoyama, Dejun Wang, Jin-Ping Ao, and Yasuo Ohno. Device Isolation for

GaN MOSFETs with Boron Ion Implantaion. Semiconductor Science and Technology,

2014, 29(5): 055002.

14 Ying Jiang, Qingpeng Wang, Fuzhe Zhang, Liuan Li, Deqiu Zhou, Yang Liu, Dejun

Wang and Jin-Ping Ao. Reduction of leakage current by O2 plasma treatment for device

isolation of AlGaN/GaN heterojunction field-effect transistors. Applied Surface Science,

2015 (In press)

15 Ying Jiang, Qingpeng Wang, Kentaro Tamai, Takahiro Miyashita, Shin-ichi Motoyama,

Dejun Wang, Jin-Ping Ao, and Yasuo Ohno. GaN MOSFET with Boron Trichloride-Based

Dry Recess Process. Journal of Physics: Conference Series (IOP), 2013, 441: 012025.



GaN MOSFETs with Boron Ion Implantaion. 5th

International Symposium on Advanced

Plasma Science and its Applications for Nitrides and Nanomaterials, 2013, Jan.

28-Feb. 1, P3114B-LN.


112

17 Ying Jiang, Qingpeng Wang, Kentaro Tamai, Takahiro Miyashita, Shin-ichi Motoyama,

Dejun Wang, Jin-Ping Ao, and Yasuo Ohno. GaN MOSFET with Boron Trichloride-Based

Dry Recess Process. 11th

Asia-Pacific Conference on Plasma Science and Technology

and 25th

Symposium on Plasma Science for Materials, 2012, Oct. 2-5, 3-P13.



GaN MOSFETs with Boron Ion Implantaion. 60th

JSAP spring meeting, 2013,

28p-G11-6.

19 Liuan Li, Ryosuke Nakamura, Qingpeng Wang, Ying Jiang and Jin-Ping Ao. Synthesis of

titanium nitride for self-aligned gate AlGaN/GaN heterostructure field-effect transistor.

Nanoscale Research Letters. 2014, 9: 590.

20 Liuan Li, Yonggang Xu, Qingpeng Wang, Ryosuke Nakamura, Ying Jiang and Jin-Ping

Ao. Metal-oxide-semiconductor AlGaN/GaN heterostructure field-effect transistors using

TiN/AlO stack gate layer deposited by reactive sputtering. Semiconductor Science and

Technology, 2015, 30(1): 015019.


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Acknowledgement

This paper is carried out during my study in the Global Double Degree Program

in Department of Electrical and Electronic Engineering, Faculty of Engineering,

University of Tokushima, and School of Electronic Science and Technology, Faculty

of Electronic Information and Electrical Engineering, Dalian University of

Technology, from October of 2012 to June of 2015. On the completion of my thesis, I

would like to express my gratitude to all those whose kindness and advice have made

this work possible.

First and foremost, I would like to express my sincere gratitude to my

supervisors, Associate Professor Jin-Ping Ao in the University of Tokushima and

Professor Dejun Wang, in Dalian University of Technology, for their invaluable

guidance and encouragement extended throughout the study. They are respectable,

responsible and resourceful scholars, who have provided me with valuable guidance

in every stage of writing this thesis. Without their enlightening instruction, impressive

kindness and patience, I could not have completed my thesis. Their keen and vigorous

academic observation enlightens me not only in this thesis but also in my future study.

I would like to express my sincere gratitude to my cooperative researchers,

Professor Yasuo Ohno from e-device Lab Inc., Mr. Shin-ichi Motoyama, Mr. Takahiro

Miyashita from SAMCO Inc. for their instructive suggestion and excellent work in

this research.

I would like to express my sincere gratitude to Ying Jiang, Liuan Li, Jiaqi Zhang,

Xiaochen Xing, Pangpang Wang, Kazuya Kawaharada, Helmi Mohammed, Shyota

Kakuyama, Kentaro Tamai and those who acted as my research partner, Japanese tutor

and best friends in Tokushima. Owing to their unconditional help on both life and

study, I could successfully accomplish my research work and thesis in the University

of Tokushima.

I would like to gratefully acknowledge Department of Electrical and Electronic

Engineering, Faculty of Engineering, University of Tokushima for providing the

resources and needs during the thesis. I would like to extend my appreciation to

Professor Nagase Masao, Professor Kaoru Ohya, Professor Shiro Sakai, Associate

Professor Yoshiki Naoi, Associate Professor Katsushi Nishino, Associate Professor


125

Kikuo Tominaga, Assistant Professor Retsuo Kawakami, Technician Azuma Chiri,

Takeshi Inaoka, Kitajima and Takechi for their unconditional help during this

research.

I would like to thank all the colleagues of Ao laboratory for their conversation

scientific and otherwise for making the laboratory such an enjoyable place to work.

I would like to thank Ms. Sawa Asada, Mr. Pangpang Wang and Mr. Haitao Wu

of CICEE of University of Tokushima and Ms. Hiroko Sato of International House of

University of Tokushima for their unconditional help to my life during my study in

Tokushima.

Finally, I would like to express my deepest gratitude towards my parents for their

unconditional support, understanding and enduring patience.

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