Design Rules & Fabrication

Somayyeh KoohiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes prepared by

author

Topics

� Design rules and fabrication� SCMOS scalable design rules� Stick diagrams

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� Stick diagrams

Why we need design rules

� Masks are tooling for manufacturing� Manufacturing processes have inherent limitations

in accuracyi l if f k hi h ill

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� Design rules specify geometry of masks which willprovide reasonable yields� Spacing� Minimum-width rule� Avoid small negative feature

� Design rules are determined by experience

Manufacturing problems� Photoresist shrinkage � tearing� Variations in material mask� Variations in temperature

V i ti i id thi k

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� Variations in oxide thickness� Variation in Vt

� Impurities� Variations between lots

� Lot consists of multiple wafer

� Variations across a wafer

Transistor problems

� Variations in threshold voltage:�oxide thickness� ion implantation

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� ion implantation�poly variations

� Changes in source/drain diffusion overlap�Variation in effective channel length

� Variations in substrate

Wiring problems

� Diffusion:� Changes in doping � variations in resistance, capacitance

� Poly, metal:

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� Variations in height, width � variations in resistance,capacitance

� Shorts and opens:

Oxide problems

� Variations in height� Lack of planarity �step coverage

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metal 1metal 2

metal 2

Via problems

� Via may not be cut all the way through� Undersize via has too much resistance� Via may be too large and create short

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� Via may be too large and create short

Topics

� Design rules and fabrication� SCMOS scalable design rules� Stick diagrams

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� Stick diagrams

MOSIS SCMOS design rules

1. Designed to scale across a wide range oftechnologies

2 Designed to support multiple vendors

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2. Designed to support multiple vendors3. Designed for educational use� Therefore, fairly conservative

λ and design rules

� 2λ is the size of a minimum feature� Specifying λ particularizes the scalable rules

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� Parasitics are generally not specified in λ units� µm-based design vs. λ-based design

Scaling

� Scale all chip parameters by x:� W’ -> W/x, L’ -> L/x, V’ -> V/x, etc.

� Transistor current shrinks:� I’/I = 1/x (EQ. 2-28)

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( )� Capacitance shrinks� Resistance unchanged

� So chip speeds up� (C’V’/I’)/(CV/I) = 1/x

� Shrinking makes chip faster and smaller� More later…

Wires

metal 36

metal 23

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metal 13

pdiff/ndiff3

poly2

Transistors

2

3 2

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3

15

Vias

� Types of via:�metal1/diff�metal1/poly

41

4

2

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�metal1/poly�metal1/metal2

� No direct connection between metal2/metal3and poly�Connection through metal1

Metal 3 via

� Type: metal3/metal2� Rules:

�cut: 3 x 3

51

3

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�cut: 3 x 3�overlap by metal2: 1�minimum spacing: 3�minimum spacing to via1: 2

Tub tie

41

� Tub to power supply

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1

Spacings

� Diffusion/diffusion: 3� Poly/poly: 2� Poly/diffusion: 1

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y� Via/via: 2� Metal1/metal1: 3� Metal2/metal2: 4� Metal3/metal3: 4� Diffusion/tub wall: 5

Topics

� Design rules and fabrication� SCMOS scalable design rules� Stick diagrams

Modern VLSI Design: Chap2 19 of 31Sharif University of Technology

� Stick diagrams

Stick diagrams

� Is a cartoon of a layout� Shows

� All components/vias (except possibly tub ties)� Relative placement

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� Relative placement� Not show

� Exact placement� Transistor sizes� Wire lengths� Wire widths� Tub boundaries

Stick diagrams (cont’d)

� Just horizontal & vertical lines� Crossing materials:

�Similar: Connected

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�Similar: Connected�Dissimilar: Unconnected

� Unless connection is established through a via

Stick diagrams (cont’d)

m2 m1 poly ndiff pdiff

Short O O O O m2

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O Short O O O m1

O O Short NMOS PMOS poly

O O O Short illegal ndiff

O O O O Short pdiff

Stick layers

metal 3

metal 2

metal 1

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metal 1

poly

ndiff

pdiff

Dynamic latch stick diagram

VDD

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in

VSSphiphi’

out

Sticks design of multiplexer

� Start with NAND gate:+

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ab

out

NAND sticksVDD

a

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VSS

out

b

One-bit mux sticks

VDD

t

a

t

a a

ai

bi

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VSS

N1(NAND)se

lect

’ out

b

N1(NAND)

out

b

N1(NAND)

out

b

sele

ct

3-bit mux sticks

m2(one-bit-mux)select’ select VDD

VSSoi

ai

bi

select’ select

a2

b2

o2

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m2(one-bit-mux)select’ select VDD

VSSoi

ai

bi

m2(one-bit-mux)select’ select VDD

VSSoi

ai

bi

a1

b1

a0

b0

o1

o0

Layout design and analysis tools

� Layout editors are interactive tools� Magic� L-edit

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� Design rule checkers are generally batch� identify DRC errors on the layout

� Circuit extractors extract the netlist from the layout� Connectivity verification systems (CVS) compare

extracted and original netlists

Automatic layout

� Cell generators (macrocell generators) createoptimized layouts for ALUs, etc.

� Standard cell/sea-of-gates layout creates layout

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� Standard cell/sea of gates layout creates layoutfrom pre-designed cells + custom routing�Sea-of-gates allows routing over the cell

Standard cell layout

rea

routing area routing area

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rout

ing

area

routing area

ting area