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DESIGN OF WISHBONE INTERFACED I2CMASTER

CORE CONTROLLER USING VERILOG

Ramesh Babu Dasara1, Y. Chandra Sekhar Reddy

2

1Pursuing M.tech,

2Assistant Professor, from Nalanda Institute of Engineering and Technology

(NIET), Siddharth Nagar, Kantepudi village, Sattenepalli Mandal, Guntur Dist.,A.P. (India)

ABSTRACT

In this paper we are implementing one of the serial communication protocol called Inter integrated circuit (I2C)

master controller. The protocol is made of set of standards with the master and slave configuration to allow

data transfer. The I2C master with wishbone controller is implemented in Verilog HDL. The modules are

synthesized in Xilinx 13.2i. Then simulated to observe the operation of the Master controller and wishbone

controller which performs high speed data transfer in presence of master or slave. This yields higher speed data

transfer over the network.

Keywords: Master,Wishbone, SDA,SCK,SLAVE

I. INTRODUCTION

In electronic world to make communication between any two digital hardware devices needs serial

communication standards. There are several communication standards are RS232, RS435, and SPI to make high

speed and low speed data transfer. To implement protocols actually we require more number of pin connections,

whereas the size of IC gradually decreasing so we need a protocol that can have minimum number of pin

connections. The protocols existed earlier are SPI, MOCROWIRE and USB needs point to point connection

such that needs multiplexing of data and address. The proposed protocol requires only two lines two

communicate with nay number of devices while other needs more number of pin connections. The I2c is best

suited for medium range communication between the circuit boards within the equipment. This is also used for

control applications where certain device to be added and removed. The I2C is also used to communicate

between the circuits using a cable or without cable. The I2C will have master and slave, the master whichsends

data to slave will generate responses based on master controller signals.

II. I2CPROTOCOL

The I2C is vital for implementing low a data rate communications. The I2C bus made of bidirectional lines with

pull up resistors. I2c will allow data transfer between many devices. It will allow us to connect certain devices to

it with each and unique address to identify them. The data and address are the inputs to the controller, the

external inputs clk ,rst which starts the data transfer. The r/w signal is used to indicate which in transmission

either master or slave.

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Fig 2.1 SDA AND SCK

The physical I2C bus consists of simply 2 wires,called SCL and SDA. SCL is that the clock line. It is used to

synchronize all information transfers over the I2C bus. SDA is that the information line. The SCL and SDA

lines are connected to all or any devices on the I2C bus. As both SCL and SDA lines square measure "open

drain" drivers they're pulled up victimisation pull up resistors.

The I2C bus is claimed to be idle once each SCL and SDA square measure at logic one level. once the master

(controller) desires to transmit information to a slave (DS1307) it begins by issuance a begin sequence on the

I2C bus, that may be a high to low transition on the SDA line whereas the SCL line is high as shown in Fig–

2(a).The bus is taken into account to be busy once theSTART condition. once the beginning condition,slave

address is distributed by the master. The slave devicewhose address matches the address that's being sent out by

the master can respond with Associate in NursingMacknowledgement bit on the SDA line by propulsion the

SDA line low. information is transferred in sequences of eight bits. The bits square measure placed on the SDA

line beginning with the savings bank (Most vital Bit). for each eight bits transferred, the slave device receiving

the info sends back Associate in Nursing acknowledge bit, therefore there are literally 9 SCL clock pulses to

transfer every eight bit computer memory unit of knowledge this is shown in Fig-3. If the receiving device sends

back an occasional ACK bit, then it's received the info and is prepared to simply accept another computer

memory unit. If it sends back a high then it's indicating it cannot settle for from now on data and also the master

ought to terminate the transfer by sending a STOP sequence.

In Fig-2.1 that shows the STOP sequence, wherever the SDA line is driven low whereas SCL line is high. This

signals the top of the group action with the slave device.

III. PROPOSED I2C WITH WISHBONE

The I2C master core supports the vital options represented within the I2C specification and is appropriate for

many applicationsinvolving I2C slave management. the planning responds to the read/write cycles initiated by

the microcontrollerThrough the wishing bone interface. It provides the right sequences of commands and

knowledge to the I2C slave device and then transfers the specified knowledge from the I2C slave device through

the 2 open-drain wires. The I2C master with wishing bone interface offloads the microcontroller from desperate

to deal several details of the I2C commands and operation sequences. Table one lists the I/O ports of the

planning. The signals ending in “_i” indicate Associate in Nursing input and people ending in “_o” indicatean

output. All signals on wishing bone facet square measure synchronous to the master clock. the 2 I2C wires, scl

and sda, should be open-drain signals and square measure outwardly force up to Vcc through resistors.

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Table3.1 Wishbone Signal Description

The design has four main modules as shown in Figure3.1. These embrace one ranking module and 3 lower-level

modules, that ar the register module, the computer memory unit module and somewhat module.In addition to

connecting all the useful blocks along, this module generates byte-wide knowledge, acknowledgement, and

interrupt for the wishing bone interface. reckoning on the parameter ARST_LVL, the reset polarity is

determined and distributed to any or all the modules The 2bit by 8bit registers are presnet in the I2C core. This

registers addresses will not be used for future reference.

Table 3.2 Internal Registers

The Prescale Register (address = 0x00 and 0x01) is employed to prescale the scl clock line supported the master

clock. Since the planning is driven by a (5 x scl frequency) internally, the prescale register is programmed in

keeping with the equation [master clock frequency / (5 x (sclk frequency)) - 1].

The content of this register will solely be changedwhen the core isn't enabled. Only 2 bits of the management

Register (address = 0x01) ar used for this style. The MSB of this register is that the

most critical one as a result of it allows or disables the complete I2C core. The core won't reply to any command

unless this bit is ready.The Transmit Register and therefore the Receive Register share an equivalent address

(address = 0x30) reckoning on the direction of information transfer. the info to be transmitted via I2C are keep

within the Transmit Register, whereas the computer memory unit received via I2C is obtainable within the

Receive register.

The standing Register and therefore the Command Register share an equivalent address (address = 0x04). The

standing Registerallows the watching of the I2C operations, whereas the Command Register stores consecutive

command for consecutive I2C operation. in contrast to the remainder of the registers, the bits within the

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Command Register ar cleared mechanically when every operation. so this register has got to be written for every

begin, write, read, or stop of the I2C operation. Table 3 provides a close description of every bit within the

internal registers

Fig 3.1 Block Daigram of the I2C Module

State1 : AN idle condition: I2C bus doesn’t perform any operation. (SCL and SDA remains high).

State2 : begin condition: master initiates information transmission by providing begin (SCL is high andSDA is

from high to low).

State 3 : Slave address - write: master sends theslave address-write (11010000) to the slave.

State 4 : If the slave address matches with the slave, it sends AN acknowledgement bit in responseto the master.

State 5 : eight Bit Register Address[12] are going to be transmitted to the slave. once more acknowledgement is

sent to the master by the slave.

State 6 : information to be transmitted is distributed to the slave by the master. once receiving the information,

slave acknowledges the master.

State seven : Stop condition: Slave sends a stop bit to the master to terminate the communication (SCL is high

and SDA is from Low to high). For playacting browse operation, write operation is performed 1st then browse

operation is completed.

Slave address for browse is 11010001. (State seven won'tbe performed for browse operation)

State eight : Master transmits slave address for browse operation to the slave.

State nine : Master receives the information from the slave and acknowledges the slave. State ten : Master sends

a STOP bit to terminate the connection (SCL is high and SDA is from Low to high).

Fig-

IV. SIMULATION RESULTS

In this project we are implementing I2C master with Wish bone interface such that wishbone bus is the medium

that will be used to connect between master and slave. That data which was sent by master will be given to the

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wishbone that will grant the permission to access the slave. There is no direct connection between the master

and slave. The master and its internal

Modules are designed using Verilog HDL. The modules synthesized in Xilinx ISE 13.2i. The repots and

simulation parameters are shown below

Top Level schematic:

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Simulation results:

I2C master with read and write enable

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I2c master with wishbone for read and write

V. CONCLUSION

In this project we have designed I2C master controller with wishbone interface. This combination will improve

the performance of the design due to multi number of master and slaves that we can connect to the wishbone

interface. The wishbone interface is a powerful media that will allow and control each devices connected to it

such we can perform full duplex communication with only two signals which makes the design efficient than

existed design. The wishbone interface, I2c master are designed using Verilog HDL. The RTL Design

description is synthesised and simulated to check the operation in Xilinx ISE 13.2i.

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REFERENCES

[1]. BollamEswari, N.Ponmagal, K.Preethi, S.G.Sreejeesh Implementation of I2C Master Bus Controlleron

FPGA

[2] Philips Semiconductor “I2C Bus Specification”version 2. 1, January 2000

[3] Raj kamal ,“Embedded system: Architecture programming and Design”,Tata McGraw Hill,2008.

[4] Stuart Sutherland, “Verilog® HDL Quick Reference Guide”, IEEE Std 1364-2001.

[5] Maxim integrated “DS1307 64 x 8, Serial, I2C Real Time Clock”, 2008.

[6] Pong P.Chu, “FPGA Prototyping By Verilog Examples:Xilinx Spartan – 3 Version” Wiley,2008.

[7] Mano,Ciletti, “Digital Design”Pearson Education India,edition 4,2008.

[8] M.Morris Mano, “Digital Design” EBSCO publishing.Inc., 2002.

[9] Frank Vahid, “Digital Design with RTL Design, Verilog and VHDL”VP and Executive publisher, 2010.

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AUTHOR DETAILS

RAMESH BABU DASARA is pursuing M.tech from Nalanda Institute of Engineering and

Technology. He completed his B.tech from Electronics and communication Engineering. His

research of interest includes CMOS DIGITAL, Analog CMOS, VLSI design etc.

Y. CHANDRA SEKHAR REDDYis working as Assistant Professor in Nalanda Institute of

Engineering and Technology. He completed his Post-graduation in VLSI. He has one year of

experience Academic Research. He is expert in Digital design and VLSI system design,

CMOS mixed signals.