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Gookyi Dennis A. N.Gookyi Dennis A. N.

SoC Design Lab.SoC Design Lab.

October.17.2014

ContentContent Round-Robin Arbiter Module

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Round-Robin ArbiterRound-Robin Arbiter In a shared bus, the arbiter determines which master

can use the bus The bus is granted on a rotary basis much like the

four position rotary switch shown below:

When a master relinquishes the bus, the switch is turned to the next position and the bus is granted to the master on the level

In this way all masters are granted the bus on an equal basis

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MASTER #0

MASTER #3

MASTER #2

MASTER #1

Round-Robin ArbiterRound-Robin Arbiter Arbiter general topology:

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LASMASSTATEMACHINE

REGISTER

COMCYCLOGIC

ENCODERLOGIC

ARBITRATIONLOGIC

GNT3 GNT3GNT2GNT1GNT0

GNT2GNT1GNT0

GNT(1..0)

CLK

CLK

CLK

LMAS0LMAS1

RST

RST_I

CYC3CYC2CYC1CYC0

COMCYC

LASMAS

CE

Round-Robin ArbiterRound-Robin Arbiter Bus requests arrive at inputs [ CYC0] to [CYC3] If bus is free, one of the 4 grant lines ([GNT0] to

[GNT1]) is asserted which corresponds to the request signals

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Round-Robin Arbiter: COMCYCRound-Robin Arbiter: COMCYC The [COMCYC] indicates whether the bus is free or

busy It is asserted whenever a master has both requested

the bus and has been granted the bus by the arbiter

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Round-Robin Arbiter: COMCYCRound-Robin Arbiter: COMCYC Inputs and outputs:

COMCYC logic diagram:

COMCYC = (CYC3 & GNT3)||(CYC2 & GNT2)|| (CYC1 & GNT1)||(CYC0 & GNT0);

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Inputs Output

CYC_3, CYC_2, CYC_1, CYC_0GNT_3, GNT_2, GNT_1, GNT_0

COMCYC

CYC_3

CYC_2

GNT_2CYC_1

GNT_1

CYC_0

GNT_0

GNT_3

COMCYC

Round-Robin Arbiter: Encoder Round-Robin Arbiter: Encoder LogicLogic Grant line [GNT0] to [GNT3] are encoded as

[GNT(1..0)] This is used with the [COMCYC] signal to indicate

which master has been granted the bus When [COMCYC] is asserted, the master located on

[GNT(1..0)] is granted the bus

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Round-Robin Arbiter: Encoder Round-Robin Arbiter: Encoder LogicLogic Inputs and outputs:

Encoder logic diagram:

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Inputs Outputs

GNT_3, GNT_2, GNT_1, GNT_0

GNT[1], GNT[0]

GNT_3

GNT_1GNT[0] = GNT3 || GNT1

GNT[1] = GNT_2 || GNT_3GNT_2

GNT_3 GNT_2 GNT_1 GNT_0 GNT[1] GNT[0]

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

0

0

0

0

0

Round-Robin Arbiter: LASMASRound-Robin Arbiter: LASMAS Round-robin arbiters keep track of the level of the

previous master The level is saved in a register that latches the state

of grant signals [GNT(1..0)] The register latches the grant signal when indicated

by the LASMAS state machine

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CE

Round-Robin Arbiter: LASMASRound-Robin Arbiter: LASMAS LASMAS state machine: state diagram

Input logic: BEG= (CYC0 || CYC1 || CYC2 || CYC3) & (~COMCYC);

From the state diagram:EDG= ( BEG & ~EDG & LASMAS) || ( BEG & EDG & ~LASMAS );LASMAS = ( BEG & ~EDG & ~LASMAS ); 11

Input = BEG

State = {EDG,LASMAS}

CYC0CYC1

CYC2CYC3

COMCYCBEG

Round-Robin Arbiter: Bus Round-Robin Arbiter: Bus TopologyTopology The arbitration logic is as below:

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MASTER #0

MASTER #3

MASTER #2

MASTER #1


GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 )|| ( ~RST & COMCYC & GNT0 );

GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 )|| ( ~RST & COMCYC & GNT1 );

GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & COMCYC & GNT2 );

GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 )

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MASTER #0

MASTER #3

MASTER #2

MASTER #1






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MASTER #0

MASTER #3

MASTER #2

MASTER #1






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MASTER #0

MASTER #3

MASTER #2

MASTER #1

Round-Robin ArbiterRound-Robin Arbiter Code

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Round-Robin ArbiterRound-Robin Arbiter Code:

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Round-Robin ArbiterRound-Robin Arbiter RTL schematic

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Round-Robin ArbiterRound-Robin Arbiter Testbench

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Round-Robin Arbiter: Round-Robin Arbiter: waveformwaveform Cyc0 request and is granted the bus

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cyc0 is granted the bus

Round-Robin Arbiter: Round-Robin Arbiter: waveformwaveform Cyc1 and cyc2 both request the bus at the same time

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comcyc is negated to indicate that the bus is free

Round-Robin Arbiter: Round-Robin Arbiter: waveformwaveform Bus granted to cyc1

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Bus granted to cyc1 because it is next in line

Round-Robin Arbiter: Round-Robin Arbiter: waveformwaveform Cyc3 request for bus and is granted

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Bus granted to cyc3

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