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Theses and Dissertations

1-1-1982

Design of a microprocessor-based electricitydemand controller for residential use.James Allen Butt

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DESIGN OF A MICROPROCESSOR-BASED

ELECTRICITY DEMAND CONTROLLER

FOR RESIDENTIAL USE

by

JAMES ALLEN BUTT

A Thesis

Presented to the Graduate Committee

of Lehigh University

in Candidacy for the Degree of _

Master of Science

in

Electrical Engineering

Lehigh University

1932

ProQuest Number: EP76729

All rights reserved

INFORMATION TO ALL USERS The quality of this reproduction is dependent upon the quality of the copy submitted.

In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if material had to be removed,

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ProQuest EP76729

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CERTIFICATE OF APPROVAL

This Thesis is accepted and approved

in partial fulfillment of the requirements

for the degree of

Master of Science

in

Electrical Engineering

(date)

Chairman of Department

-ii-

ACKNOWLEDGMENTS

~he author would like to thank Dr. Kalyan Mondal, assistant

professor of Electrical ana Computer Engineerin~, for his advice

throughout this thesis project, and for his initial proposal which

helped obtain the research grant. I would also like to thank Mr.

Preston L. Roberts, Pennsylvania Power and LiP,ht Co., for his valuable

inputs and experience. Finally, I would like to thank the ECE

department and Pl?&L for the financial support that made my work

possible.

-iii-

Table of Contents

ACKNOWLEDGMENTS

ABSTRACT

1. INTRODUCTION 1 .1 ELECTRIC USAGE AND RA.TE STRUCTURES 1.2 OBJECTIVES OF PROJECT 1.3 CURRENT TECHNOLOGY

2. GENERAL HARDWARE 2.1 PROCESSOR SELECTIO~ 2.2 DISPLAY 2.3 COMMUNICATIONS

3· INPUT/OUTPUT ).1 OUTPUT

;.1.1 DISPLAY '3.1.2 STATUS INDICATORS

3.2 INPUT 3.2.1 KEYBOARD ;.2.2 POWER FAILURE 3.2.; METER

4. CONTROL ALGORITHM 4.1 CONTROL ACTION DETERMINATION 4.2 CO~TROL ACTION EXECUTION

5· LINE CARRIER TRANSMISSION 5. 1 BSR TECHNIQUE 5.2 LINE SYNCHRONIZATION 5.3 CODE SYNTHESIS ·5. 4 CARRIER GENERATION

6. CONCLUSIONS 6.1 SU~ARY 6.2 AREAS FOR FUTURE WORK

REFERENCES

A. SYSTEM SCHEMATICS

VITA

-iv-

iii

2 2 3 5

7 7

10 11

14 14 14 15 16 16 17 19

21 21 ;;

38 ;8 42 51 55

58 58 58

60

62

65

Figure 2-1: Figure 2-2: Figure 3-1 : Figure 3-2: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 5-B: Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 5-13: Figure 5-14: Figure 5-15: Figure A-1: Figure A-2:

List of Figures

SYSTEM BLOCK DIAGRAM INTEL MCS-48 FAMILY POWER FAIL~RE CIRCUIT D~TECTION LEVELS CONTROL FLQI.~ CHART CONTROL FLOW CHART (CO~T) CONTROL FLOW CHART (CONT) CONTROL 'BANDS LOGAL CONTROL SERIES SWITCH MODIFIED CONTROL FLOW CHART SHED FL0'-4 CHART RESTORE FLO'I'I CHART RESTORE FLOW CHART (CONT) SERIAL DATA FORMAT SECURITY CODES KEY CODES COMPL~TE MESSAGE BSR OUTPUT TIMING SPLL ETERNAL INTERRUPT FLOW CHART SPLL TIMER INTERRUPT FLOW CHART LINE SYNCHRONIZATION ZERO CROSSING DETECTOR

ZERO CROSSING PHASE SHIFT TRANSMIT FLOW CHART TRANSMIT FL01n CHART ( CONT) TRANSMIT STATES UNIT SECTION ROM TABLE TRANSMITTER HARDWARE SCHF:MATIC

SYSTEM SCH~ATIC (PAGE 1) SYSTE:-1 SCHEMATIC (PAGE 2)

-v-

A 9

18 1 8 22 23 24 29 30 31 34 ;t;

36 38 40 41 43 44 46 47 48 ?0 50 52 ?3 ?4 ?4 ?5 6'3 64

ABSTRACT

Electric load management has become a very exciting area for energy

conservation. As losd management extends to sm~ller and smaller

users, devices which execute the management tasks are required.

Presently, these devices consist of simple timers, or large industrial

control systems. This project was undertaken in an effort to provide

the consu~er with an effective yet economical control device.

This thesis details a proposed controller which is a

microprocessor-b!lsed (Intel 8Q)q), real-time control system that can

be used by residential and small commercial consumers to control their

electric demand. Demand control is beneficial when the utility levies

a demand charge in its rate structure. These demand rates already

exist for commercial customers, and are steadily extending downward to

residential consumers. A proposed experimental rate structure by

Pennsylvania Po•lfer and Light Co. was used as the basis for this

research. This rate structure consisted of time-of-day, day-of-week,

and average (15 minute) demand in determining the customers cost. The

controller attempts to maintain the on-peak demand below a user

selectable target, by shedding or restoring controllable loads (eight

maximum). Control of the eight loads is accomplished via power line

carrier using standard BSR or Levi ton receivers. Energy information

is provided to the system by an encodin~ type kilowatt-hour meter. In

addition tQ controllin~, the unit also provides a large number of

monitoring functions to inform the users of their energy use patterns.

-1-

CHAPTER 1

INTRODUCTION

1.1 ELECTRIC USAGE AND RATE STRUCTURES

~he work schedules of individuals and industry vary during the day.

F.lectricity demand follows these schedules, causing peaks and valleys

in the daily load curve. Variations in this load curve have become

very wide in recent years. A higher penetration of air conditioning

causes needle-sharp peaks in the summer, while increased use of

electric space-heating has resulted in sharper winter peaks. ~CONVERSE

7? l

Typically the utilities have met this fluctuating electricity

demand by using three types of generation. Base load plants (usually

nuclear or coal fired) provide nearly constant output. These units

are the most efficient, and the most economical to operate.

Intermediate plants follow the slow variations in the daily

electricity demand, and are consequently more expensive to run.

Peaking plants are the least efficient and the most costly of all.

Peaking plants are usually gas- or oil-fired turbines that can be

started quickly to meet high demands for short periods. ( LIHACH 821

Times when a utility must resort to using more of the inefficient and

uneconomical generation are termed "on-peak" or "peak times".

The power a customer uses is actually what causes the utility

headaches, since the utility must have enough "capacity" to meet the

customer's eli::ctrici ty demand at all times. In order to encourage

customers tg reduce their demand and thus avoid building new plants,

most utilities include a demand (or capacity) charge in the rate. If

-2-

the consumer does not reduce its dem~nd, this charge will help pay for

the new generation. ~VF.NNARD 70 1 The highest electricity demand in a

billing period is compared to a demand norm, and a credit or penalty

is calculated. ~his demand charge has been common in industrial rates

for years, but has recently been introduced for residential purposes.

A typical custo!ller is at the mercy of his life style and statistics

for the determin~tion of his peak electricity demand.

New plant construction is becoming more difficult than ever.

Construction costs are skyrocketing, licensing is a nightmare of

bureaucratic red tape, and fuel costs are continuing their upward

spiral. As a result, utilities are seeking alternative means for

meeting peak electricity demands.

Load management, specifically demand control, can limit these

peaks. As a result it is possible to avoid building additional

generation. In order to realize the greatest reduction in electricity

demand, a control device is employed. This thesis describes the

design of an automatic electric demand controller which is sui table

for residential use.

1.2 OBJECTIVES OF PROJECT

The basic objectives for this pro.iect were set forth in Lehigh's

initial research proposal to Pennsylvania Power and Light Co. (PP&L).

Subsequent meetings between PP&L and Lehigh University refined· an1

developed these basic objectives into a concise specification for the

device functions. A list of these function specifications follows:

1. Uses 15 minute sliding demand window.

2. Energizes and de-energizes loads to stay below a target

-3-

demand.

3. User can pro~ram target demand and also select which loads are to be controlled.

4. Controls up to 8 loads.

5. Installation requires a minimum of household rewiring.

6. Microprocessor based.

1. Indicates on and off peak times.

8. Indicates if the target is exceeded.

9. Stores and displays:

a. Total kwh use

b. Month-to-date cost

c. Highest "on-peak" demand

d. Month-to-date kwh use

e. Previous month's kwh and demand

f. Time

10. Two peak periods per day.

11. Weekends are off-peak.

12. Steps loads on after power failure.

13. Uses rotating priority schedule (first on, first off).

14. Has capability to receive information from utility automation system.

15. Receives energy pulses from utility meter.

16. Resets registers when utility meter is read.

Item 9b, month-to-date cost, was eliminated early in the program,

due to the complexity and variability of the rate structures. Item 14

was also eliminated due in part to the magnitude of the engineering

-4-

required, but more importantly, due to the lack of a specific utility

distribution automation system.

A detailed explanation of the features and their implementation can

be found in Chapters 2 through ?.

1.3 CURRENT TECHNOLOGY

Residential demand limiters have taken many for:ns, and fall into

three major groups. The first group is Timing Devices, which is the

oldest technology, and includes basic timers, cyclers, and schedulers.

All devices of the timing type reduce demand by turning a load on or

off during prescribed time intervals. This strategy causes the most

inconvenience to the consumer. ~A?S 82]

Interlocks comprise the second group, and reduce demand by

preventing two or more electric appliances from operating at the same

time. These devices are effective, but require some house rewiring,

and are quite inflexible. They also control a limited number of loads

(usually 1).

Demand Load Controllers are the final group, and are generally

microprocessor based devices which turn loads off to stay below a

target deman1. Arizona Public Service Co. (APS) has conducted an

extensive survey of residential demand control devices. Included in

this survey were such devices as the Cyborex System One™ by Cyborex,

Demand Manager™ by Enertrol, DC-808 Demand Controller by Dencor, and

the Sentrol Tr1 SC112 by Horizon Technology. An analysis of the APS

information indicates the following typical features:

1. Controls 8 or less loads.

2. Hard wired relay type control of loads (some units have two

-?-

boxes, a control panel and a relay panel),

;. Fixed demand target set by user.

4, 24 hour operation (no time-of-day feature)

5. Only displays demand information.

Some larger residential or commercial type systems such as AT&T's

Residence F.nergy Management Terminal and Scitronics' EnerMizer I,

offer more features, but cost substantially more than a typical home

owner could afford. ~CHAI 821 [SCITRONICS 82)

Chapter 2 will discuss the early hardware decisions that were made

in order to accomplish the goals of the project which were set forth

in Section 1.2.

-6-

CHAPTER 2

GENERAL HARDWARE

In this chapter the selection process involved in choosing the

major hardware components will be described. 'igure 2-1 sh9ws the

block diagram of the controller, which has as its heart an Intel 8Q3q

microprocessor. An Intel 8755 contains the program memory in the form

of a 2k byte EPROM, and also contains 16 I/O lines. The system

contains an on-board power supply that can operate from either 120 or

240 VAC, and supplies the UC and AC volta~es required by the processor

and display devices. There is a power-fail battery back-up supply

which preserves the contents of the processor RAM for a minimum of

four days. User interface is through a 4x4 keypad, and a six digit

v~cuum fluorescent display. Communication to the receivers is through

a power line carrier technique employing a 121kHz carrier signal

injected onto the power line.

A complete schematic of the system can be found in Appendix A and a

more detailed description of the various hardware can be foun1 in the

following chapters.

2.1 PROCESSOR SELECTION

Processor selection is a very crucial part of the design of an.v

microprocessor-based device, and this project was no exception.

Several criteria were generated during the early stages of the

project, on which to base the decision. One of the criteria was

flexibility, since the processor (and the supporting development

system) had to be ordered prior to the design of the con troller

software and hardware. A sin~le chip microprocessor was desired to

-7-

I ()) I

METER INPUTS

c A LINE

6 DIGIT VACUUM FLUORESCENT

DISPLAY METER

A .,-r ~ r-COND. CIRCUIT \ DIGIT I 'SEGMENT' DRIVER DRIVER CPU

r/ 8755

8039 ~~ ~--r... POWER II ~ SUPPLY

/ "\ I 128x8 2k X 8

RAM \. I EPROM I POWER FAILURE 1 y PLUS

LOGIC TWO BBIT

JL-IO PORTS

~~ -t ~~ AC \r COND. L__r--CIRCUIT ~

J LATCH I ~ STATUS

~~ 4 X 4 DRIVER cS. - 121kHz KEYPAD ~ LOJD j COUPLING osc.

~ LEOs STATUS

FIGURE 2-1: SYSTEM BLOCK DIAGRAM

I CD I

METER INPUTS

c A LINE

6 DIGIT .. VACUUM FLUORESCENT DISPLAY

METER ~ ~r ~r COND.

CIRCUIT '\ DIGIT I ISEGMENTI DRIVER DRIVER CPU v 8755 8039 ~ --~ .-4!....- "?-

POWER SUPPLY A ~

I '\ / I 128x8 2k X 8 RAM \ ( EPROM I POWER

FAILURE ~ PLUS LOGIC TWO BBIT

;1-IO PORTS

~J, ~ ~7 AC \r COND. ~ CIRCUIT ~ I LATCH I

~ .J_ ..J..-4 X 4

DRIVER & - 121kHz STATUS KEYPAD I LONJ 1 COUPLING osc. L-f LEOs STATUS

FIGURE 2-1: SYSTEM BLOCK DIAGRAM

minimize support hardware, thereby reducing the cost and complexity.

Multiple sourcing was also a consideration, as the desi~n was to be

commercialized at some time in the future. A final criterion that was

not a direct consequence of this project, was that of future expansion

of the development system selected.

After examining several major manufacturers' devices, the Intel

MCS-4R family of devices was selected. The first member of this

family (the 8748) was introduced in 1979, and was followed by

additional pin compatible members. Over the years these devices have

become very popular, and at least three manufacturers are producing

MCS-48 components. Figure spread of capabilities

encompassed by these devices.

2-2 shows the

~INTEL 821

CHARACTERISTICS COMPONENT 8035 8039 8040 8048 8049 8050 8748 8749

RO!rl Size (kbytes·) 1 2 4 1* 2* RAM Size (bytes) 64 128 2'56 64 128 256 64 128 I/O Pins 15 15 15 27 27 27 27 27

* EPROM

Figure 2-2: INTEL MCS-48 'FAHILY

The 8048 is an integrated microcomputer which consists of a CPU,

RAM, RO~, I/0, clock generator, and a timer/counter, all contained on

a single 40-pin dual-in-line package. Operation is from a single

?-volt supply. Successively higher level devices contain more memory

than the previous device. This was crucial for our pro,iec t, as the

first processor selected was the 8748, which contains 64 bytes of RAM

and 1 k of EPROM. After writing some of the software, it became

evident that more memory would be required. The final device was the

R0,9, which contains 128 bytes of RAM. F.PROM was relocated to a

-9-

second chip, the 8755, in orrler to provide 2k bytes, and to enable the

battery back-up feature on the RAM in the CPU.

The Intel development system, an ~DS-120, has proven extremely

helpful, and the In-Circuit-Emulator (ICF.-49) is a very powerful

development tool. Expansion of the MDS-120 can be implemented to

support any of the Intel product line. Intel is known throughout the

industry as a leader in microprocessor technology, and has a very

complete product line.

2.2 DISPLAY

The candidates for the display were Liquid Crystal, Vacuum

Fluorescent, Gas Dischar~e, and Light-Emitting Diode displays. Liquid

Crystal Displays (LCDs) were preferred by PP&L for their low power

consumption and relatively low cost. The major disadvantage for LCDs

is the support hardware requirement. LCDs require AC signals that

preclude normal multiplexing techniques. Consequently, very

specialized and very expensive support devices are needed to generate

the complex waveforms.

Light-Emitting Diode (LED) displays were rejected for high cost,

high power, and low light output properties. Gas Discharge displays

also had poor light output, and require high voltage, about 60 volts,

for operation.

Vacuum Fluorescent (VF) displays were chosen for the user interface

for a number of desirable features inherent in its ,design. VF

displays were developed in Japan about 10 years ago, and are found in

many consumer products. The 'If displ!ly is basically a triode, th!i t

has a heated cathode, and an anode th9.t is coated by a fluorescent

-10-

material. The cathode luminescence is wh~t produces the light for the

display. Each segment of the st!lndard seven-segment display is a

separate cathode, with all similar cathodes of each digit connected

together. A grid is placed between the anode and the cathodes. Each

digit has a separate grid, and by applying the appropriate voltages to

grids and cathodes, a standard multiplexing technique can be realized.

The fluorescent material used is Zn-ZnO which luminesce at several

volts, allowing the display to operate on 24 volts. The blue-green

spectrum of the light output is also very pleasing to the human eye.

VF displays also consume relatively low power, approximately 60

milliwatts per digit. The device is low in cost, rugged, and has 11

l~ng life. ~NEC 791

2.3 COMMUNICATIONS

Four methods of communications from the controller to the loads

were investigated. The first method was hard wiring of the power to

the loads through the controller. Relays of either solid state or

electromechanical type would control the power to the loads. This

method is utilized in many of the controllers on the market today, but

it also has the most disadvantages. A large expense and a great deal

of trouble is involved in rewiring a household, plus the installation

is very inflexible.

The second approach is really a variation on the first, employing

low voltage control wiring from the controller to the relays, which

are located at the load or the power panel. 'This eliminates the cost

of running the power wiring, but still requires the low voltage

wiring, and inflexibility remains a problem.

-11-

Radio control was examined, with a transmitter at the controller

and radio receivers which activate relays located at the loads. An

elimination of the wirin~ is realized with this configuration, but

problems of interference between controllers was anticipated. Other

problems included the high cost of receivers and transmitters.

Problems were also envisioned with the FCC certification once the

device was to be com~ercialized.

The method chosen was a power line carrier technique introduced by

BSR ( BSR ?? ] • In this technique, a high frequency (121kHz) carrier

is injected onto the power line, and then amplitude modulated to

transmit a digital message. Receivers at the loads detect the carrier

and decode the digital message. Elimination of any extra wiring is an

inherent feature of this technique. Interference with other

transmitters is minimized since the 121kHz carrier is sufficiently

attenuated at any distribution transformer. Additionally each

transmitter can select from sixteen different codes. Leviton has also

begun ~anufacturing receivers based on the same technique, making the

receivers commercially available at economic prices. A detailed

explanation of the BSR technique can be found in Section 5.1.

Most of the work done in the field of power system communications,

has focused on centralized communication systems for utility

~ ORNL 81l distribution auto~ation and load management. CBLAIR 82]

However, the infor.nation that has been collected on

techniques, can still be applied.

the various

Power line carrier's greatest disadvantage for central systems is

that the signal can be blocked by distribution transformers and

voltage correction capacitors. This is an advantage for local

-12-

control, since interference would otherwise occur between two

controllers. Power line carrier has an sdvantage, in that very little

power is required for transmission.

Radio systems cover large areas, which could lead to interference

problems, but they also suffer from signal blockage (shadow).

Finally, telephone systems appear attractive as a central

communications medium, but they suffer from the inflexibility that is

typical of all hard wired systems.

In light of these findings, the decision to utilize power line

carrier as the means of local communications appears to be well

supported.

In the next chapter, the hardware and software that interface the

microprocessor to the user and to its environment will be discussed.

-1'3-

CHAPTER 3

INPUT/OUTPUT

In this chapter a discussion will be presented on the basic

hardware and software that allow the microprocessor to communicate

with its environment. The input and output are basically accomplished

using the program presented in reference CWARTON 80], and the

interested reader can obtain more detail in that document. Warton's

program ha~ however, been modified significantly to incorporate the

unique requirements of the controller.

;.1 OUTPUT

;.1.1 DISPLAY

The display is time multiplexed, and the display software is driven

by the interrupt structure presented in Section 5. 2. Basically, an

interrupt is generated by the internal timer every 1.28 milliseconds,

and at each interrupt a counter (CURDIG) is decremented from 12 to -1,

and then reset to 12. Each count of the CURDIG counter corresponds to

a different digit being displayed (modulo 6), with counts 0 and -1

causing a blank display. Two MC3494 drivers are used to interface the

processor output to the display. Each of the six digit select lines

controls a digit grid on the vacuum fluorescent display. Eight other

lines control the seven individual segment anodes, and the decimal

point anode. All fourteen of these output lines are latched

internally. When an interrupt occurs, CURDIG is decremented an1 the

display is blanked by turning off (high level) both the digit select

and the segment select lines. The digit correspondin~ to the new

-14-

CURDIG value is selected and the appropriate segment pattern is

latched into the output port. The segment patterns are stored in a

DISPLAY BUFFER in RAM. The DISPLAY BUFFER is described in more detail

in section 3.2.1. A separate output pin and a single transistor are

used to control the· "Z" anorie (bar), the status of which is stored in

a single byte in RAM. Each bit in the byte corresponds to a different

bar on the display, and are used to inform the user what dimensional

units apply to the data that is being displayed. Time (hours and

minutes) is indicated by the left bar, power (kw) by the second from

the left, and energy (kwh) is indicated by the third bar from the

left.

3.1.2 STATUS INDICATORS

The eight segment lines are also used to transfer data to the load

status latch. A byte in RAM, the load status byte, contains the

current status for all the loads (see Section 4.1). After blanking

the display, the load status is latched to the segment control lines.

Another output pin is then set high and then set low to generate a 5

microsecond strobe to latch the data into the 74LS363 TTL latch. By

using a TTL latch, the status LEDs can be driven directly by the

outputs, thereby minimizing hardware. After the latch has been

updated, the segment lines are returned to normal service.

Three other output lines are used to drive individual transistors,

which in turn drive indicator LEDs. The three indicators are

OFF-PEAK, CONTROLLING, and TARGET EXCEEDED, all of which correspond to

flags generated in the control algorithm (Section 4.1).

-15-

3.2 INPUT

3.2.1 KEYBOARD

Four of the six digit select lines (Section 3.1.1), are also used

to scan the 4x4 keypad. Each time a digit is selected, one of the

lines goes low, placing a low voltage on one of the column select

lines of the keypad. The four row lines of the keypad are connected

to four input pins on the processor, which have a high impedance

pull-up that normally holds the input at a "1". If a key is down in

the selected column, then the corresponding row line will be pulled

low, while keys down in a nonselected column will have no effect. If

a key is depressed its location is noted in a RAM location (LASTKY).

After several successive scans in which the same key has been

detected, the key location is transferred to KBDBUF, which then

contains a debounced key location. This byte can then be read by a

background program.

In the case of the controller the background program takes the

debounced key and processes it through a decision tree. This decision

tree allows the controller to determine the validity of the entries of

the user. Each time the background program reads the KBDBUF, it

resets the KBDBUF, and awaits the next entry. When the processor

detects an invalid entry, an error message is flashed on the display.

When the user requests the display of data, a byte (DISP) is loaded

with the base address of the RAM location which contains the data

requested. A second byte (NUMB) contains both the n~ber of bytes in

the data, and the placement of the decimal point. All the data are

stored in BCD form in~RAM, which allows the display or entry of data

with a minimum of manipulation. The DISPLY subroutine encodes the BCD

-16-

digits into seven-segment patterns, which are then loaded into the

DISPL.H BUFFER. The DISPLAY BUFFER has a RAM byte for each digit.

The DISPLY subroutine also appends the decimal point to the proper

digit. Calls to the DISPLY routine are made at the rate of two times

per A-C cycle, ensuring that the data displayed is constantly updated.

3.2.2 POWER FAILURE

A power failure is rletected by the comparator circuit shown in

Figure 3-1. This circuit consists of two level detectors, both of

which use the memory backup battery voltage (2.8 volts) as a

reference. The first level detector is used to detect a low voltage

(power fail;re i~~inent) condition. The voltage divider consisting of

R14, R15, and R16 scale the raw DC (normally 10-12 volts) which is

supplied to the 5-volt regulator, to provide a voltage that is

sui table for the comparator. Resistors R9 and R10 provide positive

feedback, which generates "hysteresis" in the detection level. Figure

3-2 shows that the scaling and hysteresis have been designed to give

an activation voltage level of q volts, and a release level of 9.5

volts. Resistor RB is a pull-up for the output of the comparator,

generating a logic signal that is fed into the TO input of the

processor. The TO pin is polled during the interrupt service routine

(every 1.28 msec) and if a low level is detected, a two instruction

loop (wait) is executed until TO returns high. This wait state

prevents accessing RAM in the event of a complete power failure.

The second level detector deter:nines the actual power failure by

detecting when the unregulated DC supply drops to 7 volts (Figure

'3-2). Scaling is accomplished using R14, R15, and R16, with R12 and

R1'3 providing 1 volt of hysteresis. Resistor R11 acts as a pull-up,

-17-

POWER 13 FAILURE----< !RESET I

s.ov UNREGULATED

DC

FIGURE 3-1: POWER FAIL CIRCUIT

LOW VOLTAGE SIGNAL

POWER FAILURE !RESET I

FIGURE 3-2: DETECTION LEVELS -18-

and feeds into a third comparator. The third comparator is used to

provide an open-collector output to the RESET pin of the processor.

When power returns, the processor starts through an initialization

routine. The ini tia.lization routine consists of a "warm start" and a

"cold start", with the difference being whether or not the RAM

contains valid data. Two memory "keys" are stored in RAM, which are

examined by the initialization routine to determine the integrity of

the RAM. If both keys are present, the memory is assumed to be

intact, and a warm start is executed. If either of the keys is not

present, a cold start is executed which zeros all the data registers,

preloads some registers with default values, and also loads the memory

keys. Tn both cases the time is no longer accurate since the time is

generated by counting AC line zero crossings. Therefore the time

registers are loaded with "FFFF" which prevents the clock from

advancing, and also serves as an indicator to the user that a power•

failure has occurred.

3.2.3 METER

The meter that was used for experimental purposes was a standard

Westinghouse type D4S induction kilowatt-hour meter equiped with a

CDI-12A pulse initiator. In actual installations, a modern

solid-state meter such as the General Electric TM-80, will be

utilized. The inputs from the utility meter consist of two signals,

the first being a pulse train that indicates energy usage. This pulse

train is generated by an encoder on the wheel of a standard induction

type kilowRtt-hour meter. A mercury-wetted relay closes and opens

each time the wheel makes a revolution, thereby generating a pulse for

every ?.2 watt-hours in the case of a standard residential meter.

-19-

Logic level conversion is accomplished by grounding one end of the

switch, and providin~ a pull-up resistor to 5 volts on the other side

of the switch. Noise on this input is rejected by a single stage RC

low pass filter, and also by the fact that the input is only polled at

a 120Hz rate.

The second input is a signal that indicates the utility meter has

been read, i.e. it is the end of a billing period. Being a groun:led

normally closed switch, this· input provides an input which is normally

low. This signal is fed to an input pin which has a high impedance

pull-up, that is held low by the low impedance switch. When the

switch is opened, a high is placed on the input, and detected by the

120Hz polling loop. Reading the meter thus signals the processor to

start a new billing period (see Section 4. 1). Only one reading in a

given day is permitted, therefore the processor latches a low to the

input pin, preventing another high level input. At the end of the day

(midnight), the input is again returned to a high impedance pull-up

condition to await the end of the next billing cycle. This input is

also fil tared with a single sta~e RC low pass filter to eliminate

noise.

In the next chapter a description will be given of how the

controller determines the control strategy an:i how this strategy is

then implemented.

-20-

CHAPTER 4

CONTROL ALGORITHM

The control al~ori th'll implemented is not in accordance with any

existing PP&L rate structure, but rather a combination of two

different rate structures, a detailed account of rate structures is

given in Section 1 .1. Residential rate structure RS provides for a

demand billing ch~rge or credit for each whole kilowatt-hour above or

below a demand norm. An experimental residential rate structure,

RX(R), is based on "time-of-day" and "day-of week" ener~y use, i.e.

peak periods CRATE RX(R) 81, RATE RS 811. Integrating the two rate

structures, yields the basis for the control algorithm, that is peak

period demand control.

4.1 CONTROL ACTION DETERMINATION

During one execution of an interrupt service routine, the time

registers are advanced. When the seconds register overflows, one

minute has elapsed, initiating the execution of the control algorithm.

Figures 4-1 to 4-'3 sho·..r the flow ch~rt of the control routine. On

entering the routine, a comparison is made between the priority table

and the load status table. The priority table is a byte in random

access memory (RAM), which contains a "1" or a "0" in each bit

location corresponding to each load. Priority for each load is

selectable by the user, with a priority "1" indicating no control

(always on), or a "0" indicating that the load is controllable. This

feature allows the user to override the controller on specific loads

with a minimum of effort. Load status table is a byte in RAM which

contains the condition of each of the eight loads at the last time of

-21-

y

SET "ON PEAK"

FLAG

y

N

SET PRIORITY "1" LOADS

TO ON

SET BSR STATE COUNTER

TO 1

SET "CONTROL"

FLAG

N

N

RESET "CONTROL"

FLAG

RESET "ON PEAK"

FLAG

FIGURE 4-1: CONTROL FLOW CHART -22-

KW tT): ave

t KWHCT) -KWHtT-15) 1•4

HKW=KW tT) ave

N

CP=HKW CP= TARGET

RESET "TARGET

EXCEEDED"

CALL RESTORE

FIGURE4-2: CONTROL FLOW CHART (CONT)

-23-

KWins~Tl = t KWH IT) -KWH!T-1 l J•SO

RETURN

CALL RESTORE

FIGURE 4-3: CONTROL FLOW CHART (CONTl

-24-

transmission, with on represented by a "0" and off by a "1 ". If, upon

making the co~parison between the priority one loads and the current

status, a priority one load is found to be off, then its corresponding

bit position in the load status table is reset to zero. Additionally,

the TRANSMIT state counter is set to one, which is a flag to the

TRANSMIT subroutine that 11 ch1.:1nge has been made to the load status

(see Chapter ? for details).

In the rate structure proposed by PP&L, peak periods are defined as

only occurring on weekdays. A data byte is used to keep track of the

day, with one being Monday, and seven representing Sunday. The first

step in control determination is to ascertain if the present time is

during a peak period. Saturday or Sunday cause both the "control"

flag and the "on-peak" flag to be reset. These two flags are used for

logical decisions further along in the control scheme. T'..ro peak

periods are allowed, and are delineated by times T1, T2, T' and T4,

which are easily programmable by the user to allow for changes in the

rate structure. This allows for either one or two peak periods by

programming the second period to be of zero length if only one period

is desired. More than two peak periods would require modifications to

the software. The first peak period is from T1 to T2, and the second

from T3 to T4. Setting of the "on-peak" flag occurs any time the unit

is in one of the two peak periods. The "control" flag is set 2'

minutes prior to the beginning of each period, permitting the

controller to exert adequate control. Twenty-three minutes is

determined from the sum of eight minutes, which is the time required

to exert maximum control effort, and fifteen minutes. The fifteen

minutes is the first set of data for the 15 minute sliding window,

since the first aver11ge "inside" the peak period actually uses the 15

-25-

minutes of prior data. Both control and on-peak flags are reset at

the end of either peak period.

After determining the condition of the' two flags, the current

average demand is calculated using the following equation:

10.~avg(T) = ~ J<l.m(T)- K~rn(T-15) I* 4 ( 4.1 )

where T is the time in minutes. The energy readings, KWH(T), are

stored on a 15 level stack in the data RAM. Two bytes of packed BCD,

representing four decades of the kilowatt-hour meter register, are

pushed ont6 the stack each minute. If the current time is during a

peak period, the average demand is compared to the value of the

highest average on-peak demand {H~f) that has occurred in this billing

period. If the present demand is higher, then the highest demand is

updated. It is this highest on,-peak demand upon which the utility

levies its demand charge. Calculating the 15 minute average every

minute is called a sliding window averaging process. This technique

eliminates the need to synchronize the controller's 15 minute window

with that of the utility meter. Msdern salid-state utility meters

also use a sliding window to prevent customers from "loading-up" at

the end of a demand interval.

The user programs (through the keypad) a desired demand, termed

"target", for the controller to maintain. Actual on-peak demand may

exceed this target due to an unrealistic target value, a high level of

uncontrolled loads, or poor control. If the target is exceeded, an

alarm is indicated in the form of a lighted yellow LED. Additionally,

the highest on-peak demand is substituted for the target as the

control point. This is an important and unique feature of the control

algorithm, one which reflects the realities of the rate structure.

-26-

Since the user is billed on the highest on-peak demand achieved during

the billing period, to control at a level below this point might cause

the user unnecessary discomfort. An optimu:n control point will be

determined if the user selects a very low target. value. The

controller will attempt to control the demand to this level, but due

to uncontrolled loads, will be unable to do so. The control point

will be progressively elevated until the minimum controllable level is

found. Determination of the control point is accomplished without the

user, and in finding the minimum control point, maximizes the

financial benefit to the user.

At the end of a billing period, which is signaled by a switch

closure when the utility meter is read, the control point is reset to

the target value. The highest on-peak demand (HKW) is moved to the

previous month highest on-peak demand (PHJ<111), and the present Hlrfl is

then reset to zero. This approach is consistent with the utility rate

structure.

If the control flag is not set, no control action is required, but

the RESTORE routine is called. A call to the RESTORE routine turns on

one load, and a detailed description is contained in Section 4.2. By

repeated calls of RESTORE, the loads are turned on one each minute.

This action prevents a displaced peak, or "restrike", from forming

immediately following the end of a peak period.

Control action commences as a result of the control flag being set

to one, with an estimation of the instantaneous demand given by

Equation (4.2).

KWinst(T) = [KWH(T) - K\m(T-1 )J * 60 (4.2)

-27-

This equation yields the one minute average demand, which is used for

control. Laboratory experiments utilizing various intervals for

estimation were tried, including a three minute interval which was

used in the Powers System 570 [PQl.ofERS 75]. It was found that due to

the large discontinuities in demand caused by the small number of

loa1s, that any averaging caused the control action to lag, resulting

in an overshoot of the target. In order to maintain the fastest

response possible, the one minute interval was chosen. Smaller

intervals were eliminated on the basis of quantization errors caused

by the finite resolution of the utility meter pulses. As was

mentioned in Section 3.2.3 ,the utility meter provides pulses

corresponding to a certain energy consumption, in this case the

resolution was ).6 watt-hours. The quantization error can easily be

shown to be+ 216 watts as follows:

r+tbitl[;.6 whrs/bit]L6o min/hr] ·- .. + 216 watts min (interval length}

Note that the error varies with an inverse relationship to the

interval value. This error can be reduced by increasing the meter

resolution.

After the estimate, ~Ninst(T), has been calculated, it is compared

to the control bands as shown in Figure 4-4 • The first decision

level, the "shed limit", is a fixed demand, or "offset", below the

control point. In the present system the offset is 0.5 kilowatts,

which prevents rounding errors and slight control overshoots from

"pumping-up" the control point. If the present' demand is above the

shed limit, the SHED subroutine is called to turn off one load. The

second decision level, the "restore limit", is 0.9 times the control

-28-

0 z < :E w 0

SHED LOAD

DEAD BAND

CONTROL POINT

CONTROL POINT­OFFSET tO.SKWl

RESTORE LOAD

S - LOAD SHED AT THIS POINT R - LOAD RESTORED AT THIS POINT

TIME tMINUTESl

FIGURE 4-4: CONTROL BANDS

-29-

-point, minus the same O.?kw offset. If the present demand is below

the restore limit, a call to the RESTORE subroutine is made, to turn

on one load. A deadband of 0.1 times the control point is thus

generated between the shed and restore limits. Within this dead band

no control action is requested.

The controlled loads may contain a local controller, such as a

thermostat, which is in series with the receiver as illustrated below:

Receiver Local Control Load 0 AC Line Switch Switch

Figure 4-5: LOCAL CONTROL SERIES SWITCH

The actual status of the load is the logical anding of the two switch

positions. Since only the receiver switch is observable by the

controller, it may, in an effort to shed load, turn off loads that are

actually already off. As a direct result of this problem, and the

fact that only one load is altered each minute, it may take some

appreciable amount of time, up to a maxim~~ of eight minutes, for the

controller's actions to have an effect on the total demand, i.e. find

a load that is actually on. During the time the controller is

searching for a load that is on, the instantaneous demand is exceeding

the control point. When the demand is finally brought back into

control, if the uncontrolled demand area is large enough, the average

demand may also exceed the control point. This "delayed error" was

observed in bench testing, and could be a problem in a real

installation, since many of the controlled lo~ds will have local

controllers. To correct this problem, the control algorith~ was

modified to that of Figure 4-6.

-30-

KW lTl = 14rnavQ

t KWH(Tl -KWHtT-14) l+ KWH ( Tl -KWH ( T- 1) ll•4

KW tTl= I nat:

KWH ITl -KWH lT-1) 1•60

y

CALL SHED

CALL SHED

FIGURE 4-6:

SET FLAG

CALL RESTORE

MODIFIED CONTROL FLOW CHART -31-

All as-pects of the original algori th1\ 9.re retained, up to the

calculation of the instantaneous demand. At this point an average

demand is calculated from the following

KW14min avg(T)=Ul(1h'H(T)-KWH(T-14) I+ (K\m(T)-KWH(T-1)] J * 4 (4. ?)

This is termed the 14 minute average, but is actually the 14 minute

average plus the demand of the previous minute. The calculated value,

KW14min avg' is then a prediction of the next 15 minute average if the

instantaneous demand continues. If this predicted deman:i plus the

offset is above the control point, a call to the SHED routine is made

to turn off one load. Upon returning from the SHED routine, a flag is

set, and the instantaneous demand is calculated as before using

Equation (4.2). The control bands of Figure 4-4 are again applied,

but if the flag is set, the control algorithm is prevented from

restoring a load on this pass. This action prevents the second

control loop from negating the efforts of the first loop. Another

important aspect of this control scheme is that the SH~D routine may

be called up to two times each pass, therefore permitting two loads to

be shed each minute. This allows the maximu11 control effort to be

realized in four minutes whereas previously eight minutes were

required. Increasing the rate of control action in the shed direction

may result in a reduced occurrence of overshoot, and consequently, a

reduced offset value. No data, however, has been taken to date in

support of this theory. It should also be noted that only the

instantaneous demand is used to restore loads.

4.2 CONTROL ACTION EXECUTION

The net result of the control algorithm presented in the previous

section is a call to either the SHED or RESTORE routines. SHF.D is the

routine which turns off one load, and the flow chart is shown in

Figure 4-7. Upon entering the routine, the present load ststus byte is

masked with the ~riority load byte to eliminate all the priority "1"

loads from possible control action. Priority "1" loads are masked to

appear off since the SHED routine is looking for loads which are on.

This masked byte then contains the status of all controllable loads

that are on. A queue pointer, which is a RAM byte containing a one in

a single bit position, points to the bit position of the load which

has been off the longest period of time. It is from this position

that the SHED routine searches for the next load to turn off. The

pointer is rotated in a circular fashion from its present position to

the next numerically higher position (i.e. from 2 to 3, 5 to 6, 8 to

1, etc.) until a load that is on is found, or until the pointer has

been rotated eight times. If a load that is on has not been found

after eight rotations, all the controllable loads are off, and a

return to the calling program is executed. If an on load is found,

the load status is modified, then stored back in RAM. The TRANSMIT

state counter is set to one to initiate the transmission of the new

status to the receivers. The queue pointer is not permanently

altered, and is restored to its original position before the return to

the calling program.

The RESTORF. subroutine is depicted in the flow chart of Figures 4-8

and 4-9. The load status byte is first checked to see if it is zero

{i.e., all loads on) and if it is, a return is executed. If a load is

off, the TRANSMIT state counter is set to one to initiate the

-33-

GET LOAD STATUS

MASK ALL PRIORITY "1"

LOADS

GET QUEUE POINTER

MASK MODIFIED STATUS WITH

POINTER

ROTATE QUEUE POINTER

SET LOAD TO OFF

STORE NEW STATUS

SET TRANSMIT STATE COUNTER

TO 1

FIGURE 4-7: SHED FLOW CHART

-34-

GET LOAD STATUS

SET TRJ\NSMIT STATE COUNTER

TO 1

GET QUEUE POINTER

MASK STJ\TUS WITH QUEUE

POINTER

SET LOAD STATUS TO ON & SAVE STATUS

N

NO MORE l LOADS TO RESTORE

FIGURE 4-8: RESTORE FLOW CHART

-35-

ROTATE QUEUE POINTER

MASK STATUS WITH QUEUE

POINTER

GET QUEUE POINTER

ROTATE POINTER

MASK PRIORITY WITH QUEUE

POINTER

y

SAVE NEW POINTER

SAVE NEW POINTER

FIGURE 4-9: RESTORE FLOW CHART (CONTl

-36-

transmission of the revised load status to the receivers. Next, the

queue pointer is obtained and checked against the load status. The

queue pointer should be pointing to the load that h'ls been off the

longest period of time, but if the priority of this load has been

changed to a one, the load may be on. If the load is off, it is

turned on, and the new status placed in RAM. After updating the

status, or if the indicated load is on, the next available off load is

located. This is accomplished by rotating the queue and masking the

load status with this rotated mask, until an off load is found, or the

queue pointer has been rotated seven times. If an off load is found,

the new queue pointer is saved, and a return to the calling program

executed. If an off load is not found, the next controllable load

must be deter.nined for the SHED routine. The next controllable load

is located by taking the ori~inal queue pointer, rotating it, and then

masking it with the priority byte. This loop also continues until a

controllable load is found, or the pointer is rotated seven times.

The final action is to save this new queue pointer and return to the

calling program.

In the next chapter the hardware and software that are used to

generate the powerline carrier communications to the loads will be

discussed.

-37-

CHAPTER 5

LINE CARRIER TRANSMISSION

In the previous chapter, the control actions were determined and

the status of the various loads deposited in a table. A flag was set

to transmit this status to the load receivers. In this chapter the

method of communicating the status to the receivers will be discussed.

5.1 BSR TECHNIQUE

The controller communicates to standard BSR X-10 or LEVITON

receivers, using a power line carrier technique. In this technique, a

high frequency, amplitude modulated signal is injected onto the power

lines, and conducted to the remote receivers. The basic BSR format

consists of a 22 bit word, transmitted serially at 120 Baud, with each

bit being synchronized with a zero crossing of the A-C line (BSR ??].

BSR utilizes a custom P-MOS large scale integrated circuit,

Transmitter Chip No. S42C, to generate all the bit patterns and to

synchronize these bits with the A-C line. "One" bits are represented

by the presence of the 121kHz carrier signal, and "zero" bits are the

absence of the carrier. Figure 5-1 depicts the serial da·ta format

employed, consisting of 11 cycles of the A-C line.

s s 1 2

2

s s 3 4

START CODE

3

H H 8 8

4

HH 4 4

5

HH 2 2

SECURITY CODE

6

H H 1 1

7

D D 8 8

8

DD 4 4

9

D D 2 2

10

D D 1 1

KF::Y CODE

Figure 5-1: SERIAL DATA FORMAT

11 CYCLE

D D 16 1 6

BIT

The 22 bit word can be broken into three sections; the start code, the

security code, and the key code.

-38-

The start, or framin~ code is four bits long, and consists of three

ones followed by a zero bit. This pattern is unique since the other

two sections consist of a bit followed by the inverse of that bit,

hence three successive ones can only occur in the start portion of the

word. This is used to synchronize the receivers with the word being

transmitted, and is a common feature of asynchronous transmission

protocols.

The second section is the security or house code. This portion of

the word is eight bits long and is used as part of the address of the

receiver. Since the eight bits are actually alternating bit and the

complement of the bit, these eight bits identify sixteen possible

security codes as "shown in Figure 5-2. All receivers that are in one

residence are typically given the same security code. By assigning

different security codes to each transmitter, several transmitters can

operate on the same lines without interference. This is particularly

useful when two residences each have a transmitter, or more

importantly when two apartments in the same building wish to utilize

transmitters.

The third section is the key code, or operation code, which is ten

bits long. This section is either the unit number, second half of the

address, or a function command. Again, the sequence is a bit followed

by its complement, so there are actually 32 possible combinations.

BSR has only defined 22 of these codes, and they are shown in Figure

5-3. Sixteen of the 22 defined codes are the unit numbers. A unit

number is the second half of a receiver's address. There are four key

codes which specify an operation. The remaining two codes are ALL,

which is used to address all the units on a particular security code,

and the CLEAR code which resets the receivers.

-'39-

SECURITY CODE HB H4 lt2 H1

A 0 0

B 0

c 0 0 0

D 0 0

E 0 0 0

F 0 0

G 0 0

H 0

I 0

J

K 0 0

L 0

M 0 0 0 0

N 0 0 0

0 0 0 0

p 0 0

Figure 5-2: SECURITY CODES

-40-

KEY D8 D4 D2 D1 D16

0 0 0

2 0 0

3 0 0 0 0

4 0 0 0

5 0 0 0 0

6 0 0 0

7 0 0 0

8 0 0

9 0 0

10 0

11 0 0 0

12 0 0

13 0 0 0 0 0

14 0 0 0 0

15 0 0 0 0

16 0 0 0

CLEAR 0 0 0 0

ALL 0 0 0

ON 0 0 0

OFF 0 0

BRIGHT 0 0 0

DIM 0 0

Figure 5-3: KEY CODES

-41-

In order to have a receiver perform an operation, it must be first

addressed by sending a word having the proper security code, and the

proper unit code. This word is trans~itted twice to assure correct

reception, followed by six cycles of no transmission. After the six

cycle delay, a second word, again having the proper security code, but

containing the appropriate operation command, is transmitted. This

word is also trans~itted twice. In total 50 cycles or 0.833 seconds

are required to trans'lli t a complete message to a single receiver.

Figure 5-4 shows a complete message transmission.

BSR specifies very tight tolerances on the placement of the carrier

burst with respect to the zero crossing of the A-C line. In BSR' s

format, a "one" bit actually consists of three separate bursts of

carrier as shown in Figure 5-5. These three bursts are spaced at 60

electrical degrees so as to allow three-phase communication. This is

required due to the fact that the receivers use the zero 7rossing as a

strobe. The first burst begins within 100 microseconds of the actual

zero crossing. Each burst is millisecond in duration, and the

leading edges of the three bursts are spaced at exactly 60 electrical

degrees (2.778 milliseconds).

5.2 LINE SYNCHRONIZATION

As was mentioned in the previous section, BSR and other devices on

the market utilize the 542C transmitter chip to generate the code and

perform the line synchronization. A different approach was chosen in

this project, and that was to allow the microprocessor, via software,

to generate the appropriate codes and also to carry out the task of

zero crossing synchronization.

-42-

3 4

" " AC LINE

""' "1" "1" "1" "0"

I I I 121kHz

_j

r

1 2 3 4 5 6 7 8 9 1 0 1 1 12 13 14 15 16 1 7 18 19 20 21 22

I I I

- ~

START CODE

>-1-:w IS~ ~

s -; 1--5

I I I I I I I SECURITY CODE KEY CODE

~ s ~ w ~ ~ - li: 0 t--w= : -w, o: -w.

~ a::o< g a::o< UZ ~ a::o· hl8c 1- ~8~ 0 ;:,a< - ~: uu=

5 Ul w (/) ~ Ul

DELAY

MESSAGE: "UNIT 1 TURN ON"

FIGURE 5-4: COMPLETE MESSAGE -43-

I I J

w 0

8~ 0 >-:

UJ ~

(T)

w Ul < I CL

ou .CD

(9

.=.! z ....... 2 .......

I~ I-

ou I-.CD

-~ ::J CL I-::J 0

c;u 0: .CD

_1/J Ul

...:.-§ co· •• li1

I

li1 ou

- I ~i w

w

0:

(f)

[6

< I

cou

......

0...

IH(!) 1-- lL

-r·~ -co

r--U "CD .oo

E

uw Nl-

<~ I::J

t _J

~0... ,Ul

-I-00~

N::J oa::o -u

-o •+ .... u ~m

-44-

I .j:>. .j:>. I

AC LINE

121kHz OUTPUT

'+100 MICRO­

SECONDS

PHASE 1

foE-'-.;.?.?c~ _j 1-EJ--------.J. 556

msec

~s"e0 I ra-e 11.0 1 hisec

BIT

lt.o 1 ~sec

PHASE 2 PHASE 3

l·t .o I msed

11.0 1 hi sec ll.o 1 ~sec

BIT

FIGURE 5-5: BSR OUTPUT TIMING

Synchronization with the line is very critical since the receivers

use the zero crossing as a strobe to sample the line for the presence

of the carrier. This synchronization is accomplished by utilizing a

"software phase-locked-loop", or SPLL, the flow ch.art of which is

shown in Figures 5-6 an:i 5-7. Figure 5-8 shows one cycle of the A-C

line and the contents of a counter CURDIG, which is also used in

Section 3.1.1.

When the system is first powered up, the CURDIG counter and the A-C

line are not synchronized. Internal timer interrupts every 1. 28

milliseconds cause the CURDIG counter to count down from twelve to

one. A total of 15.36 milliseconds has elapsed when the counter

reaches zero, and during this countdown interval the external

interrupts by the A-C line have been disabled. Counts 0 and -1 enable

the external interrupts, which are caused by the negative zero

crossing of the A-C line. The time period when .the external

interrupts are enabled is called the external interrupt window, or EXT

INT window. If the negative zero crossing does not occur during this

window, the external interrupts are again disabled, and the CURDIG

counter is reset to 12. This technique yields a free-running, i.e. no

interrupts, frequency of 55.8 Hertz (17.91 milliseconds) which results

in a nominal beat frequency of 4.2 Hertz with the 60 Hertz line.

Since the two frequencies are not identical, the phase relationship

between the two wavefol'!lls changes with time until the negative zero

crossing occurs during the EXT INT window. ~nen an external interrupt

is sensed, the timer is reset and the CURDIG counter is reloaded to

12. By resetting the timer, the unit has guaranteed that the next

zero crossing will occur during the EXT INT window, and the unit is

therefore synchronized with the A-C line. The window has been chosen

-45-

RELOAD TIMER

DISABLE EXT INT

CURDIG= 12

CALL TRANSMIT

INCREMENT TIME

CALL CONTROL

FIGURE 5-6; SPLL EXTERNAL INTERRUPT FLOW CHART

-46-

RELOAD TIMER

DECREMENT CUROIG

N

BLANK DISPLAY

ENABLE EXT INT

RESET 121kHz OSC.

·cALL TRANSMIT

. F I GURE 5-7 : SPLL TIMER INTERRUPT FLOW CHART

-47-

EXTERNAL INTERRUPT GENERATED

EXTERNAL INTERRUPTS

Ef'.VSLED

-

AC LINE VOLTAGE

CURDIG COUNTER tNOT LOCKEDl

I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 1-1 112111 110 I 9 I 8 I 7 I I I I I

"111 "1"

.I EXTERNAL

INTERRUPTS ENABLED

''0"

121kHz SIGNAL (SINGLE PHASEl

121kHz SIGNAL (MULTI -PHASE)

FIGURE 5-8: LINE SYNCHRONIZATION -48-

large enough to allow for normal variations in both the A-C line

frequency and the microprocessor clock frequency.

The actual zero crossing detection circuit is shown in Figure 5-9.

Isolation from the line is accomplished via atransformer, T1, which is

a part of the power supply section. The 24 volt winding voltage, '

which is used to supply the display, is passed through a single stage

low-pass R-C filter, and then directly into the interrupt pin of the

processor. High frequency noise which would cause false triggering is

eliminated by the filter, however the pole of this filter cannot be

too low in frequency, or the resultant phase-shift would cause errors

in the proper zero cross detection. Some compensation for this phase

shift has been designed into the system by virtue of the finite

threshold of the interrupt pin. Since the transformer winding is

referenced to ground, an ideal zero crossing detector would detect the

transition of the signal through the ground level. Interrupts are

generated by a negative transition, and the threshold of the interrupt

pin is a minimn~ of 0.8 volts (INTEL 80]. An interrupt is therefore

generated early, creating a negative phase shift as shown in Figure

5-10. Examination of the BSR format specification indicates an

extremely tight specification ( + 100 microseconds ) on the delay

between the actual zero crossing and the start of a bit [BSR ??]. An

understanding of the receiver reveals that starting a bit early is

acceptable since the receiver uses the zero crossing as a strobe to

sample the line for the carrier. Starting a bit late, however, can

not .be tolerated. By starting the bit early, less accurate zero

crossing detection is required for proper operation. This early start

technique is exploited to a minor degree on the negative zero crossing

due to the positive threshold of the interrupt pin. More importantly,

-49-

POWER TRANSFORMER Tl

120 VAC LINE

+5 VOLT SUPPLY

48VOLT C.T.

8039

FIGURE 5-9: ZERO CROSSING DETECTOR

+0.8 VOLTS

ZERO CROSSING DETECTED BY

PROCESSOR

AC LINE

PHASE SHIFTED VOLTAGE ·

TRUE ZERO CROSSING

TIME

FIGURE 5-10: ZERO CROSSING PHASE SHIFT -50-

it is utilized on timer interrupt six ( see Figure '5-8 ) , which is

used to predict the positive zero crossing, and occurs 0.653

milliseconds or 14 electrical degrees prior to the actual positive

zero crossin~. By relying on the internal timer and using the early

start technique, the need to detect the actual positive zero crossing

was eliminated.

5.3 CODE SYNTHESIS

Every time an external interrupt (Figure 5-6) or timer interrupt

six (Figure ?-7) occurs, the TRANSMIT subroutine is called to

determine if a bit should be sent, an1 if so, whether it is a one or a

zero. Fi~ures 5-11 and 5-12 show the flow chart of the TRANSMIT

subroutine. As was previously discussed in Chapter 4, the TRANSMIT

subroutine checks a state counter to ~ee if transmission is required.

If transmission is requested (state counter equal to one) or underway

(state counter greater than one) the TRANSMIT subroutine determines

the proper bit. The bit is determined in real time, and is another

approach that is made possible by the early start strategy.

Due to the word being 22 bits long and of variable format, it was

decided to break the words into the three segments mentioned in

Section 5.1 and to synthesize the words from these segments. Upon

entering the TRANSMIT subroutine, a check is made of the state counter

to determine what section of a word is being transmitted. There are

fifteen states as shown in Figure 5-13. Bit patterns for each section

are stored in table for:n in the read only memory (ROM), and these

tables are scanned by the TRANSMIT routine to determine the proper

bit. This scanning is two dimensional in nature with one pointer

incrementing each time a bit is transmi tterl, and the other pointer

-51-

GET STATE COUNTER

LOAD SCANNING POINTER WITH

PROPER ADDRESS

LOAD BYTE POINTER WITH

PROPER ADDRESS

ADD SCANNING POINTER TO

BIT COUNTER

GET BYTE POINTER TO

RETURN

LATCH STATUS TO DISPLAY

LEOs

INCREMENT UNIT COUNTER

SET STATE COUNTER TO

ZERO

SET UNIT COUNTER TO

ZERO

RETURN

SET STATE COUNTER TO

1

FIGURE 5-11: TRANSMIT FLOW CHART

-52-

AND WITH BYTE POINTER TO BY BYTE POINTER

RESET CONTROL PIN LOW

INCREMENT BIT COUNTER

GET NEXT BYTE

INCREMENT STATE COUNTER

SET BIT COUNTER TO

ZERO

y

SET CONTROL PIN HIGH

RETURN

FIGURE 5-12: TRANSMIT FLOW CHART (CONTJ

-53-

STATE SECTION STATE SECTION

0 IDLE (NOP) 1 START 8 START 2 SECURITY 9 SECURITY 3 UNIT 10 OPERATIC~

4 START 11 START 5 SECURITY 12 SECURITY 6 UNIT 13 OPERATION 7 DELA.Y 14 DELAY

Figure 5-13: TRANSMIT STATES

being set at the start of a particular section of the word. In order

to be efficient in HOI~ usage, both vertical and horizontal scanning

were utilized. Figure 5-14 shows the ROM table for the unit section.

After the present bit has been determined,

87654321 UNIT NUMBER

DB 10101010B ;D8 DB 01010101B ;-'08 DB 11000011 B ;D4 DB 00111100B ;-D4 DB 00001111B ;D2 DB 11110000B ;-'02 DB 11110000B ;D1 DB 00001111B ;-D1 DB OQOOOOOOB ;D16 DB 11111111B ;-D16 DB 11000000B ;FLAG

Figure 5-14: UNIT SECTION ROM TABLE

the next byte is fetched from ROM, and compared to the end of section

flag. If this next byte is the end of section flag, the state counter

is advanced, and the bit counter is zeroed in preparation for the next

section. If the state counter is greater than 14, it is reset to 1 ,

and the unit counter is advanced. This action causes a complete

message, with the appropriate unit code and operation code, to be

-54-

transmitted for each of the eight loads. After all eight loads have

been signaled, the state counter is returned to zero to a~ain idle the

TRANSMIT routine. Transmission of the eight loads requires seven

seconds, and is executed every time a load status is changed, and

additionally every sixteen minutes. The extra transmission every

sixteen minutes is to insure that the loads are in the proper state,

since the processor cannot observe the state directly. This is also

the reason for transmitting the entire eight loads rather than just

transmitting to the load that was changed.

For single phase control it is necessary to inject the carrier only

during a short time ( 1 millisecond ) following the zero crossing.

This is implemented by resetting the 121kHz oscillator on timer

interrupt counts eleven and four as shown in Figure 5-B. For multiple

phase control the transmitter would only change states at the external

interrupt or timer count six. This would result in the carrier being

transmitted for the entire half cycle. An inherent benefit over the

BSR system is obtained using this technique, namely that any phase can . be controlled. The BSR standard format transmits only at specific

phase angles (0,60,120) and cannot control loads on other phase angles

such as 30 degrees.

5.4 CARRIER GENERATION

The 121kHz carrier is generated by the circuit shown in Figure

5-15, and consists of two basic sections. An oscillator consisting of

a 555 timer integrated circuit, generates the fundamental 121kHz

square wave. Trimming of the frequency is accomplished via the

trimmer potentiometer R2. Resistors R1, R2 and capacitor C1 serve to

determine the frequency of the carrier. The oscillator is gated on

-55-

I

tn ()) I

CONTROL LINE FROM PROCESSOR

R3 lOk

+12v C3 +5v 0.22 ~f'

C2

"llllri~ 2200 +5v I I pf' I

8 3 I < r\.1 I

~ AC

POWER LINE

I ~ I 7

LM555 I R2 SOk

2 I I I/ Ql

4 Cl 6

1 5 I lOOpf'

C4 IO.lf-Jf'

FIGURE 5-15: TRANSMITTER HARDWARE SCHEMATIC

I m 0)

I

CONTROL LINE FROM PROCESSOR

R3 lOk

+5v

8 3

LM555

4 1 5

2

6

R2 SOk

C4 IO.lf-Jf'

+5v

C1 lOOpf'

+12v

C2 2200

pf'

01

C3

--o-·~22 r:-AC

POWE LIN

FIGURE 5-15: TRANSMITTER HARDWARE SCHEMATIC

and off by a signal from the processor through R? to the enable pin of

the 55?. A high level on this pin starts the oscillator. The output

of the 555 is then connected to the second section through resistor

R4.

Amplification and wave shapin~ are accomplished in the second

section by employing an NP~ transistor and a tuned isolation

transformer stage. The output from the oscillator drives the NPN

common emitter amplifier, with the collector current being su!lplied

through the primary of the isolation transformer. This transformer

consists of three windings; the primary, a secondary for tuning, and a

secondary for couplin~ to the A-C line. The inductance of all three

windings can be simultaneously varied by a slug over the core. This

variability is used to adjust the frequency where C2 and the secondary

resonate, and is set for the carrier frequency of 121kHz. Since the

secondary is resonating, the output of the second secondary is very

nearly sinusoidal. The output of the secondary is of very low

impedance and couples the carrier signal into the line through

coupling capacitor C?. Resistor R5 is used to degrade the Q of the

tuned circuit, which is required in order to have the carrier decay

sufficiently fast when the oscillator turns off.

Chapter 6 will describe the conclusions of this work, and will also

suggest some areas for future research.

-57-

6.1 SUMMARY

CHAPTER 6

CONCLUSIONS

The work performed in this thesis . has demonstrated a compact and

cost effective controller for residential electricity demand control.

All the ~?;Oals which were set forth at the inception of the project

were met. Theories for synthesizing the functions of the BSR

transmitter chip through software, were demonstrated with excellent

results. Improvements over the BSR technique were also shown in the

area of multi-phase control.

Laboratory experiments have indicated satisfactory results with the

final algorithm, however actual field testing was not conducted. Work

outside the scope of this thesis, in the area of computer simulation

of the controller in a typical residence, is being conducted within

the ECE department. Six prototypes have been constructed and should

be installed in residences by PP&L durin~ the fall of 1992.

A patent disclosure of this work has been filed with the Lehigh

University Office of Research. Lehigh University and PP&L are

currently negotiating an agreement to commercialize the device

presented.

6.2 AREAS FOR FUTURE WORK

Several areas for future work are indicated by this thesis. The

first area is the field testing of the controller to determine the

effectiveness of the control algorithm, and to ascertain the cost

savings to the consumer. This investigation should be underway based

-58-

on the testing of the six units mentioned above.

Secondly, an analysis should be made to establish the need for a

minimum or maximu:n off-time for compressor type loads. The minimum

off-time would prevent "sluggin~" a compressor, which is the condition

when a compressor starts against a high dischar~e pressure. A maximum

off-time would be desirable to prevent thawing in refrigerators and

freezers.

A third area would be to generate an adaptive predictor algori th.'ll

which estimates the demand of each individual load. This algorithm

would extract the demand for each load from the historic data, and

would then be used to select which load{s) would be shed or restored.

The incorporation of a means for utility communications to the

controller should be investigated. This hybrid approach would allow

the utility to synchronize the clock, alter rate structures, or

request block load shedding. Communications from the utility could be

accomplished by power line carrier, ripple control, radio control, or

zero-crossing shift techniques. If power line carrier is used, an

alte!nate frequency, or different coding than the BSR technique would

be required.

Finally, an investigation could

feasibility of custom integration,

be made

using VLSI

ancillary functions onto the same chip as the

to determine the

technology, of the

CPU. This would

eliminate all the components except the transformer, display, and the

keyboard. Additional features can also be included without increasing

the cost significantly.

-59-

~APS 821

(BLAIR 821

(BSR '??1

~CHAI 821

~CONVERSE 75]

riNTEL 80)

(INTEL 821

(LIHACH 821

(NEC 79]

I:ORNL81l

REFERENCES

Energy Control Devices Buyer's Guide New Enlarged edition, Arizonia Public Service, P.O. Box

21666, Pheonix, AZ 850;6, 1982.

Blair, William. Communication systems for distribution automation and

load management. EPRI Journal 7(4):41-42, May, 1982.

BSR (USA) Limited. ELBCTRICAL APPLIANC~ CONTROL - TRANSMITTER CHIP NO.

542C. Date published: Unknown.

Chai, D. T. and Hoekstra, T. B. Getting a line on energy use. Bell Laboratories Record 60(4):78-82, April, 1982.

Converse, A. 0. and Laaspere, T. Creative Electric Load Management. IEEE Spectrum 12:46-50, February, 1975.

MCS-48 User's Manual INTE~Corporation, Santa Clara, CA, 1980.

Microcontroller Applications Handbook INT~L Corporation, Santa Clara, CA, 1982.

Lihach, Nadine. The Load Management Decision. EPRI Journal 7(4):14-19, May, 1982.

Technical Information on NEC Fluorescent Indicator Panel (FIP --NEC Electron, Inc., Santa Clara, CA, 1979. FEB-1002A.

Blevins, Robert P. Survey of Utility Load Management Projects. Third Revised Report ORNL/Sub-80/1?644/1, Ener~y

Utilization Systems, Inc., October, 1981. Work performed for the Oak Ridge National Laboratory.

-60-

fpoWERS 751 System ?70 Software Program, Electric Demand Limiting Powers Regulator Company, Skokie,Illinois, 1975. Application Bulletin AB-408.

lRATE RS 81] PP&L. RATF. SCHEDULE RS, RESIDENTIAL SERVICE. Supplement No. 77, Electric Pa. P.U.C. No. 198. Page No. 19,19A, Issued February 3, 1981.

~RATE RX(R) 81 ] PP&L.

( SCITRONICS 82 J

RATE SCHEDULE RX(R), RESIDENTIAL SERVICE-EXPERIMENTAL RATE.

Supplement No. 77, Electric Pa. P.U.C. No. 198. Page No. 38, Issued February 3, 1981.

EnerMizer-! The Computer Based Energy Control System Scitronics, Inc., 523 S. Clewell St., Bethlehem, PA

1 90 1 5 ' 1 982 •

[VENNARD 701 Vennard, Edwin. The Electric Power Business. McGraw-Hill, Inc , 1970.

(WARTON 80] Warton, John. AP-40 Keyboard/ Display Scanning With Intel's MCS-48

Microcomputers. 8048 Family Applications Handbook :3-1 to 3-26, ---yanuary, 1980.

-61-

APPENDIX A

SYSTEM SCHEMATICS

This appendix contains the co~plete schematics of the Electricity

Demand Controller described in the preceeding chapters.

-62-

1~ 1

·' 2, 120 FIP 6C13 DISPLAY

Ntnm (T)(DOl--- o~~tnf'mCOt'C> ........ _....., ..... 3> '"29VOL TS rl 0 ~ =f +5 ~ ,_.1\/\/\/\,- _

29 _

4s-+SVOLTS \7 1 n °

0 ¥ I 00 00 II II I J

12 ~ rr=r+5 r 5 1 N(T)~f'28 ~f'39 9 ¢ 78 6 39 38 10 Q) 6 8 8 8 8 37 11 ¢ 5. 9 30 9 9 36 12 (T) 1t

10 29 10 10 35 14 u 21 I I l 11.... 26 11 11 34 15 ~ '·

7-- 4 12 12 r- 13co~ 3

~ ! +5 13 13 _.. m

~ i~ ~~ 8755 L ~ ~ 8039 16 16 +5 j_ -? > 17 17 31

1 18 18 30 9 ~ m 1 ffi 19 19 29 10 ¢ 2 I ~z '\Z ~z 21 21 28 11 m 3

-29

-,- 7 -,- 22 22 27 12 ¢ 4 ~J\J\J\_ 23 23 26 13 (T) 5 I ~vvvv- 33 20 20 25 14 0 ~

-'V\IV'v 32 ~ ~ . 24 15 :2 7 +5 r ~ Wh3lr~f~ ~ ;- 7 ~ ~ ~ t ~ ~ +klJ~ ~ ~ ~ ~ t ~ I I II M L K ~ ~ 13(T) 6 ~ ~ ~ ~ ~ ~ V H 14(0 9

6 4x4 4 ~12 3 UJ15 KEYBOARD 18_l 16

L F 17¢19 E 11('.2

J:l 5 \7' 10

FIGURE A-1: SYSTEM SCHEMATIC (PAGE 1)

I

ffi I

1

1 1

1' 1 FIP 6C13 2" 20 DISPLAY 3> rio~ t +5 Ntnm O¢¢tnl'mCOI'O> --29VOLTS +5

~-29 PHD 0> _. _. _, .......... _.. ..........

4>--+5VOLTS I 2) ~ rn::-+5 r 5 l N(T}~I'-28 01'39 9 ¢7 1---

¢ 38 6 39 10 Q) 6 8 e 8 8 37 11 V' 5 9, 30 9 9 36 12 (T)4 0{ 29 10 10 35 14 u 2 1.{ 26 11 11 34 15 1 7, 4 12 12 r- 13m2 3

~ ~ ~ +5 13 13 _. m

14 14 8755 I 15 15 -29 8039 16 16 +5 I > ~ 17 17 31

9~ m 1 18 18 30 I 19 19 29 10 ¢2 ~~ ~ ~ ~~ 21 21 28 11m3

22 22 27 12 'lit- 4

\n ~33 23 23 26 13 (T) 5 20 210. 25 l~ 0 7 ,__. 24

~~ NV'v-32 - 4 ::2: + \n AI\N'v - 7 ~ > -; ~

+fu~tttt~ j v 31ml'cotn " \7 _ff_ff ('l')(t)(T)(T} N

I I I I I I '-7 N(> < <<<~

'f\1 M L K ~ .__ 8 (l) ? ? ? ? > ,> ? ~ 13 6 _..

H 14(0 9 G 4x4 4 (l) 12 F KEYBOARD

3 (f) 15 18-116 17¢19

5

E 11('.2 f 1 5 10

FIGURE A-1: SYSTEM SCHEMATIC (PAGE 1)

I

0> ..;..

I

1 ~----------------------------------~

2~--------------------------~-------J\

3~-+5 12 ~ 6 FROM ~ ~METER

: < x r r J V Sz t !23..fuM-s 1~-~ 3

5-f---i----------+-----l

LM339

7 ( I I I I I ,,1 11 +-+------'

~ .?+5' ~ I

10~ -2 "AA" -;:r;- FROM N I CADS

9 v ~METER T

FIGURE A-2: SYSTEM SCHEMATIC

AC • 1 LINE

I m ~ I

1 ~--------------------------------~

2~------------------------~----~~

~~ rs T 6~ FROM

1Qr METER

8 ~---lt------J LM

4 ~·-------------~__.l'----11.----....--!2340-5tt--P'-1P----o 3

LM339

T 1>+5. ~ 2 .. ,..,.. ..

0~1\1\~ --NlC/1.05 1 ~_l_ vvv- ~FROM

1Qr ~METER T 9 ~----------------"

FIGURE A-2: SYSTEM SCHEMATIC (PAGE 21

VITA

James A. Butt, son of Leon and Julia Butt, was born in Boyertown,

~a in 1951. He received a B.S. degree in Electrical Engineering from

Lehigh University in June, 1973. After gradu~tin~, he was employed by

Philco-Ford Corp, Lansdale, Pa until September, 1976, when he was

transferred to the Electrical and Electronics Division of Ford Motor

Company, Dearborn, Michigan. He achieved the level of Senior

Engineer, and did advanced design of automotive electronics. He

received his Professional Engineering License in 1980 (Mich .1127503).

In 1980 he took an educational leave of absence to pursue an M.S.

degree at Lehigh University. While pursuing the M.s. degree, he

worked as a research assistant and as a teaching assistant in the

Electrical and Computer Engineering department.

Mr. Butt is a member of the IEEF., and the following IEEE societies:

Computer, Control Systems, Industrial Electronics and Control

Instrumentation, Industrial Applications, and Power Engineerinf?;. He

is also a member of the Lehigh Valley Solar Energy Association, and

the Mid-Atlantic Solar Energy Association. Mr. Butt is currently

employed by Lehigh University as a Research En~ineer for the Energy

Research Center, and as an Adjunct Lecturer to the Electrical and

Computer Engineering department.

-6'5-