Deepak Cv3
3
T. Deepak Reddy Address: 1-88/1/B, E-mail :[email protected] BALAJI NAGAR, phone no: 9989649926 GUTTALA BEGUMPET, MADHAPUR, HYDERABAD, TELANGANA,500081. CAREER OBJECTIVE: To build a career that offer challenge and growth with opportunities in a competitive environment to enrich my knowledge and skills while contributing my best to the organization I work for. EDUCATION QUALIFICATIONS: Qualification School/College Board / University Year of passing CGPA/ % of Marks B.Tech GITAM Institute of Technology GITAM University 2015 7.67 (till seventh semester) Intermediate Sri Chaitanya Junior Collage Board of Intermediate Education, Andhra Pradesh 2011 88.3 % S S C GEETANJALI Talent School Board of Secondary Education 2009 78.5 % TECHNICAL SKILLS:
description
deepak reeddddduyb
Transcript of Deepak Cv3
T. Deepak Reddy
Address: 1-88/1/B, E-mail :[email protected]
BALAJI NAGAR, phone no: 9989649926 GUTTALA BEGUMPET, MADHAPUR, HYDERABAD, TELANGANA,500081.
CAREER OBJECTIVE:
To build a career that offer challenge and growth with opportunities in a competitive environment to enrich my knowledge and skills while contributing my best to the organization I work for.
EDUCATION QUALIFICATIONS:
Qualification School/College Board / University Year of passingCGPA/
% of Marks
B.Tech
GITAM Institute of Technology
GITAM University2015
7.67 (till seventh semester)
Intermediate
Sri Chaitanya Junior Collage
Board of Intermediate Education, Andhra Pradesh 2011 88.3 %
S S CGEETANJALI Talent School
Board of Secondary Education 2009 78.5 %
TECHNICAL SKILLS:
• Programming Language : C• Hardware description language: Verilog HDL• Simulation software: TOPSPICE
INTERNSHIP: A New Approach for FEC Decoding based on BP ALGORITHM in LTE and WIMAX Systems Description: The main aim of the project is to design a decoder which decodes both LTE and WIMAX systems using BP algorithm which exploits the existing algorithms that results in reduction in complexity of the systems.
PROJECT [PURSUING]: Implementation of low area memory free AES algorithm.
Description : AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation offers lower cost, quicker and more Customizable solution. We implemented AES in FPGA with minimum latency and speedy throughput where Verilog HDL is used to simulate the operations.
EXTRA-CURRICULAR ACTIVITIES: Participated in Science Activities, Computer literacy and pot painting organized by NSS during the
period 24/3/14 to 30/3/14 Participated in workshop on Digital Signal and Image processing organized by IEEE Student chapter of
GITAM University Participated in workshop on Optical Fiber Communications and Photonics conducted by department
of ECE on 22nd February, 2014.
KEY SKILLS:
Quick Lerner Leadership and team work abilities Can do attitude
PERSONAL PROFILE:
Name : T. Deepak reddyFather’s Name : T. Venkateswara reddyMother’s Name : T. LaxmiNationality : IndianDate of Birth : 24 AUGEST 1994Hobbies : Playing Cricket, Watching MoviesLanguages Known : Telugu and English.
DECLARATION:
I hereby declare that the details furnished above are true and correct to the best of my knowledge belie.
Date: 23-03-2015,
Place: Visakhapatnam T. Deepak reddy
