Deep Sub-Micron Technology - National Chiao Tung...

Consulting & Engineering Serviceswww.tanner.com/ces

CE-LI-CC-IOmosis025

Tanner Research, Inc.

Tanner Consulting & Engineering Services

Presenting

Hi-ESD IO Pad Libraryfor

MOSIS TSMC CMOS025 ProcessDeep Sub-Micron Technology

mTSMd 0.25mTSMd 0.25µµ


CE-LI-PR-CE

TANNER CES GENERAL TERMS & CONDITIONSLiability

All designs will be implemented under the Client’s front-end specification. Our contracted engineering services are accomplished for theClient on a best effort basis. Quality assurance is achieved by arriving at a common understanding of the nature of the Project among the

engineers and managers at the Client operation and at Tanner CES. Tanner Research is not liable for the functionality, quality, orperformance of the Client’s future Projects using components produced as part of the contracted work. Tanner Research is not liable if

the Client chooses to use our recommended design or application methodologies. If prototype chips are delivered, the process vendors donot generally guarantee yield, quality, or performance of their products. Neither does Tanner Research extend any warrantee to the

contracted design and its fabricated results.

Non-Disclosure Agreement

Non-disclosure agreements (NDAs) serve the following purposes.

oo Signed between the Client and Tanner Research, the NDA protects Client’s original concept, status, and intentions in currentand future product development and manufacturing.

oo Signed between the Client and Tanner Research, the NDA protects Tanner Research’ specific technologies, IC libraries,building blocks and methodologies that are developed prior to the Client Project, or developed specifically for the Clientapplication.

oo Specific non-disclosure or non-distribution conditions may be added to the Statement of Work for individual Client Projects.These conditions do not replace or supercede any previously signed NDA; rather they serve as additional constraints to theNDA.

oo During or at the end of the Client Project, if we communicate with a process vendor or receive fabricated parts from aprocess vendor which will be forwarded to the Client, we assume that the Client is also a current customer of the vendor. Wemay request Client to provide a proof of its NDA with the vendor before any such communication or transaction.

Ownership of Work Results

The Client owns the delivered version and the fabricated version of the work results from a contracted Client Project. Theseresults are subject to the following re-distribution conditions:

oo The Client agrees to use the work results only in its own Projects or products, as developed by the Client and on the Client’sown site.

oo The Client will not distribute copies of the delivered data files and documents (such as design, libraries, process technologysetups, design flows and methodologies, software utilities, etc.) to any third parties or to any other Client site, with thefollowing two exceptions:

Exception 1: If applicable, results can be delivered to the Government Agency sponsoring the Client Project, if such deliveryis negotiated as part of the Client Project. During contract negotiations, the Client shall inform Tanner Research aboutsuch a delivery and receive advance agreement from us for the contents to be disclosed.

Exception 2: If applicable, results can be incorporated into published academic research or presented for academic purposes.During contract negotiation, the Client shall inform Tanner Research about such a presentation and receive advancedagreement from us for the contents to be disclosed.

Any other exceptions shall be specified in a written document signed by both the Client and Tanner Research.

Tanner Research does not own the original design and application concepts from the Client. We agree not to disclose the Client’sproprietary design and applications information. However, we shall distinguish the following items that remain the property ofTanner Research:

oo The methodology used through the development of the Client Project, or that we planned for Client to apply the Project’sresults, are usually either common knowledge in the industry or specific methods invented by Tanner Research. Using oradopting these methodologies in the Client Project does not institute the Client’s ownership to these methodologies.

oo Client does not own Tanner Research’s general-purpose building elements (such as cell libraries, building blocks, IO padcells, etc.) that we utilize in a contracted Project. These building elements are Tanner Research’s current design resourcesthat are widely used internally and/or distributed as commercial products. Using these building elements does not institutethe Client’s ownership of them.

Protect Tanner Research’s Engineering Resources

Through the entire Client Project cycle, starting from bid and proposal to the end of the Project, the Client will contact variousengineering resources within Tanner Research. These resources may include Tanner Research’s employees and its associates

(subcontracting firms or individuals). The Client agrees not to recruit or hire any of these individuals or contract with any firms duringthe three years following Project completion.

ooþþ


CE-LI-CC-IOmosis025

Tanner Research, Inc.

Table of Contents

Analog Reference Pad: .................................................................................... PadAref

Bi-Directional Pad with Buffer: .................................................................. PadBiDirHe

Ground Pad: ...................................................................................................... PadGnd

Input Pad with Buffer: ........................................................................................PadInC

I/O Pad: ................................................................................................................. PadIO

PadlessCorner Pad: ..............................................................................PadlessCorner

Padless Spacer Pad: ............................................................................ PadlessSpacer

Pad No Connect Pad: ............................................................................ PadNoConnect

Output Pad with Buffer: ..................................................................................... PadOut

Power Pad: ........................................................................................................ PadVdd

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

A

A B

B C

C D

D E

E F

F

1 1

22

3 3

44

5 5

G

G

Size: 5x7

Rev A

Path:O:\ces_prjct\mosis\library025u\work_dir\databook\pads\HiESD_Pad_TSMC025

Module:Pad_Frame Page:Page0

Designer:Tanner CES Library Development Team

Info:MOSIS TSMC 0.25um Hi-ESD IO Pad Set

Modified:Aug 25, 1999 15:22:53Created:Nov 9, 1998 15:15:18

Tel: (626)792-3000

2650 East Foothill Blvd, Pasadena, CA 91107Fax: (626)792-0300

0.9 mm

(7500 lambda)

0.9 mm(7500 lambda)

(750 lambda)pitch = 0.09 mm

1.5 mm(12500 lambda)

1.5 mm

(12500 lambda)

MOSIS TSMC 0.25umHi-ESD Minimum Pad Frame

(1) lambda = 0.12um

Size: 5x7Created:Nov 9, 1998 15:15:18Modified:Aug 25, 1999 15:22:53



Page:Page0Module:Pad_Frame


Rev A

Fax: (626)792-03002650 East Foothill Blvd, Pasadena, CA 91107

Tel: (626)792-3000

Tel: (626)792-3000

2650 East Foothill Blvd, Pasadena, CA 91107Fax: (626)792-0300

Rev A


Module:Pad_Dimension Page:Page0



Modified:Sep 28, 1999 14:53:54Created:Nov 9, 1998 13:20:00

A

A B

B C

C D

D E

E F

F

1 1

22

3 3

44

5 5

G

G

Size: 5x7

231 micron

51.12 micron

90 micron

(750 lambda)300 micron

78.96 micron

(658 lambda)

78.96 micron

60 micron

(500 lambda)

(1) lambda = 0.12um

Hi-ESD Pad DimensionsMOSIS TSMC 0.25um

(426 lambda)

(1925 lambda)

(2500 lambda)

(658 lambda)

BONDINGPAD

ESD TRANSISTORPMOS

PADLOGIC

ESD TRANSISTORNMOS

60 micron

LOGICPAD

NMOSESD TRANSISTOR

ESD TRANSISTORPMOS

pitch = 90 micron

(750 lambda)

PADBONDING

(500 lambda)

Fax: (626)792-03002650 East Foothill Blvd, Pasadena, CA 91107

Tel: (626)792-3000

Created:Nov 9, 1998 13:20:00Modified:Sep 28, 1999 14:53:54



Page:Page0Module:Pad_Dimension


Rev A

Size: 5x7

mTSMd025P – MOSIS TSMC 0.25µµmHi-ESD Pad Cell Library

Rev. APADLIB

Page1 of 4

Copyright 1999 by Tanner Research, Inc. All rights reserved.

Pad Library PADLIB

Description: Pad Library

Library: MOSIS TSMd025P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples

Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: Library

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: Lib_Pads

Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac

Logic Symbol Truth Table Capacitance

N/A N/A N/A

Height Width Area Equivalent Gate DriveN/A N/A N/A N/A N/A

Logic Equation

N/A

Delay Characteristics: N/A

µµmHi-ESD Pad Cell Library

Rev. APADLIB

Page2 of 4


Pad Library PADLIB

This page is intentionally left blank.


Rev. APADLIB

Page3 of 4


Pad Library Schematic PADLIB

Hi-ESD IO PAD SET

Inpu

t Pa

d wi

th B

uffe

r

Outp

ut P

ad w

ith

Buff

er

Vdd

Pad

with

ESD

Gnd

Pad

with

ESD

Anal

og R

efer

ence

Pad

wit

h ES

DAn

alog

IO

Pad

with

ESD

MOSIS TSMC 0.25um - Deep Submicron Rules

PadO

ut_S

CMOS

PadI

nC_S

CMOS

PadV

ddPa

dGnd

PadI

OPa

dARe

f


Rev. APADLIB

Page4 of 4


Pad Library Layout PADLIB


Rev. APADFRAME

Page1 of 4


Pad Frame PADFRAME

Description: Pad Frame


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: N/A

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025.tdbCell: FRAME



N/A N/A N/A

Height Width Area Equivalent Gate Drive1.5 mm 1.5 mm 2.25 mm2 N/A N/A

Logic Equation

N/A



Rev. APADFRAME

Page2 of 4


Pad Frame PADFRAME



Rev. APADFRAME

Page3 of 4


Pad Frame Schematic PADFRAME

N/A


Rev. APADFRAME

Page4 of 4


Pad Frame Layout PADFRAME


Rev. APADAREF

Page1 of 4


Analog Ref Pad PADAREF

Description: Analog Reference Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADAREF

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADAREF



N/A N/A

Height Width Area Equivalent Gate Drive300 µ 90 µ 27000 µ2 N/A N/A

Logic Equation

N/A

Delay Characteristics:

C[SIGNAL]24.40.........1TpdC[SIGNAL]23.51.........Tpd0

×+→×+→

PadARef


Rev. APADAREF

Page2 of 4


Analog Ref Pad PADAREF



Rev. APADAREF

Page3 of 4


Analog Ref Pad Schematic PADAREF

SIGNALSIGNAL

PadARef

L='4*l'M=16

TESDP W='297*l'

BONDING

PAD

L='4*l'M=16

TESDN W='297*l'


Rev. APADAREF

Page4 of 4


Analog Ref Pad Layout PADAREF


Rev. APADBIDIR

Page1 of 4


Bi-Directional Pad PADBIDIR

Description: Bi-Directional Pad with Buffer


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADBIDIR

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADBIDIR



N/A


Logic Equation

See truth table


C[DIUNBUF]24.40.........1TpdC[DIUNBUF]23.51.........Tpd0

C[DIB]49.120.........1TpdC[DIB]54.261.........Tpd0C[DI]74.310.........1TpdC[DI]79.191.........Tpd0

×+→×+→

×+→×+→×+→×+→

C[DO]1.2100.........1TpdC[DO]1.1811.........Tpd0

×+→×+→

PAD OE DI DOX 1 X In1 0 1 X0 0 0 X

PadBidirHE_SCMOS


Rev. APADBIDIR

Page2 of 4


Bi-Directional Pad PADBIDIR



Rev. APADBIDIR

Page3 of 4


Bi-Directional Pad Schematic PADBIDIR

OEOEB

OEB

OEB

OE OE

DataIn

DataInB

PadDataOut

EN

DataInUnBuf

R1200

L='4

*l'

M=4

TESD

P1W=

'297

*l'

L='3

*l'

T14a

W='5

2*l'

L='3

*l'

M=6

T11

W='5

2*l'

L='3

*l'

M=6

T9W=

'52*

l'L=

'4*l

'M=

12

TESD

P2W=

'297

*l'

L='3

*l'

M=5

T4W=

'52*

l'

L='3

*l'

M=4

T2W=

'52*

l'

L='3

*l'

M=5

T1W=

'52*

l'

L='3

*l'

T13a

W='5

2*l'

BOND

ING PAD

L='4

*l'

M=1

TESD

N1W=

'297

*l'

L='3

*l'

T14b

W='3

0*l'

L='3

*l'

M=6

T12

W='3

0*l'

L='3

*l'

M=6

T10

W='3

0*l'

L='4

*l'

M=15

TESD

N2W=

'297

*l'

L='3

*l'

M=5

T6W=

'30*

l'

L='3

*l'

M=4

T5W=

'30*

l'

L='3

*l'

M=5

T3W=

'30*

l'

L='3

*l'

T13b

W='3

0*l'


Rev. APADBIDIR

Page4 of 4


Bi-Directional Pad Layout PADBIDIR


Rev. APADGND

Page1 of 4


Ground Pad PADGND

Description: Ground Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADGND

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADGND



N/A N/A


Logic Equation

N/A


PadGnd


Rev. APADGND

Page2 of 4


Ground Pad PADGND



Rev. APADGND

Page3 of 4


Ground Pad Schematic PADGND

PadGnd

Pad

L='4*l'M=16

TESDP W='297*l'

BONDING

PAD


Rev. APADGND

Page4 of 4


Ground Pad Layout PADGND


Rev. APADINC

Page1 of 4


Input Pad PADINC

Description: Buffered Input Pad with Complementary Signals


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADINC

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADINC



N/A


Logic Equation

See truth table


C[DIUNBUF]24.40.........1TpdC[DIUNBUF]23.51.........Tpd0

C[DIB]49.120.........1TpdC[DIB]54.261.........Tpd0C[DI]74.310.........1TpdC[DI]79.191.........Tpd0

×+→×+→

×+→×+→×+→×+→

PAD DI DIB0 0 11 1 0

Pad

DataInBPadInC_SCMOS

DataInPad


Rev. APADINC

Page2 of 4


Input Pad PADINC



Rev. APADINC

Page3 of 4


Input Pad Schematic PADINC

PadInC

DataInB

DataIn

Pad

Pad

PadBidirHE_SCMOS


Rev. APADINC

Page4 of 4


Input Pad Layout PADINC


Rev. APADIO

Page1 of 4


Input/Output Pad PADIO

Description: Input/Output Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADIO

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADIO



N/A N/A


Logic Equation

N/A


C[DATA]24.40.........1TpdC[DATA]23.51.........Tpd0

×+→×+→

PadIO


Rev. APADIO

Page2 of 4


Input/Output Pad PADIO



Rev. APADIO

Page3 of 4


Input/Output Pad Schematic PADIO

DATASIGNAL

PadIO

R1 200

L='4*l'M=16

TESDP W='297*l'

BONDING

PAD

L='4*l'M=16

TESDN W='297*l'


Rev. APADIO

Page4 of 4


Input/Output Pad Layout PADIO


Rev. APADFC

Page1 of 4


Padless Corner PADLC

Description: Padless Corner



Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADLC



N/A N/A N/A


Logic Equation

N/A



Rev. APADFC

Page2 of 4


Padless Corner PADLC



Rev. APADFC

Page3 of 4


Padless Corner Schematic PADLC

N/A


Rev. APADFC

Page4 of 4


Padless Corner Layout PADLC


Rev. APADSPACE

Page1 of 4


Padless Spacer PADSPACE

Description: Padless Spacer without Bonding Pad



Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADSPACE



N/A N/A N/A


Logic Equation

N/A



Rev. APADSPACE

Page2 of 4


Padless Spacer PADSPACE



Rev. APADSPACE

Page3 of 4


Padless Spacer Schematic PADSPACE

N/A


Rev. APADSPACE

Page4 of 4


Padless Spacer Layout PADSPACE


Rev. APADNC

Page1 of 4


Pad NoConnect PADNC

Description: Pad Spacer with No Connection to Bonding Pad



Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADNC



N/A N/A N/A


Logic Equation

N/A



Rev. APADNC

Page2 of 4


Pad NoConnect PADNC



Rev. APADNC

Page3 of 4


Pad NoConnect Schematic PADNC

N/A


Rev. APADNC

Page4 of 4


Pad NoConnect Layout PADNC


Rev. APADOUT

Page1 of 4


Output Pad PADOUT

Description: Output Pad with Buffer


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADOUT

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADOUT



N/A


Logic Equation


C[DO]1.2100.........1TpdC[DO]1.1811.........Tpd0

×+→×+→

PAD D00 01 1

DataOut Pad

PadOut_SCMOS

DataOutPad =


Rev. APADOUT

Page2 of 4


Output Pad PADOUT



Rev. APADOUT

Page3 of 4


Output Pad Schematic PADOUT

PadOut

DataOut

Pad

PadBidirHE_SCMOS


Rev. APADOUT

Page4 of 4


Output Pad Layout PADOUT


Rev. APADVDD

Page1 of 4


Power Pad PADVDD

Description: Power Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMd025P.sdbModule: PADVDD

Mask layout: L-Edit File: TannerLb\scmos\mTSMd025P.tdbCell: PADVDD



N/A N/A


Logic Equation

N/A


PadVdd


Rev. APADVDD

Page2 of 4


Power Pad PADVDD



Rev. APADVDD

Page3 of 4


Power Pad Schematic PADVDD

PadVdd

PadBONDING

PAD

L='4*l'M=16

TESDN W='297*l'


Rev. APADVDD

Page4 of 4


Power Pad Layout PADVDD

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