DECODER and ENCODERS

QUICK RECAP

WHY THIS QUIZ IS IMPORTANT

DECODER

• N input and M Out put• M=2n

MAIN DECODER HONN=2

M=2n

M=22=4

3x___ Decoder

MAIN DECODER HONN=3

M=2n

M=23=8

• As its name indicates, a decoder is a circuit component that decodes an input code

• each output line equals 1 at only one input combination but is equal to 0 at all other combinations

• In other words, each decoder output corresponds to a minterm of the n input variables

DESIGN 2x$

A B O1 O2 03 04

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

A’B’A’B

AB’AB

THE CIRCUIT

LETS TRY TO GENERATE TABLE

A B

0 00 11 01 1

o1 o2 o3 o4

Lets try for 000 0

0

0

0

1

1

1

0

0

11

1

1 AND 1=1

11 AND 0=0=

0

1 AND 0=0

0

0 AND 0=0

0

The “enable” input in decoders

• If the enable “E” – is zero, then all outputs are zero regardless of the

input values. – is one, then the decoder performs its normal

operation.

If E=1

1

1

1

1

If E=0

0

0

0

0

13

Decoder

ABC ABC ABC ABC ABC ABC

ABC ABC

3:8 dec

O0 O1

O2

A

B

C

Enb

S2

S1

S0

O3

O4

O5

O6

O7

A B C O0 O1 O2 O3 O4 O5 O6 O7

0 X X X 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

E

1

1

1

1

1

1

1

1

• 2-to-4,• 3-to-8,• …• n-to-2n

14

Decoder

Example: Construct a 3-to-8 decoder using two 2-to-4 decoders with enable inputs.

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

S1 S0 Q4 Q5 Q6 Q7

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

A

B

s1 s0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

s1 s0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7 0 0 0 0 Q4 Q5 Q6 Q7

0 00 1

1 0

1 1

0 00 1

1 0

1 1

Enable= 0

Example: Construct a 3-to-8 decoder using two 2-to-4 decoders with enable inputs.

S1 S0 Q0 Q1 Q2 Q3

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

S1 S0 Q4 Q5 Q6 Q7

0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

A

B

s1 s0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

Q0 Q1 Q2 Q3 0 0 0 0

s1 s0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7

0 0 0 0 Q4 Q5 Q6 Q7 0 0 0 0 Q4 Q5 Q6 Q7

0 00 1

1 0

1 1

0 00 1

1 0

1 1

Enable= 1

Decoder design with NAND gates

• Some decoders are constructed with NAND rather than AND gates.

• In this case, all decoder outputs will be 1’s except the one corresponding to the input code which will be 0.

Design example: addition

• Let’s make a circuit that adds three 1-bit inputs X, Y and Z.

• We will need two bits to represent the total; let’s call them C and S, for “carry” and “sum.” Note that C and S are two separate functions of the same inputs X, Y and Z.

• Here are a truth table and sum-of-minterms equations for C and S.

X Y Z C S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1 1 + 1 + 1 = 11

0 + 1 + 1 = 10 C(X,Y,Z) = m(3,5,6,7)S(X,Y,Z) = m(1,2,4,7)

• Here, two 3-to-8 decoders implement C and S as sums of minterms.

• The “+5V” symbol (“5 volts”) is how you represent a constant 1 or true in LogicWorks. We use it here so the decoders are always active.

Decoder-based adder

C(X,Y,Z) = m(3,5,6,7)S(X,Y,Z) = m(1,2,4,7)

•Design a two bit comparator , using suitable decoder which provides 1 as output only if

A=BA>B

A B A=B A>BA1 A2 B1 B20 0 0 0 1 00 0 0 1 0 00 0 1 0 0 00 0 1 1 0 00 1 0 0 0 10 1 0 1 1 00 1 1 0 0 00 1 1 1 0 01 0 0 0 0 11 0 0 1 0 11 0 1 0 1 01 0 1 1 0 01 1 0 0 0 11 1 0 1 0 11 1 1 0 0 11 1 1 1 1 0

A=B(A,B) = m(0,5,10,15)

A>B(A,B) = m(4,8,9,12,13,14)

Design Using Decoder

• F1 = A' B C' D + A' B' C D + A B C D• F2 = A B C' D' + A B C• F3 = (A' + B' + C' + D')

A ‘B’C’D’ A ‘B’C’D A ‘B’CD’A ‘B’CD A ‘BC’D’ A ‘BC’D A ‘BCD’ A ‘ BCD A B’C’D’ A B’C’D A B’CD’ A B’CD

A B C’D’A B C’D A B C D’ A B C D

A1

A2

B1

B2

`

0 1 2 3 4 5 6 7 8 9

10 1 1 12 13 14 15

4:16 dec

Enb

A=B(A,B) = m(0,5,10,15)

Encoders

• An encoder performs the inverse operation of a decoder,

• It has 2n inputs, and n output lines. • Only one input can be logic 1 at any given time

(active input). All other inputs must be 0’s.

Example

3:8 decoder

O0 O1

O2

A

B

C

S2

S1

S0

O3

O4

O5

O6

O7

8:3 encoder

I0 I1

I2

A

B

C

Z2

Z1

Z0

I3

I4

I5

I6

I7

30

Encoder Circuit Design• Example:

– 8-3 Binary Encoder

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

• Note that not all input combinations are valid. • Valid combinations are those which have

exactly one input equal to logic 1 while all other inputs are logic 0’s.

• Since, the number of inputs = 8, K-maps cannot be used to derive the output Boolean expressions.

32

Application

The number of inputs: large

fewer lines

Limitations• Only one input can be active at any given time• Can we Design a Circuit which can have two ones

as input

Priority Encoders

• Use a Priority Encoder which produces the output corresponding to the input with higher priority.

• In the example, if E3 = E6 = 1, the output corresponding to E6 will be produced since E6 has higher priority than E3.

I1 i2 i3 i4 o1 o2