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http://www.asic-world.com/examples/verilog/d_latch.html#Regular_D_Latch

D LatchFeb-9-2014

D latch

Regular D Latch

1 //-----------------------------------------------------2 // Design Name : dlatch_reset3 // File Name : dlatch_reset.v4 // Function : DLATCH async reset5 // Coder : Deepak Kumar Tala6 //-----------------------------------------------------7 module dlatch_reset (

8 data , // Data Input9 en , // LatchInput

10 reset ,// Reset input11 q // Q output12 );

13 //-----------Input Ports---------------14 input data, en, reset ;15

16 //-----------Output Ports---------------17 output q;18

19 //------------Internal Variables--------20 reg q;21

22 //-------------Code Starts Here---------23 always@ ( en or reset or data)24 if (~reset) begin25 q