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Chapter 4

Input Output Systems

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Input / Output Problems Why peripherals are connected

directly to the system bus Wide variety of peripherals Delivering different data formats

At different speeds either slow or fast Need I/O modules and its functions

Interface to processor and Memory Interface to one or more peripherals

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Model of I/O Module

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External Devices Human readable - user

Screen, printer, keyboard Machine readable - equipment

magnetic disk, tape, sensors and actuators

Communication remote places Modem Network Interface Card (NIC)

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Diagram

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I/O Module Functions Control & Timing

CPU Communication Device Communication Data Buffering Error Detection

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Control And Timing To coordinate the flow of traffic between

CPU and devices Steps

CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU

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Processor Communication I/O module has to communicate with

processor also Command decoding Data Status reporting Address recognition

Device communication: Must communicate with device also Commands Status information Data

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Data buffering Buffered in I/O module and then sent to

peripheral devices In opposite direction also same

Error detection

Report errors to the processor. Mechanical and electrical malfunctions

(paper jam, bad disk number) Changes in bit pattern Parity bits

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I/O Module Block Diagram

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I/O Module Decisions Hide device properties to CPU

Support multiple or single device Control device functions or leave for

CPU

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Input Output Techniques Programmed

Interrupt driven Direct Memory Access (DMA)

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P d I/O

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Programmed I/O CPU has direct control over I/O

Sensing status Read/write commands Transferring data

CPU waits for I/O module to completeoperation

Wastes CPU time

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ki

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Working CPU issues command to I/O module

I/O module performs operation I/O module sets status bits CPU checks status bits periodically

I/O module does not inform CPU directly orinterrupt it

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I/O Commands While executing CPU issues

Address of the I/O module External device An I/O command.

Commands Control - activate or telling module what to

do Test - check status

e.g. powered on or not, Error. Read to obtain a data from peripheral Write take data to peripheral

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Addressing I/O Devices Each device given unique identifier CPU commands contain identifier

(address)

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I/O M i

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I/O Mapping Memory mapped I/O

Devices and memory share an address space Treats data and status registers as memory

locations No special commands for I/O

Same instructions for both data and memory

Isolated I/O Separate address spaces Need I/O or memory select lines

Special commands for I/O Limited set

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M M d I/O

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Memory Mapped I/O

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Isolated I/O

2020

I t t D i I/O

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Interrupt Driven I/O Overcomes CPU waiting

No repeated CPU checking of device I/O module interrupts when ready

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Basic Operation CPU issues read command

I/O module gets data from peripheralwhile CPU does other work

I/O module interrupts CPU

CPU requests data I/O module transfers data

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mp e nterrupt rocess ng

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mp e nterrupt rocess ng

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Design Iss es

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Design Issues How the processor identifies that which

module issued the interrupt? How does the processor deals with

multiple interrupts?

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Module Different line for each module

Limits number of devices Software poll

CPU asks each module in turn Slow

Daisy Chain or Hardware poll Interrupt Acknowledge sent down a

chain Requested module responds by placing

a word on data bus containing anidentifier - vector

Vectored interrupt2727

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Bus arbitration Uses vectored interrupt

Module must claim the bus before it can raiseinterrupt

One module can do Processor detects interrupt and

acknowledges, the module places its vector

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M lti l I t t

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Multiple Interrupts Based on priority

Multiple lines Each line has its priority

Software polling Polling determines priority

Daisy chain Order of modules

Bus arbitration only current master can interrupt

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89C59A interrupt controller 80x86 has one interrupt line only

80x86 based systems use 82C59A interruptcontroller

82C59A has 8 interrupt lines

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-82C59A

Accepts interrupts from attached

modules Determines priority Signals processor (raises INTR line) CPU Acknowledges (INTA line) Puts correct vector on data bus CPU processes interrupt

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Interrupt modes

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Interrupt modes Fully nested

Ordered in priority from 0(IR0) to 7(IR7) Rotating

Equal priority, then serviced one afterother

Special mask Take interrupts from certain devices only

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Interface

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82C55A

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Direct Memory Access

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Direct Memory Access Interrupt driven and programmed I/O

require active CPU intervention Transfer rate is limited Number of instructions must be executed for

single I/O transfer

DMA Large volumes of data can be moved easily

DMA controller takes over from CPU for

I/O

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DMA Block Diagram

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DMA Block Diagram

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DMA Operation

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DMA Operation CPU tells DMA controller:-

Read/Write Device address Starting address of memory block for data Amount of data to be transferred

CPU carries on with other work DMA controller deals with transfer

Without going to the processors

DMA controller sends interrupt whenfinished

Processor is involved only at the starting

and at end of transfer 3838

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-Stealing

DMA controller takes over bus for a cycle

Transfer of one word of data and returnscontrol to the processor

Not an interrupt

CPU does not switch context Slows down CPU but not as much as CPU

doing transfer

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DMA and Interrupt Breakpoints

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DMA and Interrupt Breakpointsduring an Instruction Cycle

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DMA Configurations (1)

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DMA Configurations (1)

Single Bus, Detached DMA controller Each transfer uses bus twice

I/O to DMA then DMA to memory

CPU is suspended twice

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DMA Configurations (2)

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DMA Configurations (2)

Single Bus, Integrated DMAcontroller

DMA may support more than onedevice

Each transfer uses bus once DMA to memory

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DMA Configurations (3)

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DMA Configurations (3)

Separate I/O Bus

Each transfer uses bus once DMA to memory

CPU is suspended once

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Intel 8237A DMA Controller

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Intel 8237A DMA Controller Interfaces to 80x86 family and DRAM

DMA module needs buses it sends HOLDsignal to processor Processor responds HLDA then DMA can

use buses Ex. transfer data from memory to disk

Device requests by pulling DREQ (DMArequest) high

DMA puts high on HRQ (hold request), CPU finishes present bus cycle and puts

high on HDLA (hold acknowledge). HOLD remains active for duration of DMA DMA activates DACK (DMA acknowledge),4444

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Systems Bus

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DMA starts transfer DMA deactivates HRQ, giving bus back to

CPU While DMA using buses processor idle

and while Processor using bus, DMA idle

Known as fly-by DMA controller Data does not pass through and is not stored

in DMA chip DMA only between I/O port and memory

Not between two I/O ports or two memorylocations

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I/O Channels - Evolution

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I/O Channels - Evolution CPU directly controls the peripherals

I/O module programmed I/o I/O module interrupt DMA

Processor on its own CPU initiates I/O module with memory

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I/O Channel Architecture

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I/O Channel Architecture

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Byte multiplexor low speed devices Block multiplexor high speed

devices