CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)
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Transcript of CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)
![Page 1: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/1.jpg)
1 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
CPRE 583Reconfigurable ComputingLecture 1: Wed 8/26/2009
(Course Overview, VHDL Overview 1)
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
![Page 2: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/2.jpg)
2 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Class Introduction• Class Survey (by next class, [email protected])
– Background (year in school, VHDL/Verilog, EE/CPRE background, ISU login ID)
– What would you like to get from this class
• Syllabus
• Course Expectations– Reinforce research fundamentals– Asking the right question
• VHDL handbook (source Synplicity)– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)
• VHDL online tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/
![Page 3: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/3.jpg)
3 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
• Basic objectives and topics covered in this class.
• VDHL is NOT a programming language. It is a means to describe hardware.
What you should learn
![Page 4: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/4.jpg)
4 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
• Basic components of an FPGA (Chapter 1)
• Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2)
• Examples of reconfigurable systems (Chapter3)
• Managing the reconfiguration of systems (Chapter 4)
![Page 5: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/5.jpg)
5 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
A
B
X
opcode {+, -, AND, OR}
Behavior VHDL: ALUcompnt ALU (A,B,opcode,X) case opcode when => opPlus X <= A + B; when => opSub X <= A – B; when => opAND X <= A and B; when => opOR X <= A or B; end case;end component;
ALU
Structural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
![Page 6: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/6.jpg)
6 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
A
B
X
opcode {+, -, AND, OR}
A
B
X
addAB
subAB
andAB
orAB
4:1Mux
opcode {+, -, AND, OR}
2Xadd
Xsub
Xand
Xor
ALU
ALUStructural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;
![Page 7: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/7.jpg)
7 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
FPGA
Mem
ory
CPU
![Page 8: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/8.jpg)
8 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
Mem
ory
Function1
Function2
Function4
Function3
![Page 9: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/9.jpg)
9 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
Mem
ory
Function5
Function1
Memory
Function2
Function3
Function4
Memory
Memory
Memory
![Page 10: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/10.jpg)
10 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
• Streaming Applications
• Data Parallel Applications
• Fix/Floating Point Computations
• Performance Trade-offs
• Fault Tolerance
![Page 11: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/11.jpg)
11 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
AB
addABX A
BxorAB
X AB
andABX A
BorAB
X
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0001
0 00 11 0 1 1
A B X0111
2-input Look Up Tables (LUTs)FPGA
LUT LUT LUT LUT
LUT LUT LUT LUT
LUT LUT LUT LUT
LUT LUT LUT LUT
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
X <= A+B; X <= A xor B; X <= A and B; X <= A or B;
![Page 12: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/12.jpg)
12 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
FPGA
LUT addAB LUT LUT
LUT xorABLUT LUT
LUTandAB LUT LUT
LUT orAB LUT LUT
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
AB
addABX A
BxorAB
X AB
andABX A
BorAB
X
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0001
0 00 11 0 1 1
A B X0111
2-input Look Up Tables (LUTs)
X <= A+B; X <= A xor B; X <= A and B; X <= A or B;
![Page 13: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/13.jpg)
13 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about.
Please give suggestions as the semester progresses.
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
![Page 14: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/14.jpg)
14 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
![Page 15: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/15.jpg)
15 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)
ML507Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
![Page 16: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/16.jpg)
16 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
![Page 17: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/17.jpg)
17 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC SerialUART Echo.vhd
![Page 18: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/18.jpg)
18 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC SerialUART
Echo.vhd(Modify to
capitalize only (a-z))
![Page 19: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/19.jpg)
19 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Echo.vhdEthernet(UDP/IP)
![Page 20: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/20.jpg)
20 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PCEcho.vhd
(Modify to count strings (e.g. corn!))
Ethernet(UDP/IP)
![Page 21: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/21.jpg)
21 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Echo.vhdEthernet(UDP/IP)
![Page 22: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/22.jpg)
22 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PCEcho.vhd
(Edge detection)Ethernet(UDP/IP)
![Page 23: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/23.jpg)
23 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
![Page 24: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/24.jpg)
24 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
![Page 25: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/25.jpg)
25 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
![Page 26: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/26.jpg)
26 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
• Choose your own topic
• Groups of 2-3 (maybe 4 for a large enough project)
• Encouraged to take on aggressive projects
![Page 27: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/27.jpg)
27 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Review Syllabus
• Objects
• Expectations
• Grading breakdown
• MP grading policy: (more flexible for Distance Students)– Up to 5% added for early completion (Fri Midnight)– -5% after Fri Midnight– -10% additional after Monday Midnight– -10% additional after Tue Midnight– After Wed Midnight will make a note.
![Page 28: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/28.jpg)
28 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What is Reconfigurable Computing?
• Ask wiki: http://en.wikipedia.org/wiki/Reconfigurable_computing
• Computing on a medium that is not fixed• Examples:
– rDPA (course grain reconfiguration)– FPGA (fine grain reconfiguration)– General Purpose Processor (not really)
underlining hardware typical executes a relatively small fixed instruction set.
![Page 29: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/29.jpg)
29 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
![Page 30: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/30.jpg)
30 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
![Page 31: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/31.jpg)
31 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
![Page 32: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/32.jpg)
32 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
![Page 33: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/33.jpg)
33 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
![Page 34: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/34.jpg)
34 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB
CLB
CLB
CLB CLB CLB CLB
Configurable Logic Block
![Page 35: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/35.jpg)
35 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB CLB
CLB CLB
![Page 36: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/36.jpg)
36 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
![Page 37: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/37.jpg)
37 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
00
01
ANDZA
BCD
![Page 38: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/38.jpg)
38 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
01
11
ORZA
BCD
![Page 39: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/39.jpg)
39 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
X000X001
X110X111
ABCD Z
01
11
2:1Mux
CD
B
Z
![Page 40: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/40.jpg)
40 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
![Page 41: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/41.jpg)
41 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
DFF
PIP Programmable Interconnection Point
![Page 42: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/42.jpg)
42 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
DFF
PIP Programmable Interconnection Point
![Page 43: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/43.jpg)
43 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
FPGA Usage Models
FastPrototyping
PartialReconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
•Experimental ISA
•Experimental Micro Architectures
• Image Processing
• Computational Biology
CPU + Specialized HW - Sparc-V8 Leon
• Remote Update
• Fault Tolerance
• Run-time adaptation• Run-time Customization
![Page 44: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/44.jpg)
44 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Development Platform Overview
• ML507 Evaluation Platform User Guide (pgs. 14-16)– http://www.xilinx.com/support/documentation/boards_and_kits/
ug347.pdf
![Page 45: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/45.jpg)
45 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problem 0 (MP0) Short Overview
• Officially assigned Fri (8/28), Due Friday (9/4). – Note: 1 week
• Purpose: Make sure you can run the tools. Very light VHDL coding.
• Primary Tasks:– Run the echo circuit without modifications– Run the echo circuit with a modification to convert lower
case ASCII characters to upper case.
• Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from:– For Windows: http://www.nomachine.com/download-client-windows.php– For Linux: http://www.nomachine.com/download-client-linux.php– For MAC OS: http://www.nomachine.com/download-client-macosx.php– For Solaris: http://www.nomachine.com/download-client-solaris.php
![Page 46: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/46.jpg)
46 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL basics
• VHDL: (V)HSIC (H)ardware (D)escription (L)anguage– VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
• It is NOT a programming language!!!
• It is a Hardware Description Language (HDL)
• Conceptually VERY different form C,C++
• Some links to VHDL tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)
![Page 47: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/47.jpg)
47 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
• C is inherently sequential (serial), one statement executed at a time
• VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time
![Page 48: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/48.jpg)
48 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 49: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/49.jpg)
49 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 50: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/50.jpg)
50 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 51: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/51.jpg)
51 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 52: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/52.jpg)
52 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
![Page 53: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/53.jpg)
53 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
Snap shot after input change
![Page 54: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/54.jpg)
54 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
![Page 55: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/55.jpg)
55 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Different
![Page 56: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/56.jpg)
56 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Snap shot after input change
![Page 57: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/57.jpg)
57 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
![Page 58: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/58.jpg)
58 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
“Simulates in parallel ever delta time step”
![Page 59: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/59.jpg)
59 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
![Page 60: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/60.jpg)
60 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(1)
X(1)
Ans(1)
![Page 61: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/61.jpg)
61 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(2)
![Page 62: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/62.jpg)
62 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(4)
![Page 63: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/63.jpg)
63 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit (More realistic)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(1)
X(1)
Ans(1)2ns
2ns
2ns
![Page 64: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/64.jpg)
64 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(2)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
![Page 65: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/65.jpg)
65 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(4)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
![Page 66: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/66.jpg)
66 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Typical Structure of a VHDL FileLIBRARY ieee;
ENTITY test_circuit IS PORT(B,C,Y,Z,Ans);END test_circuit;
ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B or C;
END
Include Libraries
Define component name andInput/output ports
Declare internalsignals, components
Implement components functionality
![Page 67: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/67.jpg)
67 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Next Lecture
• Basic components of an FPGA• VHDL overview cont.
![Page 68: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/68.jpg)
68 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Questions/Comments/Concerns
![Page 69: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/69.jpg)
69 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Fast Prototyping Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
![Page 70: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/70.jpg)
70 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Highly Parallel ApplicationsFast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
![Page 71: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/71.jpg)
71 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
System on Chip (SoC) Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
![Page 72: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/72.jpg)
72 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Full Reconfiguration Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
![Page 73: CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1)](https://reader030.fdocuments.in/reader030/viewer/2022032414/5681332e550346895d9a2c97/html5/thumbnails/73.jpg)
73 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Partial Reconfiguration Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)