CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )
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Transcript of CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )
![Page 1: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/1.jpg)
1 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
CPRE 583Reconfigurable Computing
Lecture 2: 8/26/2011(VHDL Overview 1 )
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
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2 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• VHDL review 1– Highly recommend VHDL tutorial
• 120 pages with a LOT of examples• http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf
– Quick reference• http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)
– Some links other VHDL tutorials• http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html• http://www.vhdl-online.de/tutorial/
• HW 1 overview
Overview
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3 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
VHDL basics• VHDL: (V)HSIC (H)ardware (D)escription (L)anguage
– VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
• It is NOT a programming language!!!
• It is a Hardware Description Language (HDL)
• Conceptually VERY different form C,C++
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4 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from C
• C is inherently sequential (serial), one statement executed at a time
• VHDL is inherently concurrent (parallel), many statements executed at a time
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5 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
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6 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
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7 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 8: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/8.jpg)
8 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
![Page 9: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/9.jpg)
9 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
![Page 10: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/10.jpg)
10 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
Snap shot after input change
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11 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
![Page 12: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/12.jpg)
12 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Different
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13 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Snap shot after input change
![Page 14: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/14.jpg)
14 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
![Page 15: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/15.jpg)
15 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
“Simulates in parallel ever delta time step”
![Page 16: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/16.jpg)
16 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Some Key Differences from CC example VHDL example
Ans = A + XA = B + CX = Y + Z
Initially: A,B,C,X,Y,Z,Ans =1
Ans <= A + XA <= B + CX <= Y + Z
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Change order ofstatements
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17 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Corresponding circuitVHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
![Page 18: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/18.jpg)
18 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Corresponding circuitVHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(1)
X(1)
Ans(1)
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19 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Corresponding circuitVHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(2)
X(2)
Ans(2)
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20 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Corresponding circuitVHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(2)
X(2)
Ans(4)
![Page 21: CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )](https://reader035.fdocuments.in/reader035/viewer/2022070420/56815e08550346895dcc6118/html5/thumbnails/21.jpg)
21 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Corresponding circuit (More realistic)VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(1)
X(1)
Ans(1)2ns
2ns
2ns
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22 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(2)
X(2)
Ans(2)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
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23 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)C(1)
Y(1)Z(1)
+A(2)
X(2)
Ans(4)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
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24 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Typical Structure of a VHDL FileLIBRARY ieee;
ENTITY test_circuit IS PORT(B,C,Y,Z,Ans);END test_circuit;
ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B + C; X <= Y + Z; Ans <= A + X;
END
Include Libraries
Define component name andInput/output ports
Declare internalsignals, components
Implement components functionality
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25 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Process• Process provide a level serialization in VHDL (e.g.
variables, clocked processes)
• Help separate and add structure to VHDL design
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26 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Process ExampleBEGIN
My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1;
My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2;
END;
Sensitivity list: specify inputs to theprocess. Process is updated when a specified input changes
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27 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Process Example (Multiple Drivers)BEGIN
My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1;
My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2;
END;
A signal can only be Driven (written) by one process. But can be readby many
Compile or simulator may give a “multiple driver” Erroror Warning message
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28 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Process Example (Multiple Drivers)BEGIN
My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1;
My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2;
END;
Maybe A,X were suppose to be A1,X1. Cutand paste error. Or may need to rethink Hardware structure to remove multiple driverissue.
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29 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Process Example (if-statement)BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin
if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if;
End My_process_1;END;
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30 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Clock Process ExampleBEGIN
My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;
END;
or
or
A()B()
X()Y()
and
C()
Z()
Ans()
circuit not clocked
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31 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Clock Process ExampleBEGIN
My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;
END;
or
or
A()B()
X()Y()
and
C()
Z()
Ans()
circuit with clock
clk
D Flip-FlopDFF
Register
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32 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Clock Process ExampleBEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;END;
or
or
A()B()
X()
Y()
and
C()
Z()
Ans()
circuit with clock
clk
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33 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Clock Process Example 2BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1;END;
xor
or
A()B()
X()
Y()
xor
C()
Z()
Ans()
circuit with clock
clk
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34 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Clock Process Example 2 (Answer)BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1;END;
xor
or
A()B()
X()
Y()
xor
C()
Z()
Ans()
circuit with clock
clk
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35 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
VHDL Constructs
• Entity• Process• Signal, Variable, Constants, Integers• Array, Record
VHDL on-line tutorials:http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.vhdl-online.de/tutorial/
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36 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Signals and Variables• Signals
– Updated at the end of a process– Have file scope
• Variables– Updated instantaneously– Have process scope
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37 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
std_logic, std_logic_vector• Very common data types
• std_logic– Single bit value– Values: U, X, 0, 1, Z, W, H, L, -– Example: signal A : std_logic;
• A <= ‘1’;• Std_logic_vector: is an array of std_logic
– Example: signal A : std_logic_vector (4 downto 0);• A <= x“00Z001”
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38 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Std_logic values• Std_logic values
– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 0
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39 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 0
1 U U U
Std_logic values
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40 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 1
0 1 U U
Std_logic values
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41 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 2
1 0 1 U
Std_logic values
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42 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 3
1 1 0 1
Std_logic values
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43 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 3
1 1 0 1
0 1
X
Std_logic values
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44 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 3
1 1 0 1
0 1
X
1
0
Std_logic values
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45 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 3
1 1 1 X
0 0
X
1
X
Std_logic values
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46 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 0
‘1’ Pull-up resistor
Std_logic values
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47 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 0
0 U H U
‘1’ Pull-up resistor
Std_logic values
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48 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 1
1 0 H 1
‘1’ Pull-up resistor
Std_logic values
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49 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)
• I have never used this value– L : weak ‘0’
Time step 2
0 1 0 1
‘1’ Pull-up resistor
Resolution(H,0) = 0
Std_logic values
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50 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• mysignal’event (mysignal changed value)• mysignal’high (highest value of mysignal’s type)• mysignal’low• Many other attributes
– http://www.cs.umbc.edu/help/VHDL/summary.html
Pre-defined VHDL attributes
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51 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Signal: global to file• Variable: local to process
Singal vs Varible scope
My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1;
My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;
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52 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
• Signal: global to file• Variable: local to process
Singal vs Varible scope
My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1;
My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2;
Each varZ are local to their process. Completely independent
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53 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Arrays and Records• Arrays: Group signals of the same type together
• Records: Group signal of different types together
VHDL on-line tutorials:http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.vhdl-online.de/tutorial/
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54 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Array Example (Delay Shift Register)flag_in flag_1 flag_2 flag_3 flag_out
BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3END;
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55 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Array Example (Delay Shift Register)flag_in flag_1 flag_20 flag_out
BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1;
flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20END;
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56 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Array Example (Delay Shift Register)flag_in flag_1 flag_20 flag_out
BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high);END;
type flag_reg_array is array (DELAY-1 downto 0) of std_logic;signal flag_reg : flag_reg_array;
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57 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Array Example (Delay Shift Register)
flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in;
flag_in flag(0) flag(1) flag(2) flag_out
0 0 11
flag_in flag(0) flag(1) flag(2) flag_out
1 0 0
flag_in flag(0) flag(1) flag(2) flag_out
0 0 11
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58 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Detailed in class design next Friday
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59 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
HW1
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60 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)
Questions/Comments/Concerns