Corrected Sequence Detector
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Transcript of Corrected Sequence Detector
7/23/2019 Corrected Sequence Detector
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Ex No: DESIGN OF SEQUENCE DETECTOR
Date:
AIM:
Designing, synthesising and implementing a sequence detector for the given sequence
using verilog and VHDL.
The given sequence is “11010.
HARDWARE REQUIRED:
!partan "#.
SOFTWARE REQUIRED:
$ilin% 1".1 &!#.
ALGORITHM:
!tep 1' !tart the program.
!tep (' Declare the input, cl), reset.
!tep "' Declare the output as y.
!tep *' Dra+ the state diagram +hose initial state is reset.
!tep ' &f the input matches +ith a given sequence the present state transits to the ne%t state.
!tep -' &f the input does not match +ith a given sequence the state +ill e in present state or
move to the reset state as per the condition given.
!tep /' The output is al+ays remains “0 until the +hole sequence is received.
!tep ' hen the sequence is fully received the output changes from “0 to “1.
THEORY:
2 sequence detector is the one +hich detects the ne%t state +hen the reset value is
given. The transition ta)es place from the present state to the ne%t state +hen the value is
given or else the present state +ill e the same state. &t can e descried using state diagrams.
#ach state is used to represent the present state or the ne%t state. The five it sequence 11010
can e detected using this state diagram if reset is given then it goes to the ne%t state s1and
attains the value 1or else it stays in the same state s0.
STATE DIAGRAM:
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STATE TABLE:
PRESENT
STATE
NEXT STATE OUTPUT (Y)
X! X" X! X"
S! S! S" ! !
S" S! S# ! !
S# S$ S# ! !
S$ S! S% ! !
S% S& S! " !
S& S! S" ! !
PROGRAM:
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a)'e*o+ ,o-e.
module me13%,cl),rst,y45
input %,cl),rst5
output y5
reg6('07state5
reg y5
al+ays 8 3posedge cl)4
egin
if3rst9914egin
state:9";0005
y:905
end
else egin
case 3state4
";000'egin
if 3%4 egin
state:9";0015
y:905
end
else egin
state:9";0005
y:905
end
end
";001'egin
if 3%4 egin
state:9";0105
y:905
end
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else egin
state:9";0005
y:905
end
end
";010'egin
if 3%4 egin
state:9";0105
y:905
end
else egin
state:9";0115
y:905
end
end
";011'egin
if 3%4 egin
state:9";1005
y:905
end
else egin
state:9";0005
y:905
end
end
";100'egin
if 3%4 egin
state:9";0005
y:905
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end
else egin
state:9";1015
y:915
end
end
";101'egin
if 3%4 egin
state:9";0015
y:905
end
else egin
state:9";0005
y:905
end
end
endcase
end
end
endmodule
/) 'HDL ,o-e:.
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Lirary &###5
<se &###.!TD=L>?&@=11-*.2LL5
<se &###.!TD=L>?&@=unsigned.2LL5
#ntity fsm is
Aort 3 %,cl),reset ' in !TD=L>?&@5 B ' out !TD=L>?&@45
end fsm5
2rchitecture Cehavioral of fsm is
type state=type is 3s0,s1,s(,s",s*,s45
signal state,ne%tstate' state=type5
signal count' std=logic=vector3( do+nto 045
egin
ump=process'process3state,%4
egin
case state is
+hen s09E
if %9;1; then ne%tstate:9s15B:9;0;5
else ne%tstate:9s05B:9;0;5 end if5
+hen s19E
if %9;1; then ne%tstate:9s(5B:9;0;5
else ne%tstate:9s05B:9;0;5 end if5
+hen s(9E
if %9;1; then ne%tstate:9s(5B:9;0;5
else ne%tstate:9s"5B:9;0;5end if5
+hen s"9E
if %9;1; then ne%tstate:9s*5B:9;0;5
else ne%tstate:9s05B:9;0;5end if5
+hen s*9E
if %9;1; then ne%tstate:9s(5B:9;0;5
else ne%tstate:9s5 B:9;1;5end if5
+hen s9E
if %9;1; then ne%tstate:9s15B:9;0;5
else ne%tstate:9s05 B:9;0;5end if5end case5
end process5
seq=process 'process3cl),reset4
egin
if reset9;1;
then state:9s05
elseif3rising=edge3cl)44 then
state:9ne%tstate5
end if5
end if5
end process5end Cehavioral5
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TEST BENCH FOR 'HDL PROGRAM:
L&CF2FG ieee5
<!# ieee.std=logic=11-*.2LL5
#T&TG try &!
#D try5
2F@H&T#@T<F# ehavior >I try &!
JJ @omponent Declaration for the <nit <nder Test 3<<T4
@>KA>#T fsm
A>FT3
% ' & std=logic5
cl) ' & std=logic5
reset ' & std=logic5 B ' ><T std=logic
45
#D @>KA>#T5
JJ&nputs
signal % ' std=logic '9 ;0;5
signal cl) ' std=logic '9 ;0;5
signal reset ' std=logic '9 ;0;5
JJ>utputs
signal B ' std=logic5
JJ @loc) period definitions
constant cl)=period ' time '9 10 ns5
C#?&
JJ &nstantiate the <nit <nder Test 3<<T4
uut' fsm A>FT K2A 3
% 9E %,
cl) 9E cl),
reset 9E reset,
B 9E B 45
JJ @loc) process definitions
cl)=process 'process
egin
cl) :9 ;0;5
+ait for cl)=period(5
cl) :9 ;1;5
+ait for cl)=period(5
end process5
reset :9 ;1;, ;0; after 10 ns5
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% :9 ;0;, ;1; after (0 ns, ;0; after *0 ns, ;1; after 0 ns,;0; after -0 ns5
JJ !timulus process
JJstim=proc' process
JJegin
JJ hold reset state for 100 ns.
JJ +ait for 100 ns5 JJ +ait for cl)=periodM105
JJ insert stimulus here
JJ +ait5
JJend process5
#D5
UCF FILE:
N Alan 2head ?enerated physical constraints
#T Ocl)O L>@ 9 A1/5 #T OresetO L>@ 9 A10-5
#T O%O L>@ 9 A10/5
DE'ICE UTILI0ATION SUMMARY:
!elected Device' "s(0epq(0J*
umer of !lices ' " out of (** 0P
umer of !lice Ilip Ilops ' " out of *Q- 0P
umer of * input L<Ts ' out of *Q- 0P
umer of &>s ' *
umer of onded &>Cs ' * out of 1 (P
umer of ?@LRs ' 1 out of (* *P
TIMING SUMMARY:
S1ee- Ga-e: .%
Kinimum period' (.((ns 3Ka%imum Irequency' **Q.*"KHB4
Kinimum input arrival time efore cloc)' (.QQ(ns
Ka%imum output required time after cloc)' ./*Qns
Ka%imum cominational path delay' -.(0ns
OUTPUT WA'EFORM:
'e*o+:
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'HDL:
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RESULT:
Thus a sequence detector for the sequence “11010 is detected, simulated andimplemented using verilog and VHDL.