MultipleChoiceQuestions#115thApril2008

SystemValidationIL2450

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1.Whichoneisthecorrectsimulationoutputforthegivenmodule.

moduleBvsNB();beginintq1,q2,q3,q4;intj1,j2,j3,j4;

inti;bitclk;initialbegin

i=5;q1=1;

q2=2;q3=3;q4=4;

j1=1;j2=2;j3=3;j4=4;

#10$stop;endalways #2clk=!clk;always@(posedgeclk)begin

q1=i;q2=q1;q3=q2;q4=q3;

endalways@(posedgeclk)begin

j1

2.Whatisthedifferencebetweenasignaloftypebitandasignaloftypelogic?

1. Bitisatwovalueddatatype,Logicisafourvalueddatatype2. Bitisafourvalueddatatype,Logicisatwovalueddatatype3. Bitisaninevalueddatatype,Logicisatwovalueddatatype4. Bitisaninevalueddatatype,Logicisafourvalueddatatype

3.Isitpossibletochangeanalwaysstatementwithanalways_ffstatement,withoutchangingthebehavioroftheprocessnorthesensitivitylist?

1. Yes,always2. No,never3. Itdependsonthesensitivitylistoftheblock4. Alwaysisaverilogconstruct,itisillegalin

SystemVeriloganditwillnotcompile.

4.Whatisthevalueofprod[3]afterfollowingcodesimulates??

reg[1:0][3:0]prod[3:0];inty,z;initialbegin

z='o377;//octalvaluefor(y=0;y

5.whatisthevalueofc0c1c2,c3c4?

enum{c0,c1=7,c2,c3=10,c4}color;

1. c0=0c1=7c2=8c3=10c4=112. c0=0c1=7c2=2c3=10c4=43. c0=Uc1=7c2=Uc3=10c4=U4. Noneoftheabove

whereUisunassignedvalues(justlike1,0,U,Z,X)

6.Whichofthefollowingconstructswouldyouuseifyouwantedtoavoidusingtheconstructalwayswithoutchangingthefunctionalityofthefollowingprocess?

always@(aorb)beginsum=b+a;end

1. always_comb2. always_latch3. always_ff4. noneoftheabove

7. Whatisthedifferencebetween=and

8.whatisthecorrectoutputforthismodule

moduledelays();inti,j,k=0;initialbegin

#10i=10;//after10nschangevalueofito10#12i

9.WhatisthecorrectdescriptionfortheA!?=Boperation

1. IsAnotequaltoB?Where(1bitTrue/Falseresult)IdentityOperatorcompareslogicvaluesof0,1,XandZ.

2. IsAnotequaltoB?Where(1bitTrue/Falseresult)EqualityOperatorscompareslogicvaluesof0and1.

3. AnotequalsB,whereXandZvaluesarewildcards(WildEqualityOperators)4. Noneoftheabove

10.Whatisthecorrectoutputforthefollowingcode

initialbeginclk=0;#5;fork#5a=0;#10b=0;join_anyclk=1;end

Output1clkbecomes1whentime=5

Output2clkbecomes1whentime=10

output3clkbecomes1whentime=15

output4clkbecomes1whentime=20

11.Whichofthefollowingoperationcannotbeperformedonunpackedarrays.

1. Readingandwritingasliceofthearray A[i:j]=B[i:j]

2. Readingandwritingavariablesliceofthearray A[x+:c]=B[y+:c]

3. AssignmentfromanintegerA=8b11111111;

4. Thestatementisincorrectandalltheoperationscanbeperformedonunpackedarrays.

12.WhichofthefollowingisnotTRUE

1. Initialstatement/blockisalwaysexecutedonceatthestartofsimulation2. Iftherearemultipleinitialstatement/blockinacodesegment,thenallof

themareexecutedatthestartofsimulation3. Initialstatementshouldhavesensitivitylistassociatedwithit.

13.Atwhichtimewilltherebearisingedgeofthesignalainthefollowingmodule?

modulelogicclk=0;logica=0;

initialbegin#40clk=1;#60clk=0;endend

always@(posedgeclk)begin#10;@(negedgeclk)#10a=1;end

1. t = 1102. t = 703. t = 1004. t = 1205. t = 80

14.A23bitpackedregtypedatawith4x3cellsofunpackeddatacannotbedeclaredas

1. reg[22:0]data[3:0][2:0];2. reg[22:0]data[4][3];3. reg[23]data[4][3];4. Alloftheabovearecorrectwaysofdeclaring.

15.WhichofthefollowingstatementisnotTRUE

1. SystemVerilogallowsfunctionstobedeclaredastypevoid2. Fornonvoidfunctions,avaluecanbereturnedbyassigningthefunctionnametoavalue3. Whenthereturnstatementisused,nonvoidfunctionsmustspecifyanexpressionwiththereturn.4. InSystemVerilog,afunctionreturncannotbeastructureorunion

16.WhichofthefollowingstatementTRUEforfollowingcodesegement.always_ff@(posedgeclkornegedgerst_n//activelowresetornegedgeset_n//activelowset)if(!rst_n)//resethaspriorityoversetq_out

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Pleasetickmarkthecorrectoptionbox.Pleaseleaveotherblack.Answerswithmultipleticmarkswillbeconsideredfalse.

Option1 Option2 Option3 Option4

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1.Which one is the correct simulation output for the given module.Output 1 Output 2 Output 3Output 4

2.What is the difference between a signal of type bit and a signal of type logic?3.Is it possible to change an always statement with an always_ff statement, without changing the behavior of the process nor the sensitivity list?4.What is the value of prod[3] after following code simulates??5.what is the value of c0 c1 c2,c3 c4?6.Which of the following constructs would you use if you wanted to avoid using the construct always without changing the functionality of the following process?7.What is the difference between = and