Computer Architecture - SAFARI Research Group...1 10 100 1000 10000 100000 1000000 8 56 104 152 200...
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Computer Architecture Lecture 6b: SoftMC Hasan Ibrahim Hasan ETH Zürich Fall 2018 4 October 2018
Transcript of Computer Architecture - SAFARI Research Group...1 10 100 1000 10000 100000 1000000 8 56 104 152 200...
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Computer Architecture
Lecture 6b: SoftMC
Hasan Ibrahim Hasan
ETH Zürich
Fall 2018
4 October 2018
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SoftMCA Flexible and Practical
Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan,
Nandita Vijaykumar, Samira Khan,
Saugata Ghose, Kevin Chang,
Gennady Pekhimenko, Donghyuk Lee,
Oguz Ergin, Onur Mutlu
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Executive Summary• Two critical problems of DRAM: Reliability and Performance
• Characterize, analyze, and understand DRAM cell behavior
• We design and implement SoftMC, an FPGA-based DRAM testing infrastructure
‒ Flexible and Easy to Use (C++ API)
‒ Open-source (github.com/CMU-SAFARI/SoftMC)
• We implement two use cases
‒ A retention time distribution test
‒ An experiment to validate two latency reduction mechanisms
• SoftMC enables a wide range of studies
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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DRAM Operations
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CPU
Memory Controller
DRAM Row
Sense Amplifier
ActivateReadPrecharge
Memory Bus
DRAM Cell
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DRAM Latency
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Activate
time
Read Precharge
Activation Latency
Ready-to-access Latency Precharge
Latency
Activate
0 (refresh) 64 msDRAM
Cell
Sense Amplifier
Retention Time: The interval during which the data
is retained correctly in the DRAM cell without accessing it
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Latency vs. Reliability
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Activate
time
Read Precharge
Activation Latency
Ready-to-access Latency Precharge
Latency
Activate
DRAMCell
Sense Amplifier
Violating latencies negatively affects DRAM reliability
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Other Factors Affecting Reliability and Latency
• Temperature
• Voltage
• Inter-cell Interference
• Manufacturing Process
• Retention Time
• …
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To develop new mechanisms improving reliability and latency,
we need to better understand the effects of these factors
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Characterizing DRAM
Many of the factors
affecting DRAM reliability and latency
cannot be properly modeled
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We need to perform experimental studies
of real DRAM chips
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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Goals of a DRAM Testing Infrastructure
• Flexibility‒ Ability to test any DRAM operation
‒ Ability to test any combination of DRAM operations and custom timing parameters
• Ease of use‒ Simple programming interface (C++)
‒ Minimal programming effort and time
‒ Accessible to a wide range of users
• who may lack experience in hardware design11
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SoftMC: High-level View
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FPGA-based memory characterization infrastructure
Prototype using Xilinx ML605
Easily programmable using
the C++ API
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SoftMC: Key Components
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1. SoftMC API
2. PCIe Driver
3. SoftMC Hardware
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SoftMC API
InstructionSequence iseq;
iseq.insert(genACT(bank, row));
iseq.insert(genWAIT(tRCD));
iseq.insert(genWR(bank, col, data));
iseq.insert(genWAIT(tCL + tBL + tWR));
iseq.insert(genPRE(bank));
iseq.insert(genWAIT(tRP));
iseq.insert(genEND());
iseq.execute(fpga);
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Writing data to DRAM:
Instruction generator functions
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SoftMC: Key Components
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1. SoftMC API
2. PCIe Driver*
3. SoftMC Hardware
Communicates raw data with the FPGA
* Jacobsen, Matthew, et al. "RIFFA 2.1: A reusable integration framework for FPGA accelerators." TRETS, 2015
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SoftMC Hardware
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PC
IeC
on
tro
ller
Instruction ReceiverInstruction
Queue
Inst
ruct
ion
D
isp
atch
er
DDR PHY
Auto-refresh
Controller
Calibration Controller
Read Capture
SoftMC Hardware (FPGA)
Instructions
ActivateReadWait (Ready-to-access Latency)
Data
Host Machine
DRAM
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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Retention Time Distribution Study
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Increase the refresh interval
Observe Errors
Read Back
Wait (Refresh Interval)
Write Reference Data to a Row
Can be implemented with just ~100 lines of code
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Retention Time Test: Results
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Refresh Interval (s)
@ ~20⁰C (room temperature)
Module A
Module B
Module C
Validates the correctness of the SoftMC Infrastructure
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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Accessing Highly-charged Cells Faster
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NUAT(Shin+, HPCA 2014)
ChargeCache(Hassan+, HPCA 2016)
A highly-charged cell can be accessed with low latency
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How a Highly-Charged Cell Is Accessed Faster?
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Activate
DRAMCell
Sense Amplifier
time
Read Precharge
Activation Latency
Ready-to-access Latency Precharge
Latency
Activate
0 (refresh) 64 ms
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Ready-to-access Latency Test
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Change the Wait Interval
Observe Errors
Read Back
Wait for theWait Interval
Write Reference
Data
Longer wait
Shorter wait Higher cell charge
Lower cell charge
With custom ready-to-access latency parameter
Can be implemented with just ~150 lines of code
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Ready-to-access Latency: Results
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Wait Interval (ms)
6 5 4 3
Latency (cycles)
@ 80⁰C temperature
Real Curves
We do not observe the expected
latency reduction effect in existing DRAM chipsN
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yte
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Refresh Interval
6 5 4 3
Latency (cycles)
Expected Curves
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Why Don’t We See the Latency Reduction Effect?
• The memory controller cannot externally control when a sense amplifier gets enabled in existing DRAM chips
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Data 0
Data 1
Cell
time
cha
rge
Sense Amp
R/WACT
Ready to AccessCharge Level
Ready to Access
Fixed Latency!
Enabling the Sense Amplifier
Potential Reduction
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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Future Research Directions
• More Characterization of DRAM
‒ How are the cell characteristics changing with different generations of technology nodes?
‒ What types of usage accelerate aging?
• Characterization of Non-volatile Memory
• Extensions
‒ Memory Scheduling
‒ Workload Analysis
‒ Testbed for in-memory Computation27
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Outline
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1. DRAM Basics & Motivation
2. SoftMC
3. Use Cases
– Retention Time Distribution Study
– Evaluating Recently-Proposed Ideas
4. Future Research Directions
5. Conclusion
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Conclusion• SoftMC: First publicly-available FPGA-based DRAM
testing infrastructure
• Flexible and Easy to Use
• Implemented two use cases
‒ Retention Time Distribution Study
‒ Evaluation of two recently-proposed latency reduction mechanisms
• SoftMC can enable many other studies, ideas, and methodologies in the design of future memory systems
• Download our prototype
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github.com/CMU-SAFARI/SoftMC
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SoftMCA Flexible and Practical
Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan,
Nandita Vijaykumar, Samira Khan,
Saugata Ghose, Kevin Chang,
Gennady Pekhimenko, Donghyuk Lee,
Oguz Ergin, Onur Mutlu
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Backup Slides
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Key SoftMC Instructions
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SoftMC @ Github
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Ready-to-Access Latency Test Results
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Activation Latency Test
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Observe Errors
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Wait for theWait Interval
Read Back
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