© 2012 IEEE

Proceedings of the 27th Applied Power Electronics Conference and Exposition (APEC 2012), Orlando Florida, USA,February 5-9, 2012

Comparative Evaluation of Soft-Switching, Bidirectional, Isolated AC/DC Converter Topologies

J. Everts,F. Krismer,J. Van den Keybus,J. Driesen,J. W. Kolar

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Comparative Evaluation of Soft-Switching,Bidirectional, Isolated AC/DC Converter Topologies

Jordi Everts∗‡, Florian Krismer ‡, Jeroen Van den Keybus†, Johan Driesen∗, and Johann W. Kolar‡

∗Dept. of Electrical Engineering ESAT-ELECTAKatholieke Universiteit Leuven, Belgium

Email: jordi.everts@esat.kuleuven.be‡Power Electronic Systems (PES) Laboratory

ETH Zurich, Switzerland†TRIPHASE

Leuven, Belgium

Abstract—For realizing bidirectional and isolated AC/DCconverters, soft-switching techniques/topologies seem to be afavourable choice as they enable a further loss and volumereduction of the system. Contrary to the traditional dual-stageapproach, using a power factor corrector (PFC) stage in serieswith a DC/DC isolation stage, we showed recently that the samefunctionality can be achieved under full soft-switching operationusing a single-stage dual active bridge (DAB) AC/DC converter.This paper investigates the performance of this single-stageapproach by comparing it with a state-of-the-art conventionaldual-stage concept (both soft-switching converters), where abidirectional interleaved triangular current mode (TCM) PFCrectifier was chosen in combination with a DAB DC/DC converter.The advantages and drawbacks of each concept are discussed indetail, focusing on the impact of the utilized semiconductor tech-nology and silicon area on the converter efficiency. Furthermore,a comprehensive comparison of power density is allowed by theanalytical models that correlate the component losses with theirrespective volume.

Index Terms—AC/DC converter, bidirectional, Dual ActiveBridge, DAB, isolated, soft-switching

I. INTRODUCTION

Isolated AC/DC converters are frequently employed in util-ity interfaced systems such as power supplies in telecommu-nication and data centers [1], [2], plug-in hybrid electricalvehicles (PHEVs) and battery electric vehicles (BEVs) [3],[4]. For these types of grid interfaced systems there is anincreasing need for bidirectional functionality since the tra-ditional electricity grid is evolving from a rather passive to asmart interactive service network (customers/operators) wherethe traditional central control philosophy is shifting to a moredistributed control paradigm. Energy systems become activeelements, providing different types of support to the grid [4],[5]. In all mentioned applications a storage element connectedto the high-voltage (HV) DC-bus can facilitate this need forpower feed-in into the grid [2], [4].

Recently we showed that bidirectional and isolated AC/DCconverters can be realized under full soft-switching operation

This research is partly funded by a Ph.D. grant of the Institute for thePromotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). Jordi Everts is a doctoral research assistant of IWT-Vlaanderen.Jordi Everts is also a visiting doctoral researcher at the Power Electronic Sys-tems Laboratory, ETH Zurich, Switzerland (scholarship of FWO-Vlaanderen).

using a single-stage dual active bridge (DAB) topology (Fig.1(a)) [6], allowing a possible enhancement of the performance(in terms of efficiency, volume, number of components andcost) compared to the traditional dual-stage topologies. In [6]a half bridge - full bridge DAB (Fig. 2(a)) was used. A similaranalysis using a full bridge - full bridge DAB (Fig. 2(b))was performed in [7], providing higher low load efficiency.In order to investigate the performance of both single-stageapproaches, a comprehensive comparison with a state-of-the-art conventional dual-stage topology (PFC for rectification andpower factor correction in series with a DC/DC converterfor galvanic isolation and output voltage regulation) is pre-sented in this paper. For the latter, an interleaved triangularcurrent mode (TCM) PFC rectifier [8] in combination withan isolated full bridge - full bridge DAB DC-DC converter[9], [10], is selected (Figs. 1(b) and 2(b)), both bidirectional,soft-switching, and proven to have an excellent performance(in terms of efficiency and power density). Soft-switchingtechniques/topologies are preferred in every conversion stageas they enable further reduction of the losses and the volumeof the system [11]. A direct comparison of the three converterconcepts based on published data is not feasible due to dif-ferent system specifications and technology standards. Perfor-mance indices of a power electronics converter (e.g. efficiencyand power density) are competing and moreover stronglydependent on the underlying specifications and technologynode. Therefore this paper focusses on a comparison whichis based on common specifications, technology standards anddetailed analytical loss and volume models. Converter modelswith the corresponding dimensioning criteria of the compo-nents are presented in Section II. Analytical loss and volumemodels of the main converter components are comprehensivelydiscussed in Section III, allowing for a complete comparison ofconverter efficiency and power density in Section IV. SectionIV also includes a Semiconductor chip Area based ConverterComparison (SAC2) [12], enabling for optimal selection ofthe semiconductors with respect to the topology and theoperating point, and providing a common Figure of Merit(FOM) for comparison: the required total semiconductor area.

978-1-4577-1216-6/12/$26.00 ©2012 IEEE 1067

C2,st

C2

C2

IDC2i2(t) iDC2(t)

C1

C1

Synchronousrectifier

AC-side HFcapacitors

DC-side HF and LFcapacitors

vAC(t)

iAC(t)

vAC(t) vDC1(t) VDC2

iDC1(t) i1(t)

t t t

20 ms 20 ms

vDC1(t) VDC2

Sec. sidePrim. side

BidirectionalDAB DC/DC

converter

SSRSSR

SSR SSR X'

Z

X Y

Y'

(a) Single-stage DAB AC/DC converter.

C2

C2

IDC2i2(t)

C1,st

TCM interleaved PFC rectifierAC-side LF and HF

capacitorsDC-side HF

capacitors

vAC(t) VDC2

iDC1(t) i1(t)

t t

20 ms

VDC1

VDC2

Sec. sidePrim. side

S11 S21

S12S22

S31

S32

SN1

SN2

vAC(t)

iAC(t) BidirectionalDAB DC/DC

converter

VDC1=VDC2

t

C1

C1

L1

L3

L2

iL1(t)iL2(t)

iL3(t)

X'

X Y

Y'

(b) Dual-stage AC/DC converter

Fig. 1. Schematics of the analyzed converter topologies.

II. ANALYTICAL MODELING AND CONTROL OF THEAC/DC CONVERTER CONCEPTS

The dimensioning criteria for each of the components in thefollowing analysis are derived using common system specifi-cations (Table I), covering the above mentioned applicationareas. A switching frequency of fs = 120 kHz is assumedfor all three topologies (i.e. the average frequency at nominalpower for the variable frequency TCM PFC), being a trade-off between frequency related losses and volume. The threesystems analyzed in this paper are controlled and designed inorder to achieve unity power factor at the AC-side,

iAC(t) = IAC sin(ωt) (1)vAC(t) = VAC sin(ωt) (2)

while satisfying the soft-switching constraints in the wholeoperating range. The soft-switching principle of the converterconcepts is based on a quasi-resonant ZVS switching. Thereby,each high-frequency switch Sxx consists of a power transistorTxx, a diode Dxx, and a parasitic nonlinear capacitor Cxx.Soft-switching operation occurs when a voltage transition isinitiated by turn-off of the respective switch Sxx, commutatingthe current from the transistor Txx to the opposite diodeDxx of the leg [11] (e.g. commutation from Tp1 to Dp2, inFig. 2(b), and turn-on of Tp2 under ZVS (anti-parallel diodeis conducting) after completion of the momentaneous resonanttransition (quasi-resonant ZVS)). A faster commutation can befacilitated by setting a minimum to the switch turn-off current(Icomm,ref = 2 A is used), avoiding voltage transition delayand shoot through. It was shown in [10] that for the highvoltage MOSFET transistors that are under consideration inthis paper (Table III), low currents (0 A 6 Icomm 6 2 A) areinsufficient to recharge the parasitic drain to source capacitorswithin a 200 ns dead-time interval, leading to increasedswitching losses. Whenever in the following considerationsthe semiconductor (active) chip area ASi,act is scaled, also ascaled minimum commutation current is used in all convertermodels:

Icomm = Icomm,ref√ASi,act/ASi,act,ref (3)

TABLE ICONVERTER OPERATING RANGE

Property Value

AC-sideVAC,rms

230V (nominal)207V 6 VAC,rms 6 253V

IAC,rms,nom 16 Afgrid 50 Hz

DC-side VDC2400V (nominal)

360V 6 VDC2 6 440V

The commutation charge, and therefore also Icomm (3), scaleswith the square of the chip area ASi,act as the current crossing istriangular shaped. Distinction is made between the total Si areaASi (thermal models) and the active chip area ASi,act (electricalmodels) of the semiconductor devices:

ASi,act = 0.9864 ·ASi − 1.3662 (mm2) (4)

Relation (4) is derived from manufacter data of the consideredsemiconductor devices.

A. Single-Stage DAB AC/DC Converter Using a Half Bridge- Full Bridge DAB (SSHF converter)

Fig. 1(a) shows the general schematic of the single-stageDAB AC/DC topology, where a DAB DC/DC converter isused in combination with a synchronous rectifier, putting asmall high-frequency (HF) filter capacitor C1 in between. Herea half bridge - full bridge DAB DC/DC converter (Fig.2(a))is used and the topology is further referred to as the SSHF(Single-Stage, Half bridge - Full bridge). The DAB receivesthe rectified AC line voltage vDC1(t) via the synchronousrectifier. It comprises HF transformer coupled primary sideand secondary side active bridges, performing the DC voltage(VDC2) regulation at the output, while maintaining unity powerfactor at the AC side by actively wave-shaping the line currentiDC1(t). The control strategy presented in [6] for the SSHFenables soft-switching operation over the whole voltage andpower range.

1068

n1:n2

v1(t) v2(t)

L iL(t)

v'2(t)

i2(t)

Sp1 Ss1 Ss3

Ss2 Ss4Sp2

Inductor and HFisolation transformer

Half active bridge Full active bridge

VDC2i1(t)vDC1(t)

X'

X Y

Y'

Z

(a) Half bridge - full bridge DAB DC/DC converter

n1:n2

v1(t) v2(t)

L iL(t)

v'2(t)

i2(t)

Ss1 Ss3

Ss2 Ss4

Inductor and HFisolation transformer

Full active bridge

VDC2i1(t) vDC1(t)

Sp1 Sp3

Sp2 Sp4

Full active bridge

X'

X Y

Y'

(b) Full bridge - full bridge DAB DC/DC converter

Fig. 2. Schematics of the bidirectional isolated DAB DC/DC converters usedin the three analyzed converter concepts.

B. Single-Stage DAB AC/DC Converter Using a Full Bridge- Full Bridge DAB (SSFF converter)

In a second implementation of the single-stage DAB AC/DCtopology, the half bridge - full bridge DAB DC/DC converterof the SSHF is replaced by a full bridge - full bridge DABDC/DC converter (Fig. 2(b)). This topology is further referredto as the SSFF (Single-Stage, Full bridge - Full bridge). Thecontrol strategy to operate the SSFF is similar to the one forthe SSHF and is presented in [7]. However, by using two fullbridges, a higher flexibility in shaping the inductor currentiL(t) is achieved, resulting in lower partial load componentRMS currents (partial load efficiency), at the expense of ahigher number of active devices (volume, reliability, cost).

C. Dual-Stage AC/DC Converter Using an Interleaved TCMPFC in Series with a DAB DC/DC Converter (DS converter)

The dual-stage AC/DC converter in Fig. 1(b), and furtherreferred to as the DS (Dual Stage) converter, uses an inter-leaved triangular current mode (TCM) PFC in series with aDAB full bridge - full bridge DC/DC converter (Fig. 2(b)).The TCM PFC [8] consists of several interleaved boost stagesoperating with variable switching frequency. The high TCMinductor current ripple is not transferred to the mains as thesuperposition of all boost cell input currents results in a smoothmains current waveform. It was shown in [8] that a numberof three boost cells is a good compromise between volumeand mains current distortion. The DAB DC/DC converter isoperated with the same switching control strategy as the SSFF,adapted for constant input and output voltages (VDC1 = VDC2).

The objective function for the derivation of the optimumvalues of the passive components is the average (over one halfof the AC input period) of the square of the instantaneous

switch RMS currents (I2S,eq,rms, equation (7), minimization

problem), resulting in the inductance values and transformerratios depicted in Table II. The inductance values (L1−3) forthe TCM PFC are determined to obtain an average switchingfrequency of 120 kHz in the nominal operating point, applyinga limit of fs,max = 250kHz. It should be noted that forreaching the minimum commutation current in the secondaryside active bridges of the DAB converters within the whole ACoperating range, the HF transformer magnetizing inductancesLM depicted in Table II are used [6], [7]. Fig. 3 shows thetypical current and voltage waveforms for the full bridge -full bridge DAB DC/DC converter (left) and the TCM PFC(right). In Fig. 4 the RMS currents iS,rms(ωt) occuring in thehigh-frequency switches during a half input sinewave interval(50 Hz) for the three converter concepts, at nominal input andoutput voltage, and 100%, 50% and 10% of the nominal inputcurrent is depicted.

TABLE IIINDUCTANCE VALUES AND TRANSFORMER RATIOS

DS converter SSHF converter SSFF converter

L1−3 60 µHL 27.6 µH L 3 µH L 11.2 µHLM 193 µH LM 33.8 µH LM 105.45 µH

n1/n2 1.25 n1/n2 0.5 n1/n2 1

variable switching period

t

iL1

vAC

vAC, vS12, iL1 vS12

iDC1

i1v'2

v1

iL

v1, v'2, iL, i1, iDC1

t

T

Fig. 3. Typical current and voltage waveforms for the full bridge - full bridgeDAB converter (left) and the TCM PFC (right).

III. LOSS AND VOLUME MODELS

The switching losses for the soft-switching converter topolo-gies presented in Section II are low, especially as the controlequations assure a minimum switch commutation current.Therefore the most important loss contributions are the semi-conductor conduction losses, the gate losses, and the losses inthe passive components. As components losses and volume aremutually coupled (e.g. a large-sized transformer naturally haslower losses), accurate models that correlate these two quan-tities are required to analytically calculate the performanceindices of a converter, such as efficiency and power density.

A. Semiconductor Losses

Conduction losses of a MOSFET are proportional to the on-resistance RDS(on). However, for allowing direct comparison ofdifferent devices and device technologies it is more convenientto consider specific device characteristics by referring them to

1069

Cur

rent

(A)

0

5

10

Angle ωt (rad)0 π/2 π

IAC,leg=22.62/3 A

11.31/3 A

2.26/3 A

switch Sx1

Cur

rent

(A)

0

5

10

Angle ωt (rad)0 π/2 π

IAC,leg=22.62/3 A

11.31/3 A2.26/3 A

switch Sx2

Cur

rent

(A)

0

20

40

Angle ωt (rad)0 π/2 π

Cur

rent

(A)

0

10

20

30

Angle ωt (rad)0 π/2 π

iAC(ωt)

Cur

rent

(A)

0

10

20

30

Angle ωt (rad)0 π/2 π

Cur

rent

(A)

0

10

20

30

Angle ωt (rad)0 π/2 π

iAC,leg(ωt)

Cur

rent

(A)

0

10

20

Angle ωt (rad)0 π/2 π

Cur

rent

(A)

0

10

20

Angle ωt (rad)0 π/2 π

iDC1(ωt)iAC(ωt)

IAC=22.62 A

11.31 A

2.26 A

IAC=22.62 A

11.31 A

2.26 A

IAC=22.62 A

11.31 A

2.26 A

IAC=22.62 A

11.31 A

2.26 A

IDC1=16*230/400=9.2 A

4.6 A0.92 A

IDC1=16*230/400=9.2 A

4.6 A

0.92 A

switch Sp,x

switch Ss,x

switch Sp,x

switch Ss,x

switch Sp,x

switch Ss,x

DS converterSSHF converter SSFF converter DS converter

iS,rms(ωt) iS,rms(ωt) iS,rms(ωt) iS,rms(ωt)

Fig. 4. RMS currents iS,rms(ωt) in the high-frequency switches at nominal input and output voltage, and 100%, 50% and 10% of the nominal input current.

the utilized active Si area ASi,act (4). The conduction losses ofa power MOSFET are then given by:

PS,cond =R∗

DS,on

ASi,actI2

S,eq,rms (5)

with R∗DS,on the specific on-resistance, being a function of the

juntion temperature Tj and the drain current density JD:

R∗DS,on = R∗

DS,on |Tj=Tj,ref,JD=JD,ref

· (1 + α1∆Tj + α2∆T 2j )

· (1 + β1∆JD + β2∆J2D)

(6)

and

I2S,eq,rms =

1

π

∫ π

0

(iS,rms(ωt))2

d(ωt) (7)

∆Tj and ∆JD are deviations from the reference junctiontemperature Tj,ref and the reference drain current density JD,ref.The specific on-resistance in dependence of JD for differentcommercially available 600V MOSFET devices is presentedin Fig. 5. Conduction losses in the internal body diodes areneglected as in normal operation they only conduct currentduring a very small time interval. As it is assumed that thetransistor switching losses can be neglected (i.e. the turn-off

R* D

S(o

n)(Ω

mm

2 )

0

20

40

60

Drain Current Density JD (A/mm2)0 0.2 0.4 0.6 0.8 1.0

SPW47N60CFDIPW60R045CPIXFB82N60PSTY112N65M5

Conventional

Super Junction

Fig. 5. Specific on-resistance of several 600 V MOSFETs in dependence ofJD, at Tj = 150C.

commutation current is controlled to be high enough to assurelossless ZVS operation), the only switching frequency relatedlosses are the gate losses:

PS,sw = PS,gate = fs ·Q∗

GASi,act

Ugs,refU2

gs (8)

where Q∗G is the specific total gate charge. A turn-on gate volt-

age of Ugs = 12V is assumed for every switch. The MOSFETjunction temperature Tj depends on the total MOSFET losses(PS = PS,cond+PS,sw) and the thermal resistance Rth,j-b betweenthe die and the coolant (coldplate with isothermal bottomtemperature Tb = 80C), and is calculated by:

Tj = PSRth,j-b + Tb (9)

Thermal equilibrium can be found by solving the interlinkedequations for the power losses and the junction temperature(5), (8), (9). The specific parameters required for the calcula-tion of the MOSFET losses are depicted in Table III.

TABLE IIISEMICONDUCTOR DEVICE PARAMETERS

MOSFET Parameters

Device UDSS ASi R∗DS,on Q∗

GV mm2 Ωmm2 nC/mm2

SPW47N60CFD 600 69.33 9.75 4.48IPW60R045CP 600 69.16 6.77 2.70IXFB82N60P 600 193 36.31 1.27STY112N65M5 600 123 4.94 2.92R∗

DS,on at J∗D = 0.5A/mm2 and Tj = 150C

Fig. 6. Package interiors and FEM models, showing respectively the chipsizes and the temperature distribution for several of the semiconductor deviceslisted in Table III.

1070

B. Semiconductor Volume

The volume occupied by each semiconductor device, Vsem,can be related to its losses when the relation between the ther-mal resistance Rth,j-b and the dimensions of the transistor-coldplate assembly is known. The same transistor cooling conceptis assumed for all topologies, consisting of an aluminium coldplate with a thickness of hCP = 8mm and constant bottomtemperature Tb = 80C, combined with a thermal pad, and thesemiconductor packages (Fig. 7). A thickness of hpkg = 8mmis taken for the semiconductor package, including mountingwith a screw, clamp or plate. The surface area of the coldplateis calculated from the Si area, taking into account the overheadcaused by the packaging of the Si chips, the connectionpins, and the space that is needed between two transistorswhen mounting them on a PCB. Therefore, when scalingthe semiconductor area with a factor fSi, each dimension isscaled with a factor

√fSi, allowing to determine the total

area occopied by a semiconductor - cold plate assembly. Bymultiplying this area with the height (hCP + hpkg) of theassembly, the volume Vsem can be calculated.

Fig. 8 shows a simplified steady state thermal model ofthe semiconductor - cold plate assembly. The total thermalresistance between the MOSFET junction and the bottom ofthe cold plate consists of a series connection of the MOSFETjunction-to-case thermal resistance Rth,j-c, the thermal resis-tance of the thermal pad Rth,pad = hpad/kpadApad, and the thermalresistance of the coldplate Rth,t-b = hCP/kCPACP. For eachMOSFET type listed in Table III, the relation between Rth,j-cand the Si area ASi was detemined by detailed modeling ofthe package and FEM simulation, resulting in the relations de-picted in Fig. 9. All analytical thermal models were validatedthrough FEM simulations.

Tb=80ºC

Mounting

Cold plate

Transistor

Thermal padhpkg

hCP

Fig. 7. Semiconductor-cold plate assembly. The packages are mounted ontoan aluminium cold plate with isothermal bottom surface at 80C.

PS,eq,1

Rth,j-c,1

Rth,pad,1

Rth,t-b,1

PS,eq,n

Rth,j-c,n

Rth,pad,n

Rth,t-b,n

Tb=80ºC

Fig. 9

PL

Rth,L-b

PTr

Rth,Tr-b

Fig. 8. Thermal network of the cold-plate assembly.

Rth

,j-c

(K/W

)

0

0.2

0.4

0.6

0.8

1.0

Total chip size (mm2)0 50 100 150 200

SPW47N60CFD

IPW60R045CP

IXFB82N60P

STY112N65M5

Fig. 9. Junction to case thermal resistance in dependence of the chip sizefor different 600 V MOSFETs. The relations are derived via modeling of thepackages and FEM simulation. The datasheet values are indicated by marks.

C. Inductors and Transformers

Losses in inductors and transformers depend on the geome-try and the arrangement of the windings, the type of wire,the core type, and the geometry and material of the core.The resulting (boxed) volume is mainly determined by thecore geometry. In the scope of this paper, an optimizationalgorithm was developed to optimize each of the possiblecombinations. This allows to map a multi-dimensional designspace into a multi-dimensional performance space for each in-ductor/transformer. The boundary of the feasible performancespace indicates the best possible compromise with respectto different performance indices (i.e. efficiency (losses) andpower density (volume)). For the optimization, planar coresare considered because of their advantageous properties withrespect to high power density and excellent electromagneticand thermal characteristics. All possible EELP and EILP corecombinations from FERROXCUBE (core material: 3F3) andEPCOS (core material: N49, N87, and N92) in the dimensionsrange from ELP32 up to ELP64 were considered. The numberof cores was limited by setting a maximum of 15cm to the totalcore length. Litz wires are chosen to reduce eddy current lossesin the windings. All commercially available Litz wires fromthe RUPALIT Classic product range of PACK-FEINDRAHTEwere taken into consideration. Four possible arrangementsare investigated, including split, concentric, hexagonal andorthogonal type windings.

For each iteration, in a first step of the optimization al-gorithm the reluctance model Rm is calculated in order tomeet the inductance values (L, LM, L1-3) depicted in Table II(the inductance is controlled with the air gap length lg), whileguaranteeing that the peak induction Bpk and air gap lengthlg do not exceed a maximum value. This introduces an upperand lower limit for the number of turns (transformer primaryside: n1, inductor: N ):

(V · s)prim,max

2Bpk,maxAc6 n1 6

√LM(Rm,core +Rm,air,max |lg=lg,max

)(10)

LIL,pk

Bpk,maxAc6 N 6

√L(Rm,core +Rm,air,max |lg=lg,max

)(11)

1071

The upper boundary of the maximum operating flux Bpk,max isset by the core material saturation flux Bsat, applying a 20%safety margin to achieve low core losses and to avoid operationclose to saturation. (V ·s)prim,max is the maximum Volt-secondsproduct (primary side of the transformer), Ac is the effectivecore cross section, and IL,pk the peak inductor current. Theair gap reluctance Rm,air is calculated using the 3D methodproposed in [13]. In a second step the objective function iscalculated (i.e. the total inductor/transformer losses), requiringdetailed models of the winding losses and core losses. Foreach iteration the objective function is minimized within thedesign constraints such as the available window area. Theohmic losses in the Litz wires can be separated into skineffect losses PLitz,S from self-induced eddy currents inside theconductor, external proximity effect losses PLitz,P,e from eddycurrents due to the external magnetic field He (originated in theair gap fringing field and the magnetic field from neighboringconductors), and internal proximity effect losses PLitz,P,i fromeddy currents due to the internal magnetic field Hi (producedby the wire itself). The winding losses per unit length (index”l”) can be calculated with [14]:

PLitz,S,l = ns ·RDC · FR(f) ·

(I

ns

)2

(12)

PLitz,P,l = PLitz,P,e,l + PLitz,P,i,l (13)

PLitz,P,l = ns ·RDC ·GR(f) ·

(He

2+

I2

2π2d2b

)(14)

Here, RDC is the per unit length DC resistance of a singlestrand of the Litz bundle, ns the number of strands in the bun-dle, db the diameter of the bundle, and I the Fourier amplitudecoefficients of the current time function ibundle(t). FR(f) andGR(f) are factors that model the frequency dependence ofthe losses and are given in [14], which also provides the 2Dmethod used for calculating the external field He. The Corelosses per unit volume (index ”V”) are calculated with theSteinmetz parameters k, α, β using the improved GeneralizedSteinmetz Equation (iGSE) [15]:

Pcore,V =1

T

∫ T

0

ki

∣∣∣∣dBdt∣∣∣∣α (∆B)

β−αdt (15)

The performance space for the SSHF inductor is depicted inFig. 10(a). An overview of the boundaries of the performancespaces of all inductors/transformers is shown in Fig. 10(b).The designs that were chosen (marked) were thermally verifiedusing a 2D nodal network (represented by RL-b and RTr-b inFig. 8), using the same coldplate as in Section III and assuminga maximum inner temperature of 120C.

D. DC-Link Capacitors

The capacitance values required for keeping the 100Hzripple amplitude ˆust of the DC-link voltages within its limit(ˆust,max = 0.05 · VDC,nom) are calculated using:

Cst =Qst

2ˆust,max(16)

Indu

ctor

Los

ses

PL

(W)

0

20

40

60

80

Inductor Volume VL (cm3)0 100 200 300 400 500

(a) Performance space of the SSHF DAB inductor.

0

5

10

15

20

25

30

0 100 200 300 400 500Inductor / transformer Volume (cm3)

Tot

al L

osse

s (W

)

SSHF transformerSSHF inductorSSFF transformerSSFF inductorDS transformerDS DAB inductorDS PFC inductor

(b) Boundaries of the performance spaces of all induc-tors/transformers. The chosen designs are marked.

Fig. 10. Results of the inductor/transformer optimization.

where the charge difference Qst is determined by:

Qst =1

2

∫ 10ms

0

|iC,st(t)|dt (17)

The capacitor current iC,st(t) is the difference between the in-coming and outgoing current, iC,st(t) = iC,st(in)(t)− iC,st(out)(t).Given the operating range, the value of Cst = 962.5µF is thesame for each converter concept. For the capacitor volumecalculations, electrolytic capacitors are chosen above filmcapacitors because of their lower volume/capacitance ratio,as can be seen from Fig. 11. For a given rated voltage thevolume of EPCOS high density electrolytic B4345x 550VDC-link capacitors scales linearly with the capacitance, VC =kC1 + kC2C = 88.8 cm3 + 0.1969 cm3/µF ·C. In practice, thebulky 100Hz DC-link capacitors are often accompanied bysmall high-frequency capacitors, which can be polypropylene(PP) film type capacitors. However, they only account for asmall portion of the total capacitor volume and are thereforenot taken into account. The same remark can be made for theother high-frequency capacitors. The losses in the capacitorsare neglected in this comparison.

E. EMI filters and Auxiliary Circuits

Typically, the losses in the EMI filters and auxiliary circuitsonly account for a very small portion of the total converterlosses and are therefore neglected. Moreover, since it was notthe intention of this paper to perform a detailed design of theEMI filter and auxiliary circuits for each topology, the volumeoccupied by these components is estimated based on the realprototype converters shown in Fig. 15.

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Vact,comp = 0.118 dm3

SSFF converter:

Ploss,trans,tot = 214 W

ASi,tot = 502 mm2

Tj (

ºC)

Los

ses

(W)

Tj(

ºC)

Los

ses

(W)

Active chip area (mm2)

Tj (

ºC)

Los

ses

(W)

Active chip area (mm2)Active chip area (mm2)

80

100

1200

10

20

0 50 10080

100

1200

20

40

60

0 50 10080

100

1200

10

20

0 50 100

S12

S11

Sp,x Ss,x

SN,xSp,x

Ss,x

SSR

Sp,x

Ss,xSSR

Sp,xSs,x

SSR

Sp,x

Ss,x

SSR

S11

S12 Sp,x

Ss,x

SN,x Vact,comp = 0.128 dm3

SSHF converter:

ASi,tot = 504 mm2

Ploss,trans,tot = 212 W

ASi,tot= 400 mm2Vact,comp=0.131 dm3

DS converter:

Ploss,,trans,tot = 165 W

SSFF converterSSHF converter DS convertert

Fig. 12. Junction temperature and semiconductor losses (conduction + gate losses) in function of the active chip area, for the separate switches in eachtopology (IPW60R045CP MOSFETs, nominal operating conditions). For each switch, ASi,act for Tj = 100C is marked.

VC

(cm

3 )

0

100

200

300

C (µF)200 400 600 800 10000

MKP, B3277x, DC, 800VELCO, B4345x, DC, 550V

Fig. 11. Volume versus capacitance for Aluminium electrolytic andPolyPropylene DC-link capacitors (B4345x respectively B3277x, EPCOS).

IV. TOPOLOGY COMPARISON

A. Semiconductor Chip Area Based Converter Comparison(SAC2)

In order to allow for a fair comparison between the differenttopologies, the total chip area needed to not exceed a junctiontemperature Tj of 100C in all semiconductor devices and atnominal operating conditions is used as a first comparisoncriterion. Therefore, the models described in Section III-A,correlating the thermal and electrical characteristics of thesemiconductor devices to the chip area, are used. Fig. 12 showsthe results of the SAC2 for the IPW60R045CP MOSFET. Thelowest total chip size was achieved with the DS converter,while the lowest volume (cold plate assembly + gate drivers)is for the SSFF topology. The SSHF has the worst chip areautilization.

B. Efficiency

Under the considerations of Section III, the converter effi-ciency is calculated from:

η =PAC,in − (PS,cond + PS,sw +

∑(PLitz + Pcore)ind., transf.)

PAC,in(18)

As semiconductor losses strongly depend on the specificdevice parameters and the chip area per switch, and due to thevarying number of semiconductors, they can only be compared

among the converter concepts for the same total Si area ASi,Σ.For each device a weight factor γi is introduced that indicatesthe percentage of ASi,Σ and is calculated in relation to the sumof all RMS currents (γi = I2

eq,rms,i/∑I2

eq,rms,i). The calculatedefficiency of all converter concepts is depicted in Fig. 13.STY112N65M5 MOSFETs, having the lowest R∗

DS,on, are usedin the synchronous rectifier of the single stage topologies(switches SSR), as well as in the low-frequency leg of the TCMPFC (switches SN,x). In the DABs of all topologies (switchesSp,x, Ss,x), and in the high-frequency legs of the TCM PCF(switches Sx,x), IPW60R045CP MOSFETs are used because oftheir better switching characteristics. The DS converter has thehighest efficiency at nominal power, while the SSFF convertershows the best partial load performance. The SSHF converterhas the worst efficiency, both at nominal power and at partialload.

Eff

icie

ncy

η(%

)

95

96

97

98

Input Power PAC (kW)0 1.00 2.00 3.00 3.68

SSHF converterSSFF converterDS converter

Fig. 13. Calculated efficiency of the SSHF, the SSFF, and the DS converters.

C. Power DensityWeight and volume limitations cause the power density to

be an important performance index for the analyzed AC/DCconverter concepts, especially in automotive applications, andcan be estimated from:

ρ =PDC,out

(1 + fpack)(Vsem + VGD + VTr. + VInd. + VC + Vx)(19)

where VGD is the volume of the gate drivers, and Vx the volumeof the auxiliary circuits, EMI filter and control board. In the

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following, Vx is estimated based on the existing prototypesshown in Fig. 15. A factor fpack = 30% accounts for theincrease in volume due to non-ideal packing, interconnectionof the components, and not considered small components (e.g.the high-frequency capcitors). As the correlation betweenconverter losses and volume is conflicting, a comparison of ρis only meaningfull in consideration of the same efficiency.Therefore a total inductor and transformer loss of 35W isaasumed, and the total Si area ASi,Σ is determined to obtainan efficiency of η = 97.2% at nominal operating conditions.The converter volumes for the different converter conceptsare given in Fig. 14. The calculations predict the lowestvolumes (highest power density) for the single stage converterconcepts.

Com

pone

nt V

olum

e (c

m3 )

0

500

1000

1500

SSHF SSFF DS

Aux., Control, EMICapacitor CstInductors L1-3Inductor LTransformerGate DriversSemiconductors

Fig. 14. Converter volumes for obtaining a nominal load efficiency of η =97.2%. ASi,SSHF = 1357mm2, ASi,SSFF = 1346mm2, ASi,DS = 889mm2.

Fig. 15. Experimental prototypes of the SSHF (left) and DS (right),bidirectional, isolated AC/DC converters.

V. CONCLUSION

A comparative evaluation of three soft-switching, bidirec-tional, isolated AC/DC converter concepts is presented. A chiparea based comparison (SAC2) shows an advantage for theconventional DS converter concept since the semiconductorarea is better utilized. This reflects in the highest efficiency innominal operating conditions. In partial load the SSFF outper-formes the DS converter as the variable frequency TCM PFCsuffers from high RMS currents during low load (switchingfrequency limit). The SSHF has the worst semiconductor util-isation, resulting in the lowest overall efficiency. Concerningcomponent count and power density, the single-stage conceptsare advantageous as they use less active components and show

a lower volume for the passive components, being also a costand reliability advantage. The volume benefit of the single-stage concepts becomes even bigger when being used in athree-phase configuration, as the bulky 100Hz capacitor can beommited. Disadvantageous for the dual-stage converter is alsothe variable switching frequency operation of the TCM PFC,while the single-stage converters cannot assure a flat output-bus DC voltage in a single-phase configuration. Experimentalprototypes of the SSHF and DS validate the conclusions ofthe theoretical analysis.

REFERENCES

[1] A. Stupar, T. Friedli, J. Minibock, M. Schweizer, and J. W. Kolar,“Towards a 99% Efficient Three-Phase Buck-Type PFC Rectifier for 400V DC Distribution Systems,” in IEEE 26th Applied Power ElectronicsConference and Exposition (APEC 2011), March 2011, pp. 505–512.

[2] A. Matsumoto, A. Fukui, T. Takeda, and M. Yamasaki, “Developmentof 400-Vdc Output Rectifier for 400-Vdc Power Distribution System inTelecom Sites and Data Centers,” in 32nd International Telecommuni-cations Energy Conference (INTELEC 2010), June 2010, pp. 1–6.

[3] A. Emadi, S. S. Williamson, and A. Khaligh, “Power ElectronicsIntensive Solutions for Advanced Electric, Hybrid Electric, and Fuel CellVehicular Power Systems,” IEEE Transactions on Power Electronics,vol. 21, no. 3, pp. 567–577, May 2006.

[4] K. Clement-Nyns, E. Haesen, and J. Driesen, “The Impact ofVehicle-to-Grid on the Distribution Grid,” Electric Power SystemsResearch, vol. 81, no. 1, pp. 185–192, 2011. [Online]. Available:http://www.sciencedirect.com/science/article/pii/S0378779610002063

[5] Directorate-General for Research and Innovation, European Commission.(2005) Towards Smart Power Networks, Lessons Learnedfrom European Research FP5 Projects. [Online]. Available:http://ec.europa.eu/research/energy/eu/publications/index en.cfm

[6] J. Everts, J. Van den Keybus, and J. Driesen, “Switching Control Strategyto Extend the ZVS Operating Range of a Dual Active Bridge AC/DCConverter,” in IEEE Energy Conversion Congress and Exposition (ECCE2011), Sept. 2011, pp. 4107–4114.

[7] J. Everts, J. Van den Keybus, F. Krismer, J. Driesen, and J. W. Kolar,“Switching Control Strategy for Full ZVS Soft-Switching Operation ofa Dual Active Bridge AC/DC Converter,” in IEEE 27th Applied PowerElectronics Conference and Exposition (APEC 2012), Feb. 2012.

[8] C. Marxgut, J. Biela, and J. W. Kolar, “Interleaved Triangular CurrentMode (TCM) Resonant Transition, Single Phase PFC Rectifier with HighEfficiency and High Power Density,” in International Power ElectronicsConference (IPEC 2010), June 2010, pp. 1725–1732.

[9] G. G. Oggier, G. O. Garcia, and A. R. Oliva, “Switching Control Strategyto Minimize Dual Active Bridge Converter Losses,” IEEE Transactionson Power Electronics, vol. 24, no. 7, pp. 1826–1838, July 2009.

[10] F. Krismer and J. W. Kolar, “Accurate Power Loss Model Derivationof a High-Current Dual Active Bridge Converter for an AutomotiveApplication,” IEEE Transactions on Industrial Electronics, vol. 57, no. 3,pp. 881–891, March 2010.

[11] S. Waffler and J. W. Kolar, “Comparative Evaluation of Soft-SwitchingConcepts for Bi-Directional Buck+Boost DC-DC Converters,” in Inter-national Power Electronics Conference (IPEC 2010), June 2010, pp.1856–1865.

[12] T. Friedli and J. W. Kolar, “A Semiconductor Area Based Assessment ofAC Motor Drive Converter Topologies,” in IEEE 24th Applied PowerElectronics Conference and Exposition (APEC 2009), Feb. 2009, pp.336–342.

[13] J. Muhlethaler, J. W. Kolar, and A. Ecklebe, “A Novel Approach for 3DAir Gap Reluctance Calculations,” in IEEE 8th International Conferenceon Power Electronics and ECCE Asia (ICPE ECCE 2011), June 2011,pp. 446–452.

[14] ——, “Loss Modeling of Inductive Components Employed in PowerElectronic Systems,” in IEEE 8th International Conference on PowerElectronics and ECCE Asia (ICPE ECCE 2011), June 2011, pp. 945–952.

[15] K. Venkatachalam, C. R. Sullivan, T. Abdallah, and H. Tacca, “AccuratePrediction of Ferrite Core Loss with Nonsinusoidal Waveforms Usingonly Steinmetz Parameters,” in IEEE Workshop on Computers in PowerElectronics, June 2002, pp. 36–41.

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