IMPLEMENTATION OF A NOVEL SOFT-SWITCHING INVERTER

FOR SWITCHED RELUCTANCE MOTOR DRIVES

by

Naveen Yadlapalli

Thesis submitted to the Faculty of the

Virginia Polytechnic Institute and State University

In partial fulfillment of the requirements for the degree of

Master of Science

in

Electrical Engineering

Dr. Jason Lai, Chairman

Dr. Dushan Boroyevich

Dr. Alex Q. Huang

July 14, 1999

Blacksburg, Virginia

Implementation of a Novel Soft-Switching Inverter Topology forSwitched Reluctance Motor Drives1

Naveen Yadlapalli

(ABSTRACT)

The purpose of this thesis is to design, develop, implement and test a novel soft-switching

inverter topology suitable for switched reluctance motor drives. Present research being

done in the field of switched reluctance motor drive inverters, including soft-switching

inverters, is discussed. The novel topology is presented and the principle of operation is

described in detail. The validity of the topology is verified through simulation. The

various components of the system are designed and the hardware implementation is

presented. Experiments carried out to verify the operation of this inverter are explained.

Results are presented and comparison is made between hard switching and soft switching

inverter topologies. Conclusions are drawn regarding the effectiveness of the proposed

topology.

1 This work made use of ERC shared facilities supported by the National Science Foundation under award

EEC-9731677.

iii

ACKNOWLEDGEMENTS

I would like to express my deep gratitude to my academic and research advisor Dr. Jason

Lai for giving me an opportunity to be a part of CPES and for guiding me towards

completion of my thesis. I would like to thank Dr. Dushan Boroyevich and Dr. Alex

Huang for their valuable help from time to time and for agreeing to serve on my

committee. I would also like to thank Dr. Lee for giving me this opportunity to be a part

of CPES.

This work wouldn’t have been possible without the constant support of Dr. Lai and

Byeong-Mun Song. I am greatly indebted to them. I thank Sriram Chandrasekaran,

Francisco Canales and Sundar Sankaran for giving me valuable suggestions during

various stages of my thesis and helping me finish my research on time.

I would like to thank Kalyan Siddabattula and Jigna Vyas for their friendship and

constant support. Peter Barbosa, Carlos Cuadros, Jeffrey Batson, Joe Price O’Brien and

all the other people at CPES made my stay at CPES a memorable one.

Finally, I wouldn’t have been in this position if I hadn’t had the support and best wishes

from my family, especially my parents. I owe everything to them.

iv

TABLE OF CONTENTS

ACKNOWLEDGEMENTS………………………………………………………… iii

TABLE OF CONTENTS…………………………………………………………… iv

LIST OF FIGURES………………………………………………………………… vi

1 INTRODUCTION........................................................................................................

1.1 SWITCHED RELUCTANCE MOTORS .............................................................................1

1.2 SOFT-SWITCHING INVERTERS.....................................................................................2

1.3 SOFT SWITCHING IN SRM...........................................................................................4

1.4 THESIS OBJECTIVE AND OVERVIEW ............................................................................5

2 SWITCHED RELUCTANCE MOTOR DRIVE ........................................................7

2.1 THE SWITCHED RELUCTANCE MOTOR .......................................................................7

2.2 PRINCIPLE OF OPERATION ...........................................................................................8

2.3 CONVERTERS FOR SRM ...........................................................................................11

2.3.1 “Classic” Inverter............................................................................................11

2.3.2 Converters with one switch per phase.............................................................12

2.3.3 Converter with phases sharing the components..............................................14

2.4 SOFT-SWITCHING SRM INVERTERS .......................................................................16

3 THE SOFT-SWITCHING INVERTER................................................................17

3.1 THE SOFT-SWITCHING TOPOLOGY.............................................................................17

3.2 PRINCIPLE OF OPERATION ........................................................................................18

3.3 DESIGN OF THE RESONANT CIRCUIT.........................................................................24

v

3.4 SIMULATION...........................................................................................................27

3.5 CONTROL SEQUENCE..............................................................................................32

4 HARDWARE IMPLEMENTATION ...................................................................36

4.1 SETUP.....................................................................................................................36

4.2 POWER STAGE........................................................................................................37

4.3 GATE DRIVERS .......................................................................................................38

4.4 CONTROL BOARD ...................................................................................................40

5 RESULTS.................................................................................................................48

5.1 SWITCHING TRANSITIONS.......................................................................................48

5.1.1 Hard Switching..............................................................................................48

5.1.2 Soft Switching................................................................................................50

5.2 INVERTER OPERATION WITH INDUCTIVE LOAD ......................................................55

5.3 INVERTER OPERATION WITH RL LOAD ..................................................................57

5.4 INVERTER OPERATION WITH THE MOTOR ...............................................................60

5.5 INVERTER EFFICIENCY ...........................................................................................65

6 CONCLUSIONS AND FUTURE WORK ............................................................68

6.1 CONCLUSIONS ........................................................................................................68

6.2 FUTURE WORK.......................................................................................................69

REFERENCES……………………………………………………………………… 70

APPENDIX…………………………………………………………………………. 72

VITA………………………………………………………………………………... 77

vi

LIST OF FIGURES

Fig. 2.1 A typical 6/4 SRM…………………………………………………….…. 8

Fig. 2.2 Inductance profile of one phase of SRM………………………………… 9

Fig. 2.3 “Classic” SRM inverter……………………………………………….…. 12

Fig. 2.4 Converter configurations with one switch per phase……………………. 13

Fig. 2.5 (n+1) switch circuit……………………………………………………… 15

Fig 3.1 Proposed Soft-Switching topology………………………………………. 18

Fig 3.2 A single phase of the proposed topology………………………………... 19

Fig 3.3 Key waveforms of the proposed topology………………………………. 20

Fig 3.4 Mode 1…………………………………………………………………… 21

Fig 3.5 Mode 2…………………………………………………………………… 21

Fig 3.6 Mode 3…………………………………………………………………… 22

Fig 3.7 Mode 4…………………………………………………………………… 22

Fig 3.8 Mode 5…………………………………………………………………… 23

Fig 3.9 Mode 7…………………………………………………………………… 24

Fig 3.10 Gate and switch voltage during turn-on under hard switching………….. 27

Fig 3.11 Switch voltage and current during turn-on under hard switching……….. 28

Fig 3.12 Switch voltage and current during turn-off under hard switching………. 28

Fig 3.13 Gate voltage for the main and the auxiliary switches…………………… 29

Fig 3.14 Gate and switch voltage during turn-on under soft switching…………... 30

Fig 3.15 Switch voltage and current during turn-on under soft switching………... 30

Fig 3.16 Switch voltage and current during turn-off under soft switching……….. 31

vii

Fig 3.17 Switch voltage and resonant current during turn-on…………………….. 31

Fig 3.18 Waveforms with incorrect timing sequence……………………………... 32

Fig 3.19 Voltage chopping waveforms……………………………………………. 33

Fig 3.20 Phase inductance sequence………………………………………………. 34

Fig 3.21 Phase pulse sequence……………………………………………………. 34

Fig 3.22 Phase sequence with high frequency chopping…………………………. 35

Fig 4.1 Proposed SRM drive system…………………………………………….. 36

Fig 4.2 Block diagram of the gate driver board………………………………….. 38

Fig 4.3 Gate driver circuit for a single MOSFET………………………………... 39

Fig 4.4 Typical output from the gate driver……………………………………… 40

Fig 4.5 Block diagram of the control board……………………………………… 41

Fig 4.6 Low frequency input-1…………………………………………………... 42

Fig 4.7 Dual monostable used for getting a delay……………………………….. 42

Fig 4.8 Phase delay using “one-shot”……………………………………………. 43

Fig 4.9 Sequence of pulses after the delay stage………………………………… 44

Fig 4.10 Sequences of pulse with high frequency switching……………………... 44

Fig 4.11 Delayed signal for the main switches……………………………………. 45

Fig 4.12 Gate signals for the main and auxiliary switch………………………….. 45

Fig 4.13 Experimental auxiliary and main gate signals…………………………… 46

Fig 4.14 Motoring sequence of the phases………………………………………... 47

Fig 5.1 Gate and switch voltage during turn-on…………………………………. 48

Fig 5.2 Switch voltage and current during turn-on………………………………. 49

Fig 5.3 Gate and switch voltage during turn-off………………………………… 49

viii

Fig 5.4 Switch current and voltage during turn-off……………………………… 50

Fig 5.5 Gate and switch voltage during turn-on under soft switching…………... 51

Fig 5.6 Resonant inductor current during turn-on……………………………….. 51

Fig 5.7 Waveforms with a saturable inductor……………………………………. 52

Fig 5.8 Switch voltage and current during turn-on under soft switching………... 53

Fig 5.9 Gate and switch voltage during turn-off under soft switching…………... 54

Fig 5.10 Switch voltage and current during turn-off under soft switching……….. 54

Fig 5.11 Output current with an inductive load…………………………………… 55

Fig 5.12 Output phase current with a inductive load……………………………… 56

Fig 5.13 Output phase current with RL load under hard switching………………. 56

Fig 5.14 Average output current waveform with RL load under hard switching…. 57

Fig 5.15 Input current waveform with RL load under hard switching……………. 57

Fig 5.16 Average input current waveform with RL load under hard switching…... 58

Fig 5.17 Output phase current with RL load under soft switching………………... 58

Fig 5.18 Average output current with RL load under soft switching……………... 59

Fig 5.19 Input current with RL load under soft switching………………………... 59

Fig 5.20 Average input current with RL load under soft switching………………. 60

Fig 5.21 Output phase current with a motor load alone 61

Fig 5.22 Input current with motor load under hard switching…………………….. 61

Fig 5.23 Average input current with motor load under hard switching…………... 62

Fig 5.24 Output phase current with motor load under hard switching……………. 62

Fig 5.25 Average output phase current with motor load under hard switching…... 63

Fig 5.26 Output phase current with motor load under soft switching…………….. 63

ix

Fig 5.27 Average output phase current with motor load under soft switching…… 64

Fig 5.28 Input current with motor load under soft switching……………………... 64

Fig 5.29 Average input current with motor load under soft switching……………. 65

Fig 5.30 Inverter Efficiencies with RL load………………………………………. 66

Fig 5.31 Efficiencies of the inverter while running the motor……………………. 66

Fig A.1 The control board………………………………………………………... 72

Fig A.2 Gate driver board………………………………………………………… 73

Fig A.3 Power stage……………………………………………………………… 74

Fig A.4 Three-phase SRM……………………………………………………….. 75

1

1 Introduction

1.1 Switched Reluctance Motors

Switched Reluctance Motors (SRM) are fast becoming a popular alternative to Induction

Motors (IM) in the variable speed drive market. Though the first SRM was built in 1838,

it did not find widespread use until the late 1970’s [9]. This was due to the difficulty in

controlling the machine. Since the 1960’s, with the advent of power electronics and high-

power semiconductor switches, control of the SRM has become much easier and there

has been a renewed interest in SRM drives.

The advantages of the SRM are summarized below.

• Simple and robust structure.

• There are no windings on the rotor of the machine and hence it is inherently less

expensive.

• High torque-to-inertia ratio. It has high starting torque without the problem of in-rush

currents and its power density is comparable to that of an induction machine.

• Maximum operating speed and maximum rotor temperatures it can withstand are

higher when compared to other machines of similar ratings.

• Each phase winding of the SRM is independent of the other phase windings and this

makes the machine highly reliable.

2

• Motor torque is independent of the phase current polarity. Thus, the converter for the

SRM drive requires only one switch per phase.

• Has inherent four-quadrant operation.

• Has a wide constant torque/power region in the torque-speed characteristics.

• High efficiency throughout the entire torque-speed range.

The disadvantages of SRM are summarized below.

• Pulsed nature of torque production, which leads to torque ripple and acoustic noise.

• To have high torque-to-volume ratio, the airgap between the stator and rotor should

be very small. This leads to less manufacturing tolerances and increased acoustic

noise.

Overall, SRM has many advantages and thus can be successfully used in variable speed

drives. The major disadvantage of having a high torque ripple can be overcome by using

suitable control methodologies. Of late, SRM has become a better alternative in a host of

applications including electric vehicles, traction, industrial drives, position servo,

robotics, textiles, aerospace, office automation, machine tools and appliances.

1.2 Soft-Switching Inverters

It is desirable for power converters to have high efficiencies and high power densities.

Packaging and cost limitations require that the converter have a small physical size and

weight. Power density and electrical performance are dependent on the switching

3

frequency as it determines the values of the reactive components in the converter. Thus,

high frequency operation of the converter is highly desired. However, operation at high

frequency results in higher switching losses and higher switching stresses caused by the

circuit parasitics (stray inductance, junction capacitance).

The main factors that contribute to the high-frequency switching losses are:

• Semiconductor devices have non-zero turn-on and turn-off times and thus there is a

finite time during the transitions wherein the devices are conducting a significant

current while a large voltage is applied across it. This results in large energy

dissipation. This energy loss increases with increasing frequency.

• At high frequencies, high dv/dt and di/dt induce voltage and current oscillations in

parasitic capacitors and inductors during switching transitions. These oscillations

result in higher peak current and voltage in the devices and thus the switching loss

increases. Furthermore, these oscillations create EMI noise, which can interfere with

other parts of the circuit or surrounding electronic equipment.

• When a device is turned on while having a voltage across it, the energy stored in the

parasitic capacitance across the switch is dissipated in it. This loss increases with the

frequency and is proportional to the square of the voltage across the device before

turn-on.

Soft-switching techniques force the switch voltage or current to zero before the device

switching, thus avoiding current and voltage overlap during the switching transition. The

advantages of soft switching are as follows:

4

• Lower switching losses due to smaller overlap of switch voltage and current.

• Lower dv/dt and di/dt and thus lower voltage spike and EMI emissions.

• Higher reliability due to reduced stresses on the switching components.

• Reduced voltage and current ratings for the devices.

• Smaller reactive elements.

Soft switching for the power devices can be achieved by either zero-voltage switching

(ZVS) or zero-current switching (ZCS). ZVS consists of turning on the switches while

the voltage across them is zero. ZCS consists of turning off the switches when the current

through them is zero. Common to all approaches of soft switching is the use of reactive

elements to shape the current and voltage waveforms to achieve the necessary conditions

for ZVS or ZCS.

Soft switching has been proven to be an effective means of reducing switching losses and

for attaining higher overall efficiencies. Various soft-switching techniques have been

developed in the recent years.

1.3 Soft switching in SRM

Enormous amounts of power electronic drives are being used in the industry nowadays.

They find wide applications in industrial drives, office automation and appliances. SRM

drives have also become popular and various converter topologies have been proposed

for these SRM drives. Due to the possibility of lower cost for SRM drives when

5

compared to the IM drives, SRM drives are becoming quite popular in certain drive

markets.

The majority of soft-switching inverters proposed in the recent years have been aimed at

the Induction Motor drive applications. Only a few studies on soft-switching converters

for SRM drives have been carried out until now [13-15]. Inverters for SRM drives are

inherently different from the inverters for IM drives due to the differences in the machine

characteristics. Thus, soft-switching inverters for SRM have certain specific

characteristics. Although there has been lot of research on soft switching in general, there

hasn’t been much work done on soft switching specific to SRM drives.

1.4 Thesis objective and Overview

The primary objectives of this thesis are to design, develop, implement and test a novel

soft-switching inverter topology specific to an SRM drive application and to compare the

switching losses in the hard switching and soft switching cases.

The drive system developed is based on a half horsepower three-phase SRM. This

machine is used in washing machines. In the industry, a half-bridge inverter is commonly

used to drive an SRM. As it would be beneficial to compare the soft-switching results

with those of a commonly used hard-switching system, it was decided that the soft

switching would be attained through an add-on soft-switching leg. Thus, it is possible to

get both the hard switching and soft switching results from the same powerstage layout.

6

Analysis is done to decide upon a proper soft-switching topology satisfying the above

conditions and also specific to SRM applications. After the topology is selected, the

powerstage and the resonant circuit are designed and the components selected. This

design is verified through simulation. Later, the system is built and tests are conduced in

both the hard switching and the soft switching case. The results from these tests are

compared to analyze the advantages and disadvantages of the proposed soft-switching

scheme.

This thesis is organized as follows.

Chapter 2 describes the theory and principle of operation of SRM. Characteristics

specific to the machine used in this experimental setup are also explained. Various

inverter topologies being used in the SRM drive industry are looked into. And finally, the

research being done in soft switching for SRM is discussed.

Chapter 3 gives the theory and principle of operation of the proposed soft-switching

drive system. Various components of the power stage and the resonant tank are designed.

The control sequence of the inverter is determined.

Chapter 4 explains the hardware implementation of this drive system, including the

powerstage, gate-drivers and the open-loop control board.

Chapter 5 presents the experimental results. Furthermore, the hard-switching and soft-

switching results are compared.

And finally, Chapter 6 provides the conclusions derived from the thesis and discusses

further research possible on this work.

7

2 Switched Reluctance Motor Drive

2.1 The Switched Reluctance Motor

A Switched Reluctance Motor (SRM) is an electric motor in which torque is produced by

the tendency of its moveable part to move to a position of least reluctance, which

corresponds to the position of maximum inductance [9]. It is a doubly salient, singly

excited motor. That is, the SRM has salient poles on both the rotor and the stator, but

only the stator poles carry windings. The rotor tries to get to a position of minimum

reluctance by aligning itself with the stator magnetic field. In the presence of a rotating

magnetic field, the rotor tries to rotate along with the rotating magnetic field to always be

in a position of minimum reluctance. Thus, exciting the stator phase windings of the

motor in a particular sequence and consequently, controlling the rotating magnetic field,

we can control the movement of the rotor.

Figure 2.1 shows a typical 6/4 SRM. It is a three-phase machine and has 6 poles on the

stator and 4 poles on the rotor. The number of poles on the stator and on the rotor is

usually not equal. This is to avoid the eventuality of the rotor being in a state of

producing no initial torque, which occurs when all the rotor poles are locked in with the

stator poles. Here, the diametrically opposite stator pole windings are connected in series

and they form one phase. Thus, the six stator poles constitute three phases. When the

rotor poles are aligned with the stator poles of a particular phase, the phase is said to be in

an aligned position. Similarly, if the inter-polar axis of the rotor is aligned with the stator

poles of a particular phase, the phase is said to be in an unaligned position.

8

In a three-phase SRM, the direction of rotation of the rotor is opposite to the direction of

the switching sequence of stator poles. A unique feature of SRM is that it can be

1

1’

2

2’3

3’

Rotor

Stator

Fig 2.1 A typical 6/4 SRM with 6 rotor poles and 4 stator poles

operated, albeit with reduced power output, even when there is a loss of one of the

phases.

2.2 Principle of operation

When current flows in a phase, the resulting torque tends to move the rotor in a direction

that leads to an increase in the inductance. Provided that there is no residual

9

magnetization of steel, the direction of current flow is immaterial and the torque always

tries to move the rotor to the position of highest inductance. Positive torque is produced

when the phase is switched on while the rotor is moving from the unaligned position to

the aligned position.

Inductance(Phase)

Lmin

Lmax

Rotor Positionon off

UnalignedPosition

Aligned Position

Fig 2.2 Inductance profile of one phase of an SRM

The torque (T) produced in the SRM is given by the formula

θd

dLiT *

2

1 2∗=

Thus positive torque is produced when the phase is switched on during the rising

inductance. Consequently, if the phase is switched on during the period of falling

inductance, negative torque will be produced.

10

An SRM is normally operated by getting a feedback of the rotor position and firing the

phases depending on this feedback. The phase is switched on when the rotor is in the

unaligned position and switched off before it reaches the aligned position. This is done so

that the current (and flux) decays to zero before the inductance begins to fall, resulting in

negative torque. This in turn maximizes the effective torque. The angle between turn-on

and turn-off is called the dwell angle. The turn-on, turn-off and dwell angles are used to

control the torque output of the motor. Having a negative voltage across the winding

would help in getting the flux back to zero quickly. This way, the dwell angle can be

increased and the torque ripple can be minimized.

There are several ways of controlling an SRM [9]. The first one is a single pulse method.

Here a single pulse is given to each phase and the current builds up to the level required

for driving the load. This method is used in high-speed operation. The next method is

current chopping, wherein the current is maintained between two preset levels. This is

also called hysteresis control. Voltage chopping is the control method wherein the phase

switching is done at a high frequency. There are two types of voltage chopping. Soft

chopping is the scheme wherein the voltage applied to the phase winding switches

between the DC rail and zero. If it switches between +DC rail and –DC rail, it is called

hard chopping. By controlling the duty cycle of this high frequency switching, we can

control the current. Chopping is used in low speed operation.

As mentioned earlier, an SRM needs a position sensor for proper firing of the phases.

This increases the cost of the motor and thus makes it unsuitable to applications where

cost is a major issue. There has been a lot of research on sensorless control, wherein the

11

rotor position is estimated by sensing the phase currents and other techniques that are

more economical [16].

2.3 Converters for SRM

As the direction of torque doesn’t depend on the signs or magnitudes of flux-linkage and

current, the converter for a SRM has to supply only unidirectional current. This makes

SRM converters simpler than the converters for Induction Machines. The main

differences between converters for SRM and other converters are:

• Only one switch per phase is required. This is a big advantage when compared to the

converters for AC motor drives, which require two switches per phase.

• An SRM drive doesn’t encounter shoot through faults. This is because there is

always a motor winding in series with each main switching device.

• As the three phases of the motor are not connected, fault in one phase doesn’t effect

the other phases and they can continue to operate independently.

• The SRM has zero short-circuit current and zero open-circuit voltage. Thus, there are

less over-voltage and over-heating problems accompanied with faults.

There are many converters being used in the SRM industry [9,10]. The typical ones are

listed below.

2.3.1“Classic” Inverter

This converter is similar to the conventional six-step ac inverter, with the difference

being that the motor windings are in series with the phase switches. The switches have

12

voltage and current ratings that are similar to those of an equivalent AC inverter drive.

This converter provides the highest efficiency, reliability and control flexibility. By

controlling the upper and lower switches independently, we can achieve all forms of

control, including hard and soft chopping. Furthermore, it can have maximum

regenerative braking capability and equal performance in forward and reverse directions.

Fig 2.3 “Classic” SRM inverter with two switches per phase

In this converter, the motor winding prevents shoot-through faults and hence protective

circuitry is not required. This converter is the most widely used converter for SRM drive

applications in the industry.

2.3.2 Converters with one switch per phase

There are several converters that have only one switch per phase. For motors having three

phases or more, the minimum number of switches required, per phase, for full control is

one. Fig 2.4 shows four different converters having only one switch per phase. All the

converters provide a freewheeling path for the phase currents.

Vdc

13

Vdc Vdc

Vdc Vdc

(a) (b)

(c) (d)

Fig 2.4 Converter configurations with one switch per phase

Converter (a) has a switch in series with the phase winding and has a freewheeling diode

in parallel with the phase winding. When the switch is turned off, the phase winding

current freewheels through the diode. The disadvantage of this converter is that during

freewheeling, negative voltage is not applied across the winding and thus the time taken

for the flux to decay to zero is much longer. For proper control, the dwell angle should be

reduced and this would reduce the efficiency of the machine.

14

In Converter (b), an external resistance has been added to Converter (a) and this

resistance is used to generate reverse voltage. This is an inefficient method in that as the

current decreases, the reverse voltage magnitude also decreases and thus this gives rise to

a current “tail”. Coupled with the losses in the resistance, this phenomenon makes this

converter unsuitable to a lot of applications.

In Converter (c), a zener diode has been added to the Converter (b). This is useful in

sustaining a high reverse voltage magnitude and thus is a better alternative to Converter

(b).

In the three converters mentioned above, the peak voltage across the switch is the supply

voltage. Converter (d) uses a bifilar-wound motor. Such motors have lower efficiency

than the normal motors. When the switch is turned off, the current in the primary winding

is transferred to the secondary winding and freewheels through the diode. Thus, negative

voltage is applied across the winding and consequently it is possible to have larger dwell

angles. The resulting gain in efficiency is more than offset by the lower efficiency of the

bifilar windings. Furthermore, the peak voltage across the switch in this converter is

twice the supply voltage and thus switches with higher ratings have to be used.

2.3.3 Converter with phases sharing the components

None of the converters mentioned above shared components, i.e., each phase had its own

set of components. Thus, switches in each phase leg would carry only the current that

flows through the winding associated with that phase leg. There are some converters that

use shared components. Here, some of the switches and diodes would conduct all phase

currents.

15

Figure 2.5 (n+1) switch circuit.

Figure 2.5 shows a (n+1) switch converter. The number of switches in this converter is

one more than the number of phases. The main (upper) switch serves all the phases, while

the switches (lower) in series with the winding commutate the phases. There are also

variations of this converter such as the n*1.5 switch converter, wherein there is one upper

switch for every two phase windings and thus can only be used for motors with even

number of phases.

In this class of converters, the lower switching devices are switching at a higher

frequency than the upper switches and thus have higher switching losses. Also, the use of

a common switching device negates the fault tolerance inherent in a SRM converter. This

is because the phases are no longer independent of one another.

Apart from the converters mentioned above, there are several other converter

configurations used in SRM drives. The most notable of these is a C-dump converter

wherein all three phases freewheel into a dump capacitor before being returned to the dc

source by a resonant circuit [12]. All these converters are suitable for specific kind of

Vdc

16

applications. As mentioned earlier, the “classic” inverter is the most widely used in the

industry. For this research, the classic inverter is chosen as the standard to be compared

to the new soft-switching topology proposed.

2.4 Soft-Switching SRM Inverters

Research on soft-switching SRM drives is in its early stages. There have been very few

papers presented on this topic [13-15]. A ZVT converter, which is based on the n+1

switch converter, is described in [13]. A ZVT converter, which is based on the n*(1.5)

switch converter, is described in [14]. A ZCS converter, which is based on a topology

similar to the n+1 switch converter, is described in [15]. Apart from these papers, there

hasn’t been much research into soft-switching SRM drives.

The next chapter will present a new soft-switching topology that is based on the

traditional classic inverter. The soft-switching leg can be added to this inverter and thus it

is possible to verify the resourcefulness of the soft-switching topology very easily.

17

3 The Soft-Switching Inverter

3.1 The soft-switching topology

This research presents a novel soft-switching inverter for SRM drive applications. It

consists of a load side auxiliary resonant (ZVT) circuit, which is added onto to the

“classic” SRM inverter. It is a simple circuit in that the resonant circuit has only one

switching device in addition to the resonant inductor and a diode. For three-phase

operation, we still need only one switch and one resonant inductor but we need to use six

diodes. Thus a simple auxiliary topology is used and this keeps the additional costs, for

soft switching, under check. The soft switching SRM drive topologies discussed in

chapter 2 have there auxiliary components on the dc rail side and thus those components

have to be rated at the same level as the main circuit components. The proposed topology

is a load side auxiliary circuit and thus the resonant component stresses are at a lower

level than the main circuit component stresses. Therefore, the rating of the soft-switching

components is lower than the rating of the main circuit components.

Fig 3.1 shows the proposed soft-switching topology. This is a converter for a 3-phase

SRM machine. As mentioned earlier, the resonant leg is just an add-on to the classic

inverter. There are two switches per phase, in addition to two freewheeling diodes for the

de-fluxing operation. The resonant branch is connected across the three phase windings.

A zero voltage-turn-on (ZVT) condition is achieved for the main switches by current

injection from the auxiliary switch. Thus, this topology achieves ZVT for the main

switches. It also achieves zero current turn-off for the auxiliary device.

18

Fig 3.1 Proposed Soft-Switching topology

Vs Cs

Sa2

Sa1

Sb2

Sb1

Sc2

Sc1

PH. BPH. A PH. CSr

Lr

Cr Cr Cr

Cr Cr CrZVT Cell

Capacitors are placed across all main switches and diodes. These form a part of the

resonant circuit and are necessary to achieve the ZVT condition for the main switches.

Furthermore, they act as lossless snubber capacitors during turn-off. The main feature of

this topology is that we can achieve near zero voltage turn-on for the main switches under

different load conditions without utilizing variable timing control. Thus, control for this

topology is relatively simple when compared to other soft-switching topologies, which

require variable timing control for their operation.

3.2 Principle of Operation

Fig 3.2 shows one phase of the proposed converter, along with the soft-switching leg.

19

C1

S1

S2 C2

C4r

C3D1

D2

LI

LrI

SVINC

xSL r

Fig 3.2 A single phase of the proposed soft-switching inverter

It consists of two main switches S1 and S2 and two freewheeling diodes D1 and D2. S1

and S2 are switched on and off together. The basic operation of this circuit consists of

turning on the auxiliary switch a fixed time ahead of the main switches. The auxiliary

resonant circuit brings the voltage across the main switches to zero, enabling them to be

turned on at zero-voltage. During turn-off, the capacitors across the main switches act as

lossless snubbers and this reduces the turn-off losses. Thus this converter achieves near

zero voltage turn-on and reduces the turn-off losses, thereby appreciably reducing the

switching losses in the converter.

Fig 3.3 shows the important waveforms of this circuit during one cycle. It is assumed that

the load current stays constant during this switching cycle.

20

S1, S2

Sx

IL

ILr

VCE

IC

t0 t1 t2 t3t4 t5 t7t6

Fig 3.3 Key waveforms of the proposed topology

The different modes of operation can be explained as follows:

Mode 1: t0 – t1

Here, the main switches, S1 and S2, are in the off state and the load current is being

freewheeled through the diodes D1 and D2.

21

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad+_ Vsw

Fig 3.4 Mode 1

Mode 2: t1 - t2

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad+_ Vsw

Fig 3.5 Mode 2

The auxiliary switch is turned on and current starts to build up linearly in the auxiliary

branch. The current in the diodes D1 and D2 begins to fall linearly. The load current is

slowly diverted from the freewheeling diodes to the auxiliary branch.

Mode 3: t2 – t3

22

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad

Fig 3.6 Mode 3

At t2, the inductor (auxiliary) current equals the load current and the current through the

diodes becomes zero. Thus the diodes turn off under zero-current condition. The resonant

inductor, Lr, resonates with the capacitors across the switches and diodes. During this

process, the capacitors discharge and thus the voltage across the capacitors decreases.

Mode 4: t3 – t4

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad

+_

Fig 3.7 Mode 4

At t3, the capacitors discharge fully and thus the voltage across the switches becomes

zero. The switches can now be turned on under zero voltage condition. As it is difficult to

23

turn on the switches at this particular instant, only near zero voltage switching can be

achieved. After the switches are turned on, the resonant inductor current, ILr, decreases

linearly. At t4, this current becomes zero and the switches carry the load current, IL.

Mode 5: t4 – t5

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad

+_

Fig 3.8 Mode 5

The resonant current, ILr, dies down to zero at t4. After a finite time, the auxiliary switch

is turned off. Thus the auxiliary switch is turned off at zero current condition.

Furthermore, the auxiliary diode is also turned off at zero current condition.

Mode 6: t5 – t6

Here, the main switches conduct the load current and the circuit is in steady state.

Mode 7: t6 – t7

The main switches are turned off under hard switching. The lossless snubbers absorb the

load current until the diodes D1 and D2 are turned on. The operation then returns to Mode

1.

24

S1

S2D1

D2LLoad

Lr

Saux

Daux

C1

C2

C3

C4

Vdc

ILoad

+_

Fig 3.9 Mode 7

3.3 Design of the Resonant Circuit

The resonant components in this circuit are the resonant inductor Lr and resonant

capacitor Cr. These values have to be designed to get a highly efficient switching. ωr and

Zr are defined as follows:

rr

rCL ⋅

= 1ω

rrr C/LZ =

These components are in resonance during the time period t2 – t3. The initial resonant

inductor current, iLr(0), is equal to the load current, IL, which is assumed to be constant

here. The initial capacitor voltage, vCr(0), is equal to the supply voltage, VS. The

instantaneous values of these quantities, during resonance, are given by the equations

)sin()( tZ

VIti r

r

SLrL ω⋅+=

))cos(1()( tVtv rSCr ω−⋅=

25

From these equations, we know that the maximum resonant current would be

r

SLLr Z

VII +=max

We can rate our resonant switch with this information. As the resonant auxiliary switch

carries this peak current only during switch transitions, it can be rated for much lower

continuous current rating.

The timing sequence of the auxiliary switch is determined by calculating the time during

each mode of operation. The auxiliary switch is turned on at t1 and the resonant current,

ILr, starts building up linearly until time t2. At t2, ILr equals the load current. Thus the time

period T1, required for the resonant current to reach the load current, is calculated by

S

Lr

V

ILttT

∗=−= )( 121

Next, the resonant time has to be calculated. This depends on the value of the resonant

components. The resonant time period, T2, is given by the equation

rr CLttT ∗∗=−= π)( 232

The time required for the resonant current to die down to zero, T3, would be equal to T1

and can be calculated by

S

Lr

V

ILttT

∗=−= )( 343

Now the auxiliary switch is turned off a finite time after t4. Thus the total conducting time

period of the auxiliary switch, T, would be calculated by

321 TTTT ++≥

26

Thus, T is a function of the load current and the value of the resonant components. For

getting the exact time sequence, the resonant inductor and capacitor values have to be

selected. The first component to be designed is the resonant capacitor. This capacitor

forms a part of the resonant circuit during turn-on and also acts as a lossless snubber

during turn-off. During turn-off, the value of the capacitance is inversely proportional to

the rate of rise of the switch voltage. This in turn reduces the turn-off losses. This implies

that we need to select a very high value of capacitance but as the capacitance increases,

there is more and more energy stored in it. This energy would be discharged during turn-

on and thus adds to the turn-on losses. Thus an optimum value of the capacitance has to

be chosen which would reduce the turn-off losses, while not affecting the turn-on

adversely.

The DC rail in this experimental setup was decided to be 165 V and the switches are to be

designed for 8 A continuous current. By trying different values of capacitance and by

judging the performance, a value of 22nF is chosen. This value is big enough to reduce

the turn-off losses significantly and is small enough not to adversely affect the turn-on.

After selecting this value, the selection of the resonant inductor depends upon the

allowable peak current through it. Allowing for a peak current of 20 A, we get a value of

13.75 for Zr. Given the value of the resonant capacitance, 22nF, this translates to a

resonant inductance of 4.16µH. With these values, the resonant time, T2, is 0.95µs. Thus,

the different time periods during the resonant cycle are as thus:

T1 = 0.2µs

T2 = 0.95µs

T3 = 0.2µs

27

Thus T has to be greater than 1.35µs. All the resonant components have thus been

designed.

3.4 Simulation

The proposed topology is verified by simulating the single-phase operation in PSpice.

Simulation is done using real physical models of the off-the-shelf components. Figure

shows the simulation results of a hard-switched inverter.

Fig3.10 Gate and switch voltage during turn-on under hard switching

Fig 3.10 shows the gate voltage and the voltage across the switch (switch voltage) during

turn-on, under hard switching condition. The switch voltage begins to fall only after the

gate signal is applied and this leads to losses. Fig 3.11 shows the voltage across the

switch and the current through the switch during the same switching period. It shows the

voltage and current overlap during the switching interval. The extent of this overlap

determines the switching losses during this transition. Fig 3.12 shows the corresponding

waveforms during turn-off. As the switching frequency increases, the switching losses

become a major part of the overall losses and thus the efficiency of the system decreases

28

considerably. The proposed topology would considerably decrease these switching losses

by reducing the voltage-current overlap during these switchings.

Fig 3.11 Switch voltage and current during turn-on under hard switching

Fig 3.12 Switch voltage and current during turn-off under hard switching

The following figures show the different waveforms utilizing soft switching. As

mentioned earlier, an auxiliary resonant branch is used to create a zero voltage turn-on

for the main switches. Fig 3.13 shows the gate voltages of the main and the auxiliary

29

switch. The time difference between these two signals was calculated in the last section

and it is equal to T1 + T2. For the given case, the value was found to be 1.15µs.

Fig 3.13 Gate voltage for the main and the auxiliary switches

The auxiliary pulse has to be greater than 1.35µs and it has been fixed at 2µs in this case.

Fig 3.14 shows the main switch gate voltage and the main switch drain-to-source voltage

during turn-on.

30

Fig 3.14 Gate and switch voltage during turn-on under soft switching

In this case, the voltage across the switch begins to decrease and is very close to zero

before the gate voltage is applied. Thus the switch is turned on at near zero voltage

condition. Fig 3.15 shows the voltage across the switch and the current through it, for the

same switching period.

Fig 3.15 Switch voltage and current during turn-on under soft switching

Here, the voltage current overlap is very small and thus the switching loss is less,

compared to the hard switching case. Fig 3.16 shows the waveforms during turn-off.

31

Fig 3.16 Switch voltage and current during turn-off under soft switching

The voltage-current overlap here is considerably smaller than in the hard switching case.

Thus, the turn-off switching loss is much lower with soft switching.

Fig 3.17. Switch voltage and resonant inductor current during turn-on

Figure 3.17 shows the voltage across the switch and the resonant inductor current. The

timing sequence in this soft-switching circuit is very important. If it is not adjusted

properly, the switching losses would not be minimized.

32

Fig 3.18 Waveforms with incorrect timing sequence

Fig 3.18 shows the waveforms with incorrect timing sequence. Here, the voltage starts to

built up again and there would be considerable voltage-current overlap. This would lead

to higher switching loss than with correct timing sequence. Thus it is essential that the

inverter has the right timing sequence.

3.5 Control Sequence

To verify the effectiveness of the proposed soft-switching inverter, the scope of this

research included running the SRM with the inverter. To determine the control sequence

for the inverter required to run this three-phase motor, the operation of the three phase

SRM is looked into first. The motor being used in this experimental setup is a 12/8 SRM.

It has 12 stator poles and 8 stator poles.

The simplest way to run an SRM motor is to run it open loop with voltage chopping

[9,16]. Figure 3.19 shows the waveforms during voltage chopping. In this scheme, the

voltage applied across the motor inductance is switched between +VS and –VS. This

chopping frequency is fixed at 20 kHz. We need a high switching frequency to reduce the

33

torque ripple. As the torque ripple is one of the major issues in SRM drives, a high

switching frequency would be useful. To achieve this kind of chopping with the inverter

being used in this research, both the switches of the phase are switched together. When

they are conducting, the DC bus voltage, VS, is applied across the motor inductance.

When they are off, the freewheeling diodes conduct and thus the negative DC bus voltage

is applied across the motor inductance. Here, there is lower current at the start of overlap

between the stator and rotor poles. This, along with repeated short freewheeling periods,

will have less mechanical impact on the motor than the current chopping method.

Unaligned Position

Aligned PositionIdealized Inductance Profile

Voltage Chopping

VS

-VS

Current

on off

Fig 3.19 Voltage chopping waveforms

34

The next step in designing the control sequence is to determine the relationship between

the required speed and the firing sequence of the different phases.

15

Phase A Phase B Phase C

Fig 3.20 Phase inductance sequence

As the stator has 12 poles, the mechanical phase shift angle between the inductance

profiles of two consecutive phases is 15o. Thus the phases should be fired 15 mechanical

degrees apart. To achieve a particular speed, this mechanical phase shift would translate

into certain time shift. If Tp is the time difference between firing of two consecutive

phases, then there are 2415

360 = firings per one mechanical revolution of the rotor and

this translates to 24*Tp seconds. Thus the motor speed would be )24(

1

PT∗revolutions per

second (rps). This translates to 60)24(

1 ∗∗ PT

revolutions per minute (rpm). This

particular design is made to achieve a motor speed of 75 rpm. Solving for the value of Tp,

we get Tp=33.3ms.

33.3ms100ms

Phase APulse

Phase BPulse

Phase CPulse

Phase APulse

Fig 3.21 Phase pulse sequence

35

Thus the pulses for consecutive phases are time shifted by 33.3ms and the entire

waveform is periodic with a period equal to 100ms.

This rotor speed is realized by exciting the stator phases at a frequency of 10 Hz. We

need a switching frequency of 20 kHz for the inverter to get an efficient powerstage. This

is achieved by chopping the pulse for each phase at a frequency of 20 kHz.

Thus by giving the pulses in the above sequence, the motor can be run at 75 rpm with an

inverter have a switching frequency of 20 kHz. Also, the width of each pulse has to be

determined. The flux built up, when the pulse is applied, has to be brought down to zero

before the inductance begins to fall. This is to prevent production of negative torque. In

the voltage-chopping mode, negative voltage is applied when the switches are off and

thus the de-fluxing operation is done very rapidly. Thus we can use almost the entire

period of rising inductance for switching the phase on. To allow for certain physical

delays, a certain time lag is incorporated. The final pulse width of each pulse is fixed at

30ms with a gap of 3ms between pulses for consecutive phases.

30m

33.3m

Fig 3.22 Phase sequence with high frequency chopping

The inverter is operated in the above control sequence in order to run the motor at 75

rpm, with the inverter switching at 20 kHz.

36

4 Hardware Implementation

4.1 Setup

The overall setup of this system consists of the control board, the gate drivers for the

inverter switches, the inverter power-stage, the SRM and the interconnections.

SRMSoft-switching

Inverter

Control Board

GateDrivers

Fig 4.1 Proposed SRM Drive System

The control board generates the control logic signals required to run the motor in the way

described in chapter 3. There are four outputs, one each for each phase leg of the inverter

and one for the auxiliary switch. These in turn would help control the inverter in order to

get the motor running at the required speed. The pulses from this control board are fed to

the gate drivers, which amplify the signal to the levels required for switching the inverter.

The output of these gate drivers is directly fed to the inverter switches. The current output

37

from the inverter is fed to the motor. Thus, the controlled current output from the inverter

is used to run the motor at the required speed. The following sections describe the

hardware implementation of each of these stages.

4.2 Power Stage

The first step in designing the power stage is to select the power semiconductor devices.

This inverter consists of six main switches, six freewheeling diodes, one auxiliary switch

and six auxiliary diodes. The input to the system is fixed at 165V DC and system is to be

designed for an average load current of 8A. IRFP360, a 400V and 23A power MOSFET

was chosen as the main switching device for the inverter. To realize the freewheeling

diode, a 600V, 30A, hyperfast diode, RHRG3060, is chosen.

The peak resonant branch current is designed to be 20 A. The auxiliary switch used in the

setup is the same as the main switch, i.e., IRFP360. For the auxiliary diode, an ultrafast

500V, 4A rectifier, MUR450, is used.

Apart from the above devices, a 22nF capacitor and a 4.2 µH inductor form a part of the

auxiliary resonant circuit. A 22nF, 600V polypropylene film capacitor is connected

across all the main devices. The resonant inductor is made by using a MPP core,

55353A2. 14 turns were used to get the required inductance. Furthermore, to reduce the

reverse recovery problem of the diode, a saturable inductor is placed in series with the

resonant inductor. This would suppress the current ringing during the switching

transitions.

All the devices are connected on the heat sink and the interconnections are made on a

PCB. A low frequency 1000µF electrolytic capacitor and a high frequency 1µF

polypropylene film capacitor are connected across the DC rail.

38

4.3 Gate Drivers

The gate drivers get the signal pulses from the control board and amplify them to the

level required for switching the power MOSFETs. The MOSFET’s used in this setup

have an input capacitance of 4nF and thus the driving capability required from the gate

drivers is not too large. The designed gate driver board consists of two parts. The first one

being the input buffer and the second one being the gate driver. The input buffer is

required to provide high impedance for the input control signal. It is also used to boost

the current, so that sufficient current is available to the gate driver circuit. The input

buffer was implemented by using a hex inverter, 74ACT11004. It has high input

impedance and 24mA output drive current capability. As this chip has six hex inverters,

each board was designed to have two gate drivers, one for each switch of a phase. Fig 4.2

shows the block diagram of the gate driver board.

Input Buffer

Gate Driver forupper switch

Gate Driver forlower switch

To upperMOSFET

To lowerMOSFET

Control Signal 1

Control Signal 2

Fig 4.2 Block diagram of the gate driver board

The output of the gate driver is connected across the gate and source of the power

MOSFET. The source terminal of the upper MOSFET is floating and thus it can either be

at 0V or at 165V. As this is connected to the gate driver ground, this floating ground

would generate lot of common mode noise. This would interfere with the normal

39

operation of the circuit and it might malfunction. To avoid this situation, the ground of

each gate driver output is isolated from the grounds of the other gate driver and also from

the input stage ground. The input-output isolation is achieved by using an opto-coupler to

transfer the control signal from the input buffer stage to the gate driver stage. Further, an

isolated DC/DC converter ensures that the grounds of each gate driver circuit are isolated

from the other.

2

3

5V G5-15V G 15V

NMA0515SH

CPL

3120

8

7

6

5

To MOSFETGate terminal

To MOSFETSource terminal

180

10

Isolated Grounds

Control Signal

5V

Gnd

Input Buffer

Fig 4.3 Gate driver circuit for a single MOSFET

Fig 4.3 shows the gate driver circuit for a single MOSFET. The input buffer state is made

up of hex inverters and a current limiting resistor. The output current of this buffer is

24mA. An opto-coupled gate driver, HCPL3120, is used to implement the gate drive

circuit. This gate driver provides a minimum peak output current of 2A. This current

capability is good enough to drive the MOSFET being used. It also isolates the input

signal from the output signal and thus common mode noise is reduced.

A MOSFET needs +15V for turn-on and –15V for turn-off. The input to the gate driver

board is 5V. To get the required ±15V, we need a DC/DC converter. Further, it has to be

isolated to avoid common mode noise. This function is achieved by using an isolated,

40

dual output, 1 Watt DC/DC converter, NMA0515S. For further reduction of noise

problems, a ground plane is used for each individual circuit. An external resistance of

10Ω is placed in series between the gate driver output and the gate terminal. This resistor

helps to determine the rise and fall times of the gate pulse. Fig 4.4 shows a typical output

from the gate driver circuit.

+15V

-15V

GND

Fig 4.4 Typical output from the gate driver

4.4 Control Board

The control board should generate pulses as shown in the figure 3.22.

41

DelayCircuits

HighFrequency

SignalGenerator

AuxiliarySignal

Generator

MainSignal

Generator

ORGATE

Input signal fromfunction generator(Low Frequency)

High Frequency(Chopping) signal

Auxiliary Signal

MainSignal

Fig 4.5 Block diagram of the control board

Fig 4.5 shows the block diagram of the control board. There are two input signals to the

control board. The first one (input 1) is the low frequency signal, which determines the

speed of the motor. The second input (input 2) is the high frequency signal, which

determines the switching frequency of the inverter. Both the inputs are got from function

generators. Input 1 is given to the delay circuits to get three output signals, each phase-

shifted by 120ο from the other. These signals are then combined with input 2 by using an

AND gate. The output from this AND gate is then given to two different blocks. The first

block would create the gate pulses for the auxiliary switch and the second block would

create gate pulses for the main switches.

42

30ms100ms

Fig 4.6 Low frequency input-1.

Fig 4.6 shows the low frequency input, Input 1. It has a frequency of 10 Hz and a duty

cycle of 30 percent. This would give the pulse required for phase A of the inverter. In

order to get the pulses for phase B and C, a delay block is used. This block is realized by

using “one-shot” monostable multivibrator. CD4528BC is a dual monostable

multivibrator.

Input4

_Q

1 2

VDD

12 Q

15 14

VDD

RX1

CX1

RX2

CX2

Delayed Output

Fig 4.7 Dual Monostable used for getting a delay

Input 1 is applied to the first “one-shot”. It is programmed to be triggered by the rising

edge of the input and this would give an output pulse of a specified width. Externally

connected Rx1 and Cx1 specify this width. This width was adjusted to be 33.3ms, as per

the system requirements. This pulse is then applied as an input to the second “one-shot”

and it is triggered by the rising edge of this waveform. The output pulse width is adjusted

43

to be of the same width as that of the original input pulse width i.e., 30ms. Thus,

effectively, we have a pulse of frequency 10Hz and duty cycle 30 percent, which has

been delayed by 33.3ms.

3.3ms

3ms

3ms

Input

Output of first “one-shot”

Output

Fig 4.8 Phase Delay using “one-shot”

Fig 4.8 shows the waveforms of the delay block. The output of this would be the pulse

required for phase B. To get the pulse for phase C, the phase B pulse is sent through a

dual “one-shot” again. Thus we have three pulses, one for each phase, phase-shifted by

120ο. Now, if this signal were applied to the inverter, it would make the inverter switch at

a very low frequency (10 Hz). This would result in bulky magnetic components, higher

harmonics, higher torque ripple and other effects, which are not preferable. Thus the

switching frequency should be increased, while keeping the motor speed at the same

value. This is achieved by combining the above pulses with a high frequency waveform,

by means of an AND gate. A Quad two input AND gate (74LS08) is used for this

purpose.

44

33.3ms100ms

Phase APulse

Phase BPulse

Phase CPulse

Phase APulse

Fig 4.9 Sequence of pulses after the delay stage

The switching frequency for this system was decided to be 20 kHz. Fig 4.10shows the

output of the AND stage. Here, the switching frequency is 20 kHz but the frequency at

which the phases are excited still remains 10 Hz.

30m

33.3m

Phase A Phase C Phase C

Fig 4.10Sequence of pulses with high frequency switching

Now, in order to realize soft-switching, the above pulses are sent through two more

blocks. The first block is for generating pulses for the main switches and the second one

is for generating pulses for the auxiliary switch. For realizing soft switching, the auxiliary

switch should be turned on before the main switch. The rising edges of the output

waveform from the AND gate trigger the auxiliary gate signal generator circuit. This

generates the gate signal for the auxiliary switch. A “one-shot” monostable multivibrator

(CD4528BC) is used to generate this pulse. The pulse width is adjusted by controlling the

externally connected resistor and capacitor. For this system, the pulse width was set for

45

1.15µs. An R-C circuit is utilized to generate the necessary delay for generating the gate

signals for the main switches. As an R-C delay would not produce a sharp rising or

falling edge, the output from this stage is passed through two schmitt triggered inverters.

By adjusting the Rdelay and Cdelay values, the required delay can be achieved. A delay of

2µs was achieved in this way.

Input Delayed OutputRdelay

Cdelay

Fig 4.11 Delayed signal for the main switches

50us

Input

2us

50us

Auxiliary Gate Signal

Main Switch Gate Signal

1.15us

Fig 4.12 Gate signals for the main and auxiliary switch

46

While the logical OR of the three auxiliary signals is sent to the gate driver, the output

from the main switch gate signal generator circuit is directly fed to the gate drivers. The

logical OR function is realized by using a triple 3-input OR gate (MC14075B).

Aux Gate Signal

Main Gate Signal

Fig 4.13 Experimental auxiliary and main gate signals

Fig 4.13 shows the experimental waveforms showing the time delay between the pulses

for the auxiliary switch and main switch. Fig 4.14 shows the experimental waveforms of

the phase sequence. These pulses are the output from the control board, which are then

applied to gate drivers.

All these independent systems were connected together and experiments were conducted.

The next chapter presents the various waveforms obtained during the experimental

verification of this drive system

47

Phase A Phase B

Phase C

Fig 4.14 Motoring sequence of the phases

.

48

5 Results

5.1 Switching Transitions

5.1.1 Hard Switching

The first test conducted was to operate the inverter under hard-switching. The turn-on and

turn-off waveforms are captured. Fig 5.1 shows the main gate signal and voltage across

the switch during turn-on.

Voltage across Switch

Gate Voltage

100 V/div

20 V/div Time base0.2 µs/div

Fig 5.1 Gate voltage and voltage across the switch during turn-on

As seen in the Fig 5.1, the voltage across the switch begins to fall only after the gate

voltage is applied. Fig 5.2 shows switch voltage and current overlap during the transition.

It can also be seen that there is a lot of ringing in the switch current during this transition.

This is due to the reverse recovery problem of the freewheeling diodes. Also, there is a

considerable overlap between the voltage and current waveforms during this switching.

49

This gives a measure of the switching loss. Thus, each switching transition results in

considerable switching loss.

Switch Voltage100 V/div

Average Switch Current5 A/div

Time base0.2 µs/div

Fig 5.2 Switch voltage and current waveforms during turn-on

Gate Voltage20 V/div

Switch Voltage100 V/div Time base

0.5 µs/div

Fig 5.3 Gate and switch voltage waveforms during turn-off.

50

Figures 5.3 and 5.4 show the corresponding hard-switching waveforms during turn-off.

Average switch current5 A/div

Switch voltage100 V/div Time base

0.5 µs/div

Fig 5.4 Switch Current and voltage overlap during turn-off

As can be seen, there is considerable switch current and switch voltage overlap during

turn-off also. This is because the rate of rise of the voltage across the switch is high and

this leads to higher current-voltage overlap. The turn-on and turn-off switching losses

together constitute a large part of the total losses in the inverter. Soft switching attempts

to reduce these losses.

5.1.2 Soft Switching

The next test done was to operate the inverter under soft switching. The proposed soft-

switching scheme achieves near zero voltage turn-on and reduces the turn-off losses by

using a snubber capacitor. Fig 5.5 shows the gate and switch voltage during turn-on.

51

Switch Voltage50 V/div

Gate voltage20 V/div

Time base1 s/div

Fig 5.5 Gate and switch voltage during turn-on under soft switching

Gate Voltage20 V/div

Switch Voltage50 V/div

Resonant current5 A/div

Aux Gate Voltage

Time base1 s/div

Fig 5.6 Resonant inductor current during turn-on

The voltage across the switch resonates and is close to zero when positive gate voltage is

applied. Thus it achieves near zero voltage turn-on. The proposed topology, with fixed

52

timing, cannot achieve exact zero voltage switching though it reduces the turn-on losses

considerably.

Fig 5.6 shows the resonant inductor current during this switching transition. The resonant

inductor current builds up linearly to the load current value, resonates and then falls

linearly after the resonant switch is turned off. During turn-off process, this inductor

current has a lot of ringing due to the auxiliary diode reverse recovery. A saturable

inductor was placed in series with the resonant inductor to suppress this ringing.

Six turns on a metglass core was used to realize the saturable inductor. The core and the

number of turns were decided after some initial tests. This helped to suppress the ringing,

though it was not completely eliminated.

Resonant current5 A/div

Aux Gate Voltage

Switch Voltage50 V/div

Gate Voltage20 V/div

Time base1 s/div

Fig 5.7 Waveforms with a saturable inductor

Fig 5.8 shows the switch current during turn-on. Due to the difficulty of isolating the

current flowing through the switch, the waveform includes the current flowing through

the snubber capacitor connected across the switch as well.

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Switch voltage50 V/div

Switch Current5 A/div

Time base1 s/div

Fig 5.8 Switch voltage and current during turn-on soft switching

It can be seen that there is considerably less overlap in these waveforms and thus the

turn-on loss is reduced.

Figures 5.9 and 5.10 show the relevant waveforms during turn-off under soft switching.

As can be seen, the capacitor across the device acts as a snubber and this reduces the rate

of rise of voltage. Thus the extent of overlap between the current and voltage is reduced

and hence, there is lower turn-off loss.

Apart from the MOSFETs, the freewheeling diodes also experience a zero current turn-

off in this topology. This eliminates the reverse recovery problem of the freewheeling

diodes. The resonant switch and diodes turn off under zero current condition as well and

thus the switching loss in the resonant branch is also reduced.

Thus, the overall switching loss in the soft switching topology is considerably less than

the hard switching scheme.

54

Gate Voltage20 V/div

Switch Voltage50 V/div

Time base1 s/div

Fig 5.9 Gate and switch voltage during turn-off under soft switching

Switch voltage50 V/div

Switch current5 A/div

Time base1 s/div

Fig 5.10 Switch voltage and current during turn-off under soft switching

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5.2 Inverter Operation with Inductive Load

The pulses from the control board operate the three-phase inverter. This section presents

the output current waveforms of the inverter. Fig 5.11 shows the output current waveform

of the inverter with an inductive load.

Output Current0.2 A/div

Time base10 s/div

Switch voltage

Gate voltage

Fig 5.11 Output current with an inductive load

Here, the main switches are turned on and the DC rail voltage is applied across the

inductor. Consequently, the output current rises. When the switch is off, the freewheeling

diodes carry the current and the negative DC rail voltage is applied across the inductor.

As a result, the inductor current falls linearly.

The phase A is switched on for 30ms and the current builds up during this interval. This

output current is shown in figure 5.12 . We can see that the current increases while the

pulse is on. The rate of rise of this current is controlled by the chopping duty cycle. The

duty cycle was adjusted to give the required current output.

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Output phase current5 A/div

Phase A pulse50 V/div

Aux Switch pulse20 V/div

Time base20 ms/div

Fig 5.12 Output phase current with a inductive load

Output phase current5 A/div

Time base20 ms/div

Fig 5.13 Output phase current with RL load hard under hard switching

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5.3 Inverter Operation with RL Load

The inverter was then run with an RL load to simulate the motor.

Average output phase current5 A/div

Time base20 ms/div

Fig 5.14 Average output current waveform with RL load under hard switching

Input current2 A/div

Time base10 ms/div

Fig 5.15 Input current waveform with RL load under hard switching

58

Figures 5.13 to 5.20 show the output current waveforms under both hard switching and

soft switching conditions.

Average Input current2 A/div

Time base10 ms/div

Fig 5.16Average input current waveform with RL load under hard switching

Output phase current5 A/div

Time base50 ms/div

Fig 5.17 Output phase current with RL load under soft-switching

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Average output phase current5 A/div

Time base50 ms/div

Fig 5.18 Average output current with RL load under soft switching

Input current5 A/div

Time base20 ms/div

Fig 5.19 Input current with RL load under soft switching

60

Average input current5 A/div

Time base20 ms/div

Fig 5.20 Average input current with RL load under soft switching

It was noticed that there was less noise in the soft-switching case.

5.4 Inverter Operation with the motor

The three-phase SRM was run using this inverter. The motor is connected as the three

phase load for the inverter. The difference between the RL load and the motor load is that

the inductance of the motor changes with the position of the rotor. Thus motor load is

effectively a variable RL load. In this setup, an RL load was put in parallel with the

motor load in order to test the inverter for higher power outputs. The output and input

current waveforms are shown here, corresponding to both the soft-switching and the

hard-switching cases. It was noticed that there was less noise in the soft switching case.

This was noticeable by comparing the fluctuations in the input power magnitude for any

output power value. The inverter efficiencies are presented in the next section.

61

Output current0.5 A/div

Time base5 ms/div

Fig 5.21 Output phase current with a motor load alone

Fig 5.21 shows the output current waveform when the inverter had only the motor load.

All the other waveforms has a RL load in parallel with the motor load.

Input current2 A/div

Time base20 ms/div

Fig 5.22 Input current with motor load under hard switching

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Average input current2 A/div

Time base20 ms/div

Fig 5.23 Average input current with motor load under hard switching

Output phase current5 A/div

Time base50 ms/div

Fig 5.24 Output phase current with motor load under hard switching

63

Average output phase current5 A/div

Time base50 ms/div

Fig 5.25 Average output phase current with motor load under hard switching

Output phase current5 A/div

Time base50 ms/div

Fig 5.26 Output phase current with motor load under soft switching

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Average output phase current5 A/div

Time base50 ms/div

Fig 5.27 Average output phase current with motor load under soft switching

Input current2 A/div

Time base20 ms/div

Fig 5.28 Input current with motor load under soft switching

65

Average input current2 A/div

Time base20 ms/div

Fig 5.29 Average input current with motor load under soft switching

5.5 Inverter Efficiency

The inverter was operated at different output powers with both the RL load and motor

load. The input and output power of the inverter were measured. A three phase power

analyzer was used to measure the output power. The efficiencies were calculated. Fig

5.29 gives the plot comparing the efficiencies at different power outputs with an RL load.

The efficiencies calculated here have a margin of error, as the output wattage was not

constant while making these measurements. The average output wattage was taken into

consideration. There is about 0.5-4 % margin of error in these measurements.

It is seen that the efficiency of the inverter improves under the soft switching case.

Though the improvement is not significant at lower power outputs, there is significant

66

improvement in efficiency at higher power outputs. The efficiency of the soft-switching

inverter saturates at 96.5 percent. The inverter is tested for output wattage of up to 300

watts.

Inverter Efficiency with RL Load

70

75

80

85

90

95

100

0 100 200 300 400

Output Power

Eff

icie

ncy

Hard Switching

Soft Switching

Fig 5.30 Efficiencies of the inverter with RL load

Inverter Efficiency with Motor

75

80

85

90

95

100

0 100 200 300 400 500

Output Power

Eff

icie

ncy

Hard Switching

Soft Switching

Fig 5.31 Efficiencies of the inverter while running the motor

67

The inverter was then used to drive the motor and a RL load in parallel and the efficiency

in the two cases was calculated. Fig 5.30 shows the comparative efficiencies of the

inverter while running the motor.

In this case also, the efficiency of the inverter was found to be better in the soft switching

case. The inverter efficiency saturates at 96.1 percent in the soft switching case. The

inverter was tested for output power up to 400 watts.

Thus, the proposed soft switching topology was found to be effective in reducing the

switching losses and hence, in increasing the efficiency of the inverter.

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6 Conclusions and Future Work

6.1 Conclusions

In this thesis, we proposed and implemented a novel soft switching inverter topology for

a switched reluctance motor drive. The operating principle of the SRM was described and

the research being done in the field of SRM inverters was discussed. The scarcity of

research in the field of soft switching inverters for SRM motors was identified. A novel

soft-switching topology was presented and its principle of operation was explained.

Various components of this inverter were designed. The hardware implementation of all

the relevant subsystems was presented. To verify the functionality of the inverter, it was

used to run a three-phase, 12/8 SRM. All the relevant waveforms were captured and the

efficiency of the inverter was calculated under various loads and under different

switching schemes. The following observations were made:

• A near zero voltage turn-on was achieved for the main switches.

• Turn-off losses were reduced by using the snubber capacitor.

• Freewheeling diodes turned off under zero current condition and this greatly reduced

the reverse recovery problem of the diodes.

• Auxiliary switch turns off under zero current condition.

• Auxiliary diodes turn off under zero current condition.

• Due to all the above effects, the switching losses are considerably reduced.

• Soft switching results in considerably less noise than in the hard switching case

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• An improvement in efficiency of the inverter was observed in the soft switching case.

This was true for all types of loads used in this setup, namely inductive load, RL load

and the SRM motor.

Hence, the proposed topology has been successfully implemented and its effectiveness

has been verified.

6.2 Future Work

One issue that was not looked into in this research was the condition when there is

overlap between the phase currents. As the three phases share one auxiliary switch, there

might be some complications when there is current overlap and consequent firing of two

phases together. If there are unwanted complications, the soft-switching leg can be

disabled during this overlap period. This way, we loose soft switching condition during

this overlap but the switching losses are still reduced as the time of overlap is still small

compared to the total time period.

In order to achieve a controlled torque output from the SRM, a closed loop control

system can be implemented. A digital controller can be designed to realize the above

function. The shaft position can be fed back to this controller and the firing of the phases

can be done accordingly. Speed control can also be incorporated.

One of the major problems in SRM drives is the high torque ripple. Any work done to

minimize this torque ripple would be interesting and challenging. Furthermore, the effect

of the proposed soft switching topology on torque ripple and the EMI can be studied.

70

References

[1] Byeong-Mun Song, Jason Lai, Dayu Qu, Huijie Yu, Ho-Kyeong Sung, “A novel soft-

switching chopper using auxiliary resonant snubbers for a MAGLEV system”, VPEC

seminar, Blacksburg, VA, Sept. 1998.

[2] Byeong-Mun Song, Jason Lai, “ A novel two-quadrant soft-switching converter with

one auxiliary switch for high power applications”, to be presented in IEEE Industrial

Applications Society conference, Phoenix, AZ, 1999.

[3] Huijie Yu, Byeong-Mun Song, Jason Lai, “Design of a novel ZVT soft-switching

chopper”, Conference Recordings, IEEE Power Electronics Specialists Conference, 1999,

pp. 287-292.

[4] J. S. Lai, R. W. Young, G. W. Ott, J. W. Mckeever, F. Z. Peng, “A delta configured

auxiliary resonant snubber inverter”, IEEE Transactions on Industrial Applications,

Vol.32, No.3, May/Jun. 1996, pp518-525.

[5] D. M. Divan, “The resonant DC link converter--- A new concept in static power

conversion”, Conference Recordings. IEEE IAS Annual Mtg., Oct. 1986, pp. 648-656.

[6] J. S. Lai, “Fundamentals of a new family of auxiliary resonant snubber inverter”,

IEEE Transactions on Industrial Applications, Vol.32, No. 3, May/June 1996, pp.518-

523.

[7] J. S. Lai, “Practical design methodology of auxiliary resonant snubber inverters”,

IEEE Power Electronics Specialists Conference, Italy, July 1996, pp.432-437.

[8] Yuqing Tang, “High power inverter EMI characterization and improvement using

auxiliary resonant snubber inverter”, Master’s thesis, VPISU, Dec. 1998.

71

[9] T. J. E. Miller, Switched reluctance motor and their control, Magna physics

publication, Oxford press, 1993.

[10] Slobodan Vukosavic, Victor R. Stefanovic, “ SRM inverter topologies: A

comparative evaluation”, IEEE Transactions on Industry Applications, Vol.27, No.6,

Nov/Dec. 1991.

[11] T. J. E. Miller, “Converter volt-ampere requirements of the switched reluctance

motor drive”, IEEE Transactions on Industry Applications Vol.IA-21, No.5, Sept/Oct.

1985.

[12] Mehrad Ehsani, James T. Bass, T. J. E. Miller, Robert L. Steigerwald, “Development

of a unipolar converter for variable reluctance motor drives”, IEEE Transactions on

Industry Applications, Vol.IA-23, No.3, May/June 1987.

[13] T. W. Ching, K. T. Chau, C. C. Chan, “A new zero-voltage-transition converter for

switched reluctance motor drives”.

[14] Jung G. Cho, Won H. Kim, Dong W. Yoo, Geun H. Rim, “Reluctance motor

drives”.

[15] Y. Murai, J. Cheng, M.Yoshida, “A soft-switched reluctance motor drive circuit with

improved performances”.

[16] J. T. Bass, Mehrad Ehsani, T. J. E. Miller, “Robust torque control of switched

reluctance motors without a shaft-position sensor”, IEEE Transactions on Industrial

Electronics, Vol. IE-33, No.3, August 1986, pp.212-216.

72

Appendix

Fig A.1 The control board

73

Fig A.2 Gate driver board

74

Fig A.3 Power stage

75

Fig A.4 Three-phase SRM

76

Motor Information

The motor used in this set is a three phase, 12/8 Switched Reluctance Motor (SRM). It

has 12 stator poles and 8 rotor poles. It is wound as a three-phase motor and each phase

circuit comprises single-tooth coils wound on one set of four stator poles, 90 mechanical

degrees apart. Six leads are brought out to the terminal block and they are labeled C+, B+,

A+, A-, B- and C-. There are no internal connections between the phases.

The resistance between any pair of phase terminals is about 2 ohms. This measurement is

at normal lab temperature, i.e., 23ο C. The aligned inductance of a phase is about 49 mH

and the unaligned inductance of the phase is about 10 mH.

This motor is generally operated from a conventional six-switch, six-diode converter

(“classic converter”). To get an output power of about one-half horsepower, the motor

has to be run between 700 rpm and 11,000 rpm. With an input voltage of 165V DC to the

converter, this power output converts to no more than 8 A peak current in the phase at

any instant.

The machine has a built in optical position encoder. This is a three-pin encoder with only

one output signal.

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VITA

Naveen Yadlapalli was born on May 7th, 1974 in Hyderabad, India. He did all his

schooling in Hyderabad. He completed his Bachelor of Technology in Electrical and

Electronics Engineering from Jawaharlal Nehru Technological University, Hyderabad.

He joined Virginia Tech in Spring 97 and joined VPEC in summer ‘97. His primary

interest is in the area of Power Electronics and Motor Drives. He would be joining

Motorola Lighting Inc as a design engineer after his graduation.