CMOS WAFER PREPARATION BEFORE BONDING...DE TAPING CMP / Cleanroom (100) ADC Si substrate (> 700 µm)...
124
Forum Be Flexible 2012, Munich, Nov 21st CMOS WAFER PREPARATION BEFORE BONDING
Transcript of CMOS WAFER PREPARATION BEFORE BONDING...DE TAPING CMP / Cleanroom (100) ADC Si substrate (> 700 µm)...
Forum Be Flexible 2012, Munich, Nov 21st
CMOS WAFER PREPARATION
BEFORE BONDING
Contents
• Rockwood wafer services
• Context – Customer’s outsourcing
– Rockwood thinning flow
• Learning curve – Yield loss
– Breakages
– Ruling polishing pad lifespan
• Cases study – Investigating process issues
– Microvoids
– Tape waviness transfer
2
ROCKWOOD WAFER
SERVICES
3
Rockwood Wafer Services
4
Rockwood Wafer Services
• Part of Rockwood Specialties Inc - A 4B$ US Listed Company
5
Rockwood Wafer Services
• Part of Rockwood Specialties Inc - A 4B$ US Listed Company
• Located near Aix en Provence in France.
6
Rockwood Wafer Services
• Part of Rockwood Specialties Inc - A 4B$ US Listed Company
• Located near Aix en Provence in France.
• Diversified business in 2008 – from only reclaim activities
– to include Wafer Processing Services
– which is now making a significant contribution to our business.
7
Rockwood Wafer Services
• Part of Rockwood Specialties Inc - A 4B$ US Listed Company
• Located near Aix en Provence in France.
• Diversified business in 2008 – from only reclaim activities
– to include Wafer Processing Services
– which is now making a significant contribution to our business.
• Offering the following typical services – Thinning
• Pre Packaging Grinding
• SOI thinning.
• Wafer carriers
• Bonded wafers
• Taiko Grinding.
– Dicing (including DBG process)
– Wafer re-sizing.
– Wafer Edge trimming.
– Polishing and cleaning • DSP
• Bonding Surface preparation
– And soon Wafer Bonding.
8
CONTEXT
9
Context
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Processing of individual sensitive
wafers
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Processing of individual CMOS wafers
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
grinding,
polishing
cleaning
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
grinding,
polishing
cleaning
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
grinding,
polishing
cleaning
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
DIRECT BONDING
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
grinding,
polishing
cleaning
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
Context
• Customer’s outsourcing – Rockwood processes his customer ‘s CMOS wafers
– Further used to build sensor
Sensitive
Wafer
Prime Si
Wafer
grinding,
polishing
cleaning
Cu
sto
me
r’s
fab
(+
su
bco
ntr
ac
tors
)
CMOS wafer
Photodiode
wafer
CMOS wafer
Signal sensitive
wafer
Context
• Rockwood Thinning flow
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room ADC Si substrate (> 700 µm)
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 - 400 µm) + clean
2 steps: bulk + final polish
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
ADC Si substrate
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 - 400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
ADC Si substrate
ADC Si substrate
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 - 400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
ADC Si substrate
ADC Si substrate
ADC Si substrate
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 - 400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
ADC Si substrate
ADC Si substrate
ADC Si substrate
PACKING & SHIPPING
Context
• Rockwood Thinning flow INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
GRINDING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 - 400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
ADC Si substrate (> 700 µm)
ADC Si substrate (> 700 µm) To protect CMOS side & make the
handling safer
ADC Si substrate
The wafer is highly warped and the
surface damaged
ADC Si substrate
ADC Si substrate
ADC Si substrate
Next step: bonding on
customer’equipment PACKING & SHIPPING
LEARNING CURVE
Product yield, breakage yield
31
Learning
• Yield
Learning
• Yield – Customer’s data
Learning
• Yield – Customer’s data
– « Yield loss »= bad dies / total dies (per wafer, per batch)
Learning
• Yield – Customer’s data
– « Yield loss »= bad dies / total dies (per wafer, per batch)
– Overlay of C-SAM , electrical measurements, defect measurements
Learning
• Yield – Customer’s data
– « Yield loss »= bad dies / total dies (per wafer, per batch)
– Overlay of C-SAM , electrical measurements, defect measurements
0%
5%
10%
15%
20%
25%
30%
Dec 2010 - Feb 2011 Jan 2012 - Mar 2012
Quartile 1
Moyenne
Mediane
Min
Max
Quartile 3
Production ramp up phase 1 year later
Batch average Yield loss (range box)
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% 26% 28% 30%
Cu
mu
late
d %
in c
lass
Lot yield loss (%)
Dec 2010 - Feb 2011 Jan 2012 - Mar 2012
Learning
• Yield – Customer’s data
– « Yield loss »= bad dies / total dies (per wafer, per batch)
– Overlay of C-SAM , electrical measurements, defect measurements
Out of 3 production months during
ramp up phase
~ only 25% with yield loss < 10%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% 26% 28% 30%
Cu
mu
late
d %
in c
lass
Lot yield loss (%)
Dec 2010 - Feb 2011 Jan 2012 - Mar 2012
Learning
• Yield – Customer’s data
– « Yield loss »= bad dies / total dies (per wafer, per batch)
– Overlay of C-SAM , electrical measurements, defect measurements
Out of 3 production months during
ramp up phase
~ only 25% with yield loss < 10%
Out of 3 production months 1 year later
~95%
Learning curve
• Ruling pad lifespan
39
Learning curve
• Ruling pad lifespan
40
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
Learning curve
• Ruling pad lifespan
41
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
Learning curve
• Ruling pad lifespan
42
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
Step 1: bulk polishing
Defect removal,
Roughness ~nm
Step 2: Final polishing
Roughness ~A
Learning curve
• Ruling pad lifespan
43
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
Learning curve
• Ruling pad lifespan
44
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
T0: process set up and frozen with
qualification lots (few)
Learning curve
• Ruling pad lifespan
45
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
T0: process set up and frozen with
qualification lots (few)
Ramp up phase : what about lifespan of
consumables ?
Learning curve
• Ruling pad lifespan
46
INSPECTION – Thickness meas.
Final clean room
TAPING
Cleanroom 100
THINNING ( 200 - 400 µm)
Cleanroom 10000
2 steps: rough + fine wheel
POLISHING ( 200 -400 µm) + clean
2 steps: bulk + final polish
DE TAPING
CMP / Cleanroom (100)
FINAL CLEAN & INSPECTION
Final clean room (1 – 10)
T0: process set up and frozen with
qualification lots (few)
Ramp up phase : what about lifespan of
consumables ?
Technical driver: polishing quality vs time
Learning curve
Learning curve
• Ruling pad lifespan
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
-80%
-60%
-40%
-20%
0%
20%
40%
60%
80%
100%
-15 -10 -5 0 5 10 15 20
yie
ld l
oss
(a.
u.)
Pad lifetime (hrs from mid lifetime )
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
– And the winner is…pad lifespan on polishing step #2
Average yield loss
Mid
life
tim
e
Number of processed hours vs std reclaim lifespan
-80%
-60%
-40%
-20%
0%
20%
40%
60%
80%
100%
-15 -10 -5 0 5 10 15 20
yie
ld l
oss
(a.
u.)
Pad lifetime (hrs from mid lifetime )
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
– And the winner is…pad lifespan on polishing step #2
High degradation rate vs std
reclaim polishing process
Average yield loss
Mid
life
tim
e
Number of processed hours vs std reclaim lifespan
-80%
-60%
-40%
-20%
0%
20%
40%
60%
80%
100%
-15 -10 -5 0 5 10 15 20
yie
ld l
oss
(a.
u.)
Pad lifetime (hrs from mid lifetime )
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
– And the winner is…pad lifespan on polishing step #2
High degradation rate vs std
reclaim polishing process
More likely due to higher wearing
rate as caused by sharp edge of
thin wafers
Average yield loss
Mid
life
tim
e
Number of processed hours vs std reclaim lifespan
-80%
-60%
-40%
-20%
0%
20%
40%
60%
80%
100%
-15 -10 -5 0 5 10 15 20
yie
ld l
oss
(a.
u.)
Pad lifetime (hrs from mid lifetime )
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
– And the winner is…pad lifespan on polishing step #2
Average yield loss
Mid
life
tim
e
Number of processed hours vs std reclaim lifespan
-80%
-60%
-40%
-20%
0%
20%
40%
60%
80%
100%
-15 -10 -5 0 5 10 15 20
yie
ld l
oss
(a.
u.)
Pad lifetime (hrs from mid lifetime )
Learning curve
• Ruling pad lifespan – Plot of lot yield loss versus consumables information
• Polishing insert lifespan
• Polishing pad preparation conditions
• Polishing pad lifespan (pad step#1 & pad step #2)
• Etc..
– And the winner is…pad lifespan on polishing step #2
Average yield loss
Lim
it
Mid
life
tim
e
Number of processed hours vs std reclaim lifespan
CASES STUDY
Experimental data
59
INVESTIGATING PROCESS
ISSUES
Case study #1
60
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool – Quality alert from the customer (< 4 % of the production)
C-SAM map of the wafer
edge after bonding
Wafer
C SAM
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool – Quality alert from the customer (< 4 % of the production)
– Investigations
C-SAM map of the wafer
edge after bonding
Wafer
C SAM
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool – Quality alert from the customer (< 4 % of the production)
– Investigations
• Sometimes at the end of the polishing cycle the wafer stay
“sticked” onto the polishing pad, which is impregnated with slurry
• local chemical etching by the basic slurry: the pad groove pattern
is “printed” on the wafer
C-SAM map of the wafer
edge after bonding
Wafer
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
C SAM
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool – Quality alert from the customer (< 4 % of the production)
– Investigations
• Sometimes at the end of the polishing cycle the wafer stay
“sticked” onto the polishing pad, which is impregnated with slurry
• local chemical etching by the basic slurry: the pad groove pattern
is “printed” on the wafer
C-SAM map of the wafer
edge after bonding
Wafer
Equivalent pattern
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
C SAM
Case study #1: investigating process issues
• 1: wafer handling issue on
polishing tool – Quality alert from the customer (< 4 % of the production)
– Investigations
• Sometimes at the end of the polishing cycle the wafer stay
“sticked” onto the polishing pad, which is impregnated with slurry
• local chemical etching by the basic slurry: the pad groove pattern
is “printed” on the wafer
The problem has been fixed
Use of vacuum to hold the wafer
C-SAM map of the wafer
edge after bonding
Wafer
Equivalent pattern
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
28
WAFER
POLISHING PADPOLISHING PAD (impregnated with slurry)
Pad/ wafer contact (local etching)
No contact (no etching)
C SAM
MICROVOIDS
Case study #2
67
Case study #2: microvoids
Case study #2: microvoids
• Microvoids
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
– Small unbonded areas (<0,01 mm²)
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
– Small unbonded areas (<0,01 mm²)
– Preferably located at the edge of the wafer
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
– Small unbonded areas (<0,01 mm²)
– Preferably located at the edge of the wafer
– Major yield detractor: 1 microvoid 1 lost die
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
– Small unbonded areas (<0,01 mm²)
– Preferably located at the edge of the wafer
– Major yield detractor: 1 microvoid 1 lost die
• Characterization
Case study #2: microvoids
• Microvoids – Defect located at the bonding interface
– Small unbonded areas (<0,01 mm²)
– Preferably located at the edge of the wafer
– Major yield detractor: 1 microvoid 1 lost die
• Characterization – C-SAM & Mic
Case study #3: microvoids
• Characterization – Profilometry
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
• Debonding of the pair of wafers
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Sensitive wafer
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
• Debonding of the pair of wafers
• Profile on the CMOS wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Sensitive wafer
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
• Debonding of the pair of wafers
• Profile on the CMOS wafer
Crater like defect
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Sensitive wafer
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
• Debonding of the pair of wafers
• Profile on the CMOS wafer
Crater like defect
~ 100 µm wide,
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Sensitive wafer
Case study #3: microvoids
• Characterization – Profilometry
• Manufacturing of low adhesion bonded wafers
• Wafer mapping (microvoids localization)
• Debonding of the pair of wafers
• Profile on the CMOS wafer
Crater like defect
~ 100 µm wide,
~10nm depression /~6nm elevated ring
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Top view Side view
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
CMOS Wafer
SOI Wafer
Sensitive wafer
Case study #2: microvoids
• Microvoids counts vs process
deviations
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
CM
OS
PR
OC
ES
S
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
CM
OS
PR
OC
ES
S
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
CM
OS
PR
OC
ES
S
Case study #2: microvoids
Location of the final thin wafer into the original PRIME
wafers
Original PRIME wafer
Thin wafer
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
CM
OS
PR
OC
ES
S
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
CM
OS
PR
OC
ES
S
Case study #2: microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
CM
OS
PR
OC
ES
S
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
– Grinding amount
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
– Grinding amount
– Increased polishing removals
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
– Grinding amount
– Increased polishing removals
– Clean (modified cleaning/drying sequence)
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
– Grinding amount
– Increased polishing removals
– Clean (modified cleaning/drying sequence)
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
No clear trend:
uneven occurrence
of microvoids
• Microvoids counts vs process
deviations – Microvoids count = number of microvoids / wafer, batch
• DOE on PRIME wafers (still ongoing)
– Influence of the silicon raw material
• Depth variation
• Type of silicon (CZ, FZ)
– Thermal treatment (w, w/o)
– Grinding amount
– Increased polishing removals
– Clean (modified cleaning/drying sequence)
– Type of tape
CM
OS
PR
OC
ES
S
CM
OS
Th
inn
ing
Case study #2: microvoids
No clear trend:
uneven occurrence
of microvoids
No clear trend:
uneven occurrence
of microvoids
TAPE WAVINESS TRANSFER
Case study #3
100
Case study #3: tape waviness transfer
101
• Final visual inspection on thin wafers
Case study #3: tape waviness transfer
102
• Final visual inspection on thin wafers
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
103
• Final visual inspection on thin wafers
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
104
• Final visual inspection on thin wafers – Wafer warpage: lamp not straight but curved
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
105
• Final visual inspection on thin wafers – Wafer warpage: lamp not straight but curved
– Reflection is not mirror-like.
• small “waves” topography on the polished surface
• mostly random pattern
• with main direction
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
106
• Final visual inspection on thin wafers – Wafer warpage: lamp not straight but curved
– Reflection is not mirror-like.
• small “waves” topography on the polished surface
• mostly random pattern
• with main direction
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
107
• Final visual inspection on thin wafers – Wafer warpage: lamp not straight but curved
– Reflection is not mirror-like.
• small “waves” topography on the polished surface
• mostly random pattern
• with main direction
nm
mm
H
W
H= ~ 500 - 800 nm
W = 10 – 15 mm
W/H = 12 000 30 000
Profile
Thin wafer (thinned
side)
Case study #3: tape waviness transfer
• Investigation
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
Wafer
motion
Tape frame
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
Wafer
motion
Tape frame
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
Wafer
motion
Tape frame
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
– Demonstration • Virgin silicon wafers, 3 taping conditions
• Std thinning, inspection
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
– Demonstration • Virgin silicon wafers, 3 taping conditions
• Std thinning, inspection
Pressure roller
Wafer
motion
notch
Pattern direction
Hologenix – YIS 150
(light deflectivity)
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
– Demonstration • Virgin silicon wafers, 3 taping conditions
• Std thinning, inspection
Pressure roller
Wafer
motion
notch
Pattern direction
Pressure roller
Wafer
motion
notch
Pattern direction
Hologenix – YIS 150
(light deflectivity)
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
– Demonstration • Virgin silicon wafers, 3 taping conditions
• Std thinning, inspection
Pressure roller
Wafer
motion
notch
Pattern direction
Pressure roller
Wafer
motion
notch
Pattern direction
Hologenix – YIS 150
(light deflectivity)
No tape
Case study #3: tape waviness transfer
• Investigation – Finally focused on 1 step : tape deposition
• wafer is moved under a roller
• Ensuring uniform pressure
– Demonstration • Virgin silicon wafers, 3 taping conditions
• Std thinning, inspection
Pressure roller
Wafer
motion
notch
Pattern direction
Pressure roller
Wafer
motion
notch
Pattern direction
Hologenix – YIS 150
(light deflectivity)
No tape
Wave pattern is confirmed (shape and
orientation) tape dependent
Case study #3: tape waviness transfer
• Any impact on microvoids ?
Case study #3: tape waviness transfer
• Any impact on microvoids ?
BONDING with tape
Case study #3: tape waviness transfer
• Any impact on microvoids ?
BONDING with tape
Top wafer
Bottom wafer
Case study #3: tape waviness transfer
• Any impact on microvoids ?
BONDING with tape
Top wafer
Bottom wafer
Bonding w/o tape
Case study #3: tape waviness transfer
• Any impact on microvoids ?
BONDING with tape
Top wafer
Bottom wafer
Bonding w/o tape
Top wafer
Bottom wafer
TO CONCLUDE
122
To conclude
• Successfull cooperation with CMOS fab
• Enabling – Production of sensor with consistent yield though a complex supply chain
– New technology for our customer
• Building of depth of experience for
Rockwood
• Thin wafer (200 µm – 450 µm)
processing : tradeoff – w/o temporary carrier fewer thermal and cleaning limitations
– w/o sacrificial carrier cheaper
– But breakage occurrences
123
THANK YOU
124
