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CMOS-TECHNOLOGY - STATUS, TRENDS ANDAPPLICATIONS

F. Neppl, H.-J. Pfleiderer

To cite this version:F. Neppl, H.-J. Pfleiderer. CMOS-TECHNOLOGY - STATUS, TRENDS AND APPLICATIONS.Journal de Physique Colloques, 1988, 49 (C4), pp.C4-13-C4-22. �10.1051/jphyscol:1988402�. �jpa-00227824�

JOURNAL DE PHYSIQUE Colloque C4, suppl6ment au n09, Tome 49, septembre 1988

CMOS-TECHNOLOGY - STATUS, TRENDS AND APPLICATIONS

F. NEPPL and H.-J. PFLEIDERER

Siemens AG, Corporate Research and Development, Microelectronics, Otto-Hahn-Ring 6, 0-8000 Miinchen 83, F.R.G.

Abstract

Todays CMOS technology is reviewed with respect to process architec- ture, acquired CMOS specific device know-how, design and applications. The process and device related problems of further miniaturization are discussed. Trends of innovative device design and technology concepts able to overcome these problems are summarized. Finally examples are given for future CMOS applications.

In the last decade CMOS has turned from a specialty technology for battery driven devices and military applications into the main stream technology for high density VLSI circuits. By now it has widely replaced the earlier domi- nating NMOS-technology for new designs. Also world wide CMOS sales now ex- ceed NMOS sales significantly. Mainly two CMOS advantages are responsible for this development: low power dissipation and high noise margin. The sig- nificantly lower power dissipation improves power/delay product and allows higher packing density and chip complexity without the penalty of excessive chip temperature or cooling cost. The increased noise margin makes CMOS cir- cuits more resistant to variations of supply voltage, temperature and pro- cess variations. Additionally the importance of the initial CMOS inherent disadvantages of higher process complexity and larger chip size have con- tinuously decreased: CMOS process design became smarter and simultaneously NMOS technology had to implement more sophisticated circuit techniques (dynamic NMOS) and processes to reduce power dissipation to an acceptable level.

This paper summarizes the current status of CMOS technology and its appli- cations, discusses the problems of further scaling and circuit integration and outlines trends and extensions to overcome these problems.

Most of todays modern CMOS-processes have 1.0pm design rules at least in some critical levels like gate, contacts and metal 1. This requires 5:l or 10:l optical stepper lithography. A typical process concept contains epitaxy on highly doped substrate and twin tub for sufficient latch-up resistance, LOCOS isolation, about 20 nm of gate oxide, n+-poly- or polycide-gates, LDD for hot carrier resistant n-

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988402

JOURNAL DE PHYSIQUE

channel devices, reflowed isolation oxide for pre-planarization, tapered contact holes and diffusion barriers for low resistive and highly reliable contacts to Si and double level metallization for high packing density. The importance of the question whether n-well or p-well is the appropriate choice for main stream CMOS has been largely reduced by true twin tub con- cepts that allow to switch from n-well to p-well concept by simply changing the substrate from p- to n-type without changing the process sequence and implantation doses and hence the device parameters. Modern CMOS processes have 10 to 12 photolithography steps including double level metallization and passivation. This is significantly lower than ini- tial conservative CMOS approaches with about 15 masks and is close to the 10 masks required by a competitive NMOS process with buried contact and deple- tion transistors. Examples of process simplifications are self-aligned twin tub generation /I/, elimination of field and channel implant masks by ap- propriate adjustment of the well concentrations /2/, elimination of the LDD implant mask by new sidewall spacer techniques /3/ and selective oxidation of highly doped regions to protect these regions against subsequent S/D im- plantations in a self-aligned way. For process and device optimization extensive use is made of process and de- vice modeling to accelerate development and to reduce the expense of experi- mental wafer processing.

2.2 ~ M ~ ~ S P E C ~ T F I C ~ nev- -

Much of the present status of CMOS technology is the result of intensive re- search in general MOS technology like gate oxide quality, hot carrier de- gradation and interconnect systems. In this section only the CMOS specific areas of latch-up and the compensated p-channel transistor will be reviewed. The CMOS-inherent latch-up effect /4/ is the possibility of triggering the parasitic n+pnp+-SCRs present in every CMOS inverter. A lumped element model of the situation is given in Fig. 1. Triggering of the SCR is possible if the product of the current gains of the two coupled parasitic bipolar tran- sistors involved exceeds 1. It was demonstrated, however, that for Dl,= x PV,,= > 1. lower &product does not necessarily imply higher latch-up resistance (see Fig. 2). Particularly for high P,,,, the critical or trigger current is mainly determined by the shunt resistances involved and becomes independent of the P-product /5/. As is seen in Fig. 2 epi on highly doped substrate increases the critical current by more than an order of magnitude. This is a consequence of the drastical reduction of the substrate resistance. The characteristics of the MOS devices at the surface are not affected since the resistivity of the thin epi layer itself is sti.11 high, i.e. the doping level is low. General- ly, thinner epi makes shunting more effective. If the epi layer is too thin, however, the highly doped substrate may partly compensate the well doping and thus favor emitter/collector punch-through of the vertical bipolar tran- sistor.

Fig. 1

Wlth epilayer

n-WELL

Fig. 1: Lumped element model of parasitic SCR in n-well CMOS with Rs = substrate resistance and Rw = well resistance.

Fig. 2: Critical current of the parasitic SCR versus base width x of the parasitic lateral bipolar transistor for different technologies/l5/.

Low well resistance also increases the critical current. Aside of the re- duced shunt resistance, the corresponding higher doping level additionally degrades the current gain of the vertical bipolar transistor. In standard well constructions, however, excessive well doping increases body factor and junction capacitances and reduces the junction breakdown voltage of the MOS devices in the well and thus deteriorates circuit performance. This shows, that doping levels, epi thickness and well depths have to be ad- justed carefully to obtain optimum overall device characteristics. In addition to these bulk related effects, the parasitic field MOSFETS at the surface were shown to influence the turn-on of the two parasitic bipolar transistors and hence reduce the critical current and the latch-up re- sistance /6/. Finally, also dynamic triggering of latch-up during power-on and noise pulses could be explained by a combined effort of experiments / 7 / and simulations /8/. Initially, the two parasitic bipolar transistors were simply decoupled by separating n- and p-channel MOS devices by 20pm and more. This was a signi- ficant limitation for shrinking CMOS circuits. Based on the understanding of the essential parameters and their interdependences, even with conventional approaches careful process design currently allows minimum n+/p+-spacings of 5 - 6pm without latch-up risk. This implies that pad cells with drivers and ESD protection circuits, which are particularly effective current injecters, are specially separated from the adjacent logic by guardrings. The second CMOS specific device problem is the understanding and design op- timization of the "normally off" buried p-channel transistor, which results when in case of n+-poly gates (+,s = -0.3 V) the threshold voltage is ad- justed to a reasonable value around -0.8 V. Of particular concern are sub- threshold behavior or punch-through /9/ and UT(L) /lo/ of this MOSFET type. At the compensated surface, the total space charge region underneath the gate is a superposition of the depletion zone of the channel junction and of the gate induced depletion zone leading to a minimum of potential energy for holes (Fig. 3). The energy difference between this minimum und the hole source potential is the potential barrier AV the holes have to surmount in the sub-threshold region. Since the minimum of the potential barrier is located away from the surface (Fig. 3), the gate voltage control of aV is relatively weak. This results in a relatively high sub-threshold swing and makes the buried p-channel transistors particularly prone to punch-through. The situation is discussed in detail in /9/. Figs. 4 + 5 summarize the es- sential results of this study in terms of the potential barrier AV. Fig 4 demonstrates how the drain voltage control of the barrier and hence the sus- ceptability to punch-through is reduced when the gate oxide thickness is re- duced. Fig. 5 shows the decrease of aV with increasing channel junction depth d and surface p-concentration NA. From the variety of dependences, guidelines for the design of punch-through resistant buried p-channel tran- sistors down to the sub-micron regime could be derived: low gate oxide thickness, high n-well concentration, low surface concentration Nn and low channel junction depth d. The latter, however, has technological limitations

Fig. 3 lo, = 25nm

N +-gate I I

I A V 0.7 0.4 0.05

d = 0.1 pm 0.6 25

30 0.2

nm \ 0.2

I 0 1 2 3 4 5 ( V ) 6 0 2 4 6 8 1 0 1 ' 2

VDS --+ N A ( X 1 0 1 6 ) 4

Fig. 3: Band diagram of buried channel structure of the pMOSFET with n+- poly gate /9/.

Fig. 4: Gate oxide thickness dependence of the drain voltage induced lower- ing of the potential barrier~v for holes at zero gate voltage / 9 / .

Fig. 5: Influence of channel junction depth d and n-well concentration Nn on the potential barrier gV 191.

JOURNAL DE PHYSIQUE

in terms of implantation energy and annealing cycle. The doping conditions imply either relatively high threshold voltages or a very high concentration of centers for impurity scattering. Both effects limit the p-channel tran- sistor current.

Generally, switching from NMOS to CMOS brought design simplifications be- cause in many cases straight forward CMOS design could replace rather complicated (e.g. dynamic) NMOS logic. In particular, there is no permanent concern about d~mensioning the load and drive transistors because there is no trade-off between power consumption and speed like in NMOS. CMOS, in- stead, widely allows the use of standard transistors. Only a few critical data paths need to be optimized. This design simplification was also the basis for easier design automation and hence the MOS semi-custom approach with gate arrays and standard cells, One of the main design innovations of CMOS is the simplicity of implementing analog functions.This is demonstrated in Fig. 6 for an operational ampli- fier. The comparison with an equivalent NMOS version clearly shows the de- sign simplification in case of CMOS. Therefore, CMOS favors the combination of digital signal processing with A/D converters or other analog functions on a single chip. This is important because, even though signal processing now is mostly digital, interfacing with e.g. sensors is mostly analog. Together with the low power consumption these design advantages make CMOS the favorable technology for further system integration.

Fig. 6

r NMOS -

Input ,,, Level shift ,,, Gain ,, Output 1- 1- 1-

CMOS

Fig. 6: Comparison of operational amplifier circuits in NMOS and CMOS.

2.4 W S APP-

Because of the advantages discussed above, CMOS has become the technology of choice for a wide range of applications. This includes microcontrollers, mi- croprocessors, microcomputers, components for signal processing and tele- communication, EPROMs, SRAMs and DRAMS. Improvements of defect densities, lithography and device know-how as well as the reduction of power density have increased the integration density of CMOS in production to over one million transistors per cmZ. The most promi- nent representative of this category of chips is the 1 Mbit DRAM now avail- able on the market from several companies. The SIEMENS 1 Mbit DRAM, e.g., has about 2 x lo6 MOS devices on a chip area of 54.6 mm2, and a typical ac- cess time of 100 ns. A completely different example is standard-cell logic. This type of chip na- turally is not optimized with respect to high density of transistor func- tions. Instead, its integration density is predominantly determined by the metal pitches. Chip sizes of up to 200 mm' with up to several hundred thousand transistors but a dense net of interconnects are currently realized. Finally, CMOS is increasingly replacing TTL standard logic.

The urge for higher circuit speed, increased system integration and reduced cost per function keeps CMOS driven towards further scaling. Integration complexity is expected to increase from todays 10E6 to 10E7 to over 10E9 components per chip in the year 2000. Many predictions are based on the future development of DRAMS which are con- sidered to be technology leaders with respect to minimum feature size and integration density and for which in the past a certain regularity of the appearance of new generations was observed. Today, 4 Mbit DRAMS with minimum feature size of 0.8pm are already on their way into pilot line production. Furthermore, 16Mbit DRAMS with minimum feature size of 0.6pm are scheduled for the first half of the nineties and research aims already at 0.3 to 0.4pm feature size for 64 Mbit DRAMS. First experiments even demonstrate the feasibility of O.lpm MOSFETs which provide gate delays of 19 psec at room temperature and 13 psec at 77 K /11/. Fig. 7 exhibits the basic device structure and O.lpm transistor charac- teristics.

Fig.

O:O 0'2 0:4 0:6 0:8 (V) 1:0

Drain vollage +

Fig. 7: Cross section and J-V characteristics of O.lpm nMOSFET at 77 K ( - ) and 300 K ( - - - ) /11/.

This last example shows that MOS still has considerable potential for further scaling. Many process and device related problems need to be solved, however, before such technologies - if ever - can be utilized in a produc- tion like environment.

To fullfill the increasing requirements with respect to defect density, first of all special attention has to be paid to the quality of the starting material which increasingly also affects device reliability. An indispensable precondition for further scaling of CMOS is the ability to reproducibly generate structures of a few tenths of a micron. Down to =0.5pm optical lithography with deep UV in combination with sophisticated resist techniques will dominate. With X-ray, electron beam and ion beam lithography there exist techniques down to less than a tenth of a micron. Electron-beam and ion-beam lithography, however, have a low throughput and are therefore not yet suitable for high volume production. X-ray lithography provides suf- ficiently high throughput, but might be limited by mask tolerances which are transfered 1:l onto the chip. Although reactive ion etching provides excellent line width control, radia- tion damage during etching might affect the quality of extremely thin gate oxides ( 5 10 nm ) and of the Si/SiOa-interface unacceptably. Reactive ion stream etching might reduce radiation damage sufficiently /12/. Radiation damage during sputter deposition and plasma enhanced deposition is also a concern and needs to be minimized. Finally more attention has to be paid to device degradation by electrostatic potentials which build up during plasma processing and ion implantation /13/. Only when solutions to these processing related problems are found, sub- O.5um-technologies will eventually go into production.

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Further scalirig of CMOS below 1.0pm requires significant innovations in de- vice design. Sufficiently Latch up resistant circuits with n+/p+-spacings below 5pm ask for special technological measures: the retrograde well structure /14/ pro- vides the beneficial lower well resistance without affecting the device cha- racteristics at the surface. Its realization, however, needs the not yet established MeV-implantation. ~chottky-S/D /15/ or silicided S/D reduce the emitter effici.ency of the parasitic bipolar transistors and thus their f3- product. Final.ly, trench isolation of the wells in combination with epi on highly doped substrate was shown to effectively decouple the bipolar tran- sistors because the collector current of the vertical bipolar transistor is shunted to the substrate and does not reach the base of the lateral bipolar transistor /16/. Holding voltages above 10 V can be achieved for n+/p+- spacings as low as 2pm if the trench depth comes close to the epi thickness (Fig. 8): Control of the trench side wall isolation is necessary, however, before thls technique can be successfully implemented. For intra-well device isolation, bird's beak free techniques, which addi- tionally provide a higher degree of planarization, have to be adopted. Can- didates are BOX /17/ or refill of patterned oxide by selective Si-epitaxy /18/.

Fig. 8 Fig. 9

Holding voltage. V H

Epi : 3 pm x trench : 1.4 pm o trench : 0 pm

4 6 8 (urn) 10 n + -p + spacing, d -

Drain current reduction - A l o l l D 1100 , I

To, = 16 nm L = O B p m , .-- N-dose [LDD) = 2 X 10 131crn 2 .I*'. Measure. Vo = 0 1V. VG = 3 V ./ surface/^^^

0 V G = 3 5v. v o = 7 v * .'

I 10 io 2 l b 3 (set) 1'04

Stress time --+

Fig. 8: Holding voltage V, versus n+/p+-spacing d with trench depth as parameter /16/.

Fig. 9: Drain current degradation of surface channel and buried channel nMOSFETs /19/.

Sub-micron CMOS will feature MOSFETS with gate lengths of a few tenths of a micron, gate oxide thickness of a few nm only and source/drain junction depths <0.2pm. These MOSFETs eventually will have to be operated at a supply voltage <5 V. A crucial problem is the hot carrier degradation of future n-channel MOSFETs. The standard LDD-technique might not be able to guarantee sufficient transistor lifetime. More sophisticated LDD structures like buried LDD provide better reliability. An alternative approach is to adopt the buried channel structure for the n-channel and thus shift the location of maximum hot carrier generation into the bulk and away from the endangered gate oxide. For an acceptably low threshold voltage, this requires a gate material with higher work function than n+-poly. Fig. 9 shows more than an order of magnitude reduction of the degradation rate for buried n-channels 1 9 It has to be noted, that there is a trade-off with respect to the short channel characteristics. Technologically, however, the buried n- channel is easier to control than the p-channel, because As instead of the fast diffusing B is used for surface compensation.

Also the p-channel MOSFETs become increasingly prone to hot carrier degradation and will require LDD techniques. The short channel charac- teristics of the p-MOSFETs can be improved by changing the work function of the gate material to higher values, i.e. from n+-poly to silicide, metal or p+-polycide gate. Thereby the p-channel type is changed from buried to surface type. Fig. 10 demonstrates the improvement of the short channel characterlstlcs In terms of the sub-threshold swing obtained for silicide and p+-polycide gate, respectively /20/. Furthermore, UT of the surface channel transistor with p+-polycide gate can be chosen low (erg. 0.6 V) without a trade-off with respect to punch-through. This results In a 15-20% higher current drive than for the standard buried p-channel device. These examples show that the gate work function can improve the charac- teristics of both types of MOSFETs and therefore might-become a significant parameter for optimization of sub-micron devices. SALICIDE will be widely used to minimize parasitic series resistances of MOSFETs. Most techniques use a uniform metal deposition (e.g. Ti, Co, Pt) with subsequent selective silicide reaction with underlying Si /21/. Recently selective CVD of silicide with the advantage of minimum Si consumption and planarization capability has also been demonstrated for this application /22/. In combination with the "strap" technique /23/ SALICIDE allows a significant reduction of the junction capacitances, adds additional wiring flexibility and offers the possibility of direct contacts between source/drain and the gate level for both transistor types, analog to the buried contact in NMOS. Therefore, SALICIDE is one of the key process inno- vations for improved packing density and speed.

Fig. 10

ub-threshold swing O U G S I A (log lo)

Fig. 11

0 5 1.0 1.5 (urn) 2.0 Efleclive channel lenglh ----+

' 194 Annealing time 120 min 1 Annealins time 120 min I

Junction depth ----+ Junctcon depth ----c

Fig. 10: Subthreshold swing of pMOSFETs with different gate electrodes. Channel implants were adjusted for constant threshold voltage /20/.

Fig. 11: SIMS profiles of As and B doped source/drain regions fabricated by outdiffusion of implanted TaSil /25/.

Junction depths L0.2pm can be obtained by rapid thermal annealing and/or preamorphization of Si by Si or Ge implantation /24/. The fabrication of extremely shallow junctions L O.lpm was demonstrated by outdiffusion of implanted silicide /25/. Fig. 11 shows examples for boron and arsenic. Scaling below 1.0pm raises particular problems with respect to the inter- connect system. For non-scaled thickness, interconnect lifetime was esti- mated to decrease with the fifth power of the scaling factor /26/ which makes electromigration failures an increasingly important issue. Since wiring capacitances no longer scale with line width and are dominated by the metal thickness dependent fringing capacitances, reducing the metal thick- ness is essential to reduce the total capacitive load. This makes the elec- tromigration problem even worse. In sub-micron metallizations, stress migration was demonstrated to become an additional failure .mode. Its importance increases with decreasing line width /27/. Consequently the introduction of a metal "stronger" than aluminum is mandatory.

JOURNAL DE PHYSIQUE

As interconnect cross sections decrease and average interconnect lengths rather increase, interconnect resistivity is no longer negligible with respect to voltage drops and RC delays. Therefore particularly low resistive interconnect materials are needed. Al/Ti multisandwich structures /28/ provide a promising compromise between both requirements. Tungsten may be restricted to short and medium range in- terconnects because of its relatively high resistivity. High temperature superconductors were largely eliminated as a possible solution to the inter- connect problem in CMOS technology /29/. One of the reasons is that at the required temperatures of I 80 K the established Al-technology again full- fills all requirements. Contact and via filling e.g. by CVD-tungsten will be generally used to avoid metal step coverage problems in small contacts. The standard planarization of the inter inetal dielectric including PECVD-oxide, polyimide or spin-on- glass auxiliary layers and etch-back might continue to dominate for a while because reduced metal thickness and superconformal PECVD-oxides alleviate the actual problems. Deep sub-micron optical lithography for fine line interconnects, however, requires additional efforts with respect to global planarization to account for the limited depth of focus of high resolution lenses.

With the device innovations discussed above, standard CMOS has considerable potential for further scaling. In addition, however, conceptual innovations are discussed to drive CMOS towards higher performance and packing density. For higher speed, operating CMOS at 77 K is often discussed. A summary of performance improvements, necessary device optimizations and remaining problems is given e.g. in a special issue of IEEE Trans. Electron Devices /30/. Advantages include high transistor current, extremely low latch up risk, low metal resistance and better reliability with respect to thermally activated degradation mechanisms. This, e.g., dramatically improves metal- lization reliiibility. The significantly increased hot carrier induced degradation at low temperatures, however, requires a reduced supply voltage. Therefore, the possible speed advantage is partly lost again. An overall increase of circuit speed of a factor of 1.5 to 2 over room temperature CMOS is predicted. Cost and inconvenience of cooling, however, might prevent this approach to be (jenerally adopted.

SO1 structures on Si wafer substrates are of increasing interest. They avoid the substrate cost penalty of earlier SOS and maintain the device and cir- cuit advantages of this technology, i.e. low capacitances, low sub-threshold swing,higher packing density and radiation hardness. Technologies used are oxygen implantation of Si (SIMOX), oxidation of porous Si, recrystallization of poly-Si /31/ and lateral growth of Si-epitaxy /32/. The applicability of these techniques in production of highly integrated circuits has to be proven yet.

BICMOS technology combines the low power dissipation of CMOS with the high speed and the inherent analog advantages of bipolar devices. From a pro- cessing point of view, there is no reservation to integrate both tech- nologies in one line, since many process steps can be used simultaneously for CMOS and bipolar, anyway, and bipolar specific process steps can be inserted as modules. High speed SRAMs are the field of application for BICMOS which offers high performance bipolar transistors. Since CMOS and bipolar components have to be optimized simultaneously, process complexity is rather high and the number of masks may increase to 20. An alternative approach uses mostly CMOS process steps for the fabrication of the bipolar transistors and requires only 1 to 3 additional masks. Nevertheless, this type of BICMOS also provides significantly better current drive (and hence speed) and easi.er implementation of analog functions than pure CMOS. Such BICMOS with at most moderate extra cost might be a candidate for replacing pure CMOS as a main stream technology in the future. To account for the increasing development cost and for the simultaneous need for application specific technologies, process architecture is generally forced towards a modular scheme with one basic CMOS process that can be supplemented by certain application specific modules. BICMOS is an outstanding example. But also process optimization with respect to e.g. DRAMS, SRAMs or E2PROMs will increasingly follow this concept.

Reduction of supply voltage is often discussed for mitigation of hot carrier problems and of excessive power dissipation of sub-micron chips. 0.5pm technology is considered to be a critical process generation for this change. Interfacing with existing 5 V circuitry can be solved in principle by on-chip voltage reduction. The major concern is the increase of gate delay caused by a VD,-reduction which would have to be overcompensated to make scaling still advantageous with respect to higher speed. A general trend of applications is towards more system integration to reduce cost, system delay and reliability problems related to the number of packages and pins involved. In view of increasing chip complexity, extensive use of automatic design and shrinkability of optimized components is man- datory. CMOS chips for small and medium size computer systems have to provide a data processing rate of more than 10 MIPS. CMOS components for broad band ISDN have to meet the 140 or 560 Mbit/sec requirement of this technology. Appli- cations like high definition TV ask for signal processing with up to 50 MHz band width and high density memories with low access time. All these applications need the most progressive technology available and partly also new chip architecture. The most aggressive requirements might come from the attempt to functionally simulate the human brain by realizing "artificial neuron nets" for extensive parallel and associative processing. This concept is advantageous e.g. for fast recognition of image and speech patterns. Even simple implementations with loo neurons require the packing density of 1.0pm technology, already. More useful systems with lo4 neurons would need O.lgm technology and thus the most progressive MOS technology demonstrated so far.

4 . CONCLUSION

This summary shows that CMOS is a main stream technology with considerable potential of technological development and applications. Since one ap- proaches the fundamental physical limits, however, the cost of progress 1s increasing significantly. Particularly the step from feasibility to pro- duction seems to become increasingly difficult, time consuming and expen- sive. On the other hand, speed improvement by scaling is becoming less than predicted by simple scaling. Consequently the price for a given improvement of performance is rising dramatically and is even about to exceed the pos- sibilities of individual companies. To push deep sub-micron CMOS technology nevertheless, government-funded cooperations like SEMATEC in USA or JESSI in Europe have been started. These efforts show that CMOS is considered a key technology for further technological and economical development.

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