Class-AB Single-Stage OpAmp for Low-Power Switched ...pserra/cnm/2015 - Class-AB Single-Stage... ·...
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Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits S. Sutula 1 , M. Dei 1 , L. Terés 1,2 and F. Serra-Graells 1,2 1 Integrated Circuits and Systems Group, IMB-CNM(CSIC) 2 Dept. of Microelectronics and Electronic Systems [email protected] A new family of Class-AB OpAmp circuits based on single-stage topologies with non-linear current amplifiers is presented. The proposed architecture is characterized by generating all Class- AB current in the output transistors only. It exhibits low sensitiv- ity to technology parameter variations and avoids the need for internal frequency compensation. It is suitable for low-power switched-capacitor circuits and optimized for a fast on-off op- eration and multi-decade load-capacitance specifications. A complete OpAmp design example is integrated in a standard 0.18-μm 1P6M CMOS technology. Compared to the MOS-only state-of-the-art Class-AB OpAmps, the presented architecture obtains the highest figure of merit. Abstract A single-stage-OpAmp architecture is proposed with two com- plementary Class-AB control paths for the NMOS and PMOS output transistors. Supposing strong inversion operation for all boxed devices, each non-linear current amplifier behaves as r I onp D = r I inp A + r nβ 2 V cp D . = AB A+B From the Class-AB viewpoint, the wanted functionality for these voltage-controlled current mirrors is: I outp ≡ 0 V cp ≡ V xp I onp ≡ I inp ≡ I tail 2 Bias point I outp 6≡ 0 V cp 6≡ V xp I onp I inp I onp I inp Class-AB operation Architecture A cross-coupled pair (B-B) is introduced to provide the positive feedback for the Class-AB operation, while a crossing transistor (C) play the role of a feedback limiter. I inp =B 2 q I onn D - q I onp D + q I inp A q I onp D - q I inp A +C q 2I tail D - q I onp D - q I onn D + q I inp A + q I inn A q I onp D - q I onn D - q I inp A + q I inn A The process parameters β and n disappear from the current- amplifier equation. Hence, independence from technology is achieved. Under Class-AB high modulation, common-mode currents can be injected to prevent a possible self-latch. Type-I Circuit Here, the crossing transistor (C) of the Type-I circuit is replaced by two split counterparts (C-C), which are auto-biased. Thus, extra reference circuits are not needed and power consumption is reduced. I inp = 2 B q I onn D +C q I onp D -(B+C) q I onp D - q I inp A q I onp D - q I inp A D . = A(B+C) A+B+C I max ’ 1+ A C 1+ A B+C I tail >I tail Independence from the technology parameters is also preserved. Type-II Circuit Type-II architecture is chosen for the design example in a 0.18-μm CMOS technology node. − 1 0 1 I onn I onp I inp 0 4 8 [mA] I inn [mA] As shown, the number of transistor groups is mini- mized and minimum device lengths can be used. In this particular case, optimization finds the best performance for A=4, B=3 and C=1. The Class-AB behavior is demonstrated for the NMOS outputs. The OpAmp is stable for a wide range of load capacitance values. 0 0. 4 0. 8 1. 2 1. 6 2 − 1 0 1 Time × Input Frequency [-] Diff. Output Voltage [ V] 650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz The OpAmp is integrated using a standard 0.18-μm 1P6M CMOS technology, achieving an overall area of 0.07-mm 2 . The circuit layout includes additional common-mode feedback (CMFB) averaging capacitors for switched-capacitor applications. Practical Design − 1 0 1 Simulated Measured 0 0. 4 0. 8 1. 2 1. 6 2 0 5 10 I supply I opp I opn Current [mA] 0 40 80 120 160 200 − 2 − 1 0 1 2 Time [ms] Ideal Simulated Measured Diff. Output Voltage [ V] Diff. Output Voltage [ V] Operating at a 1.8-V power supply, a remarkable differential full scale of 3.3 V pp is measured. The performance of the proposed OpAmp is compared with others from published Class-AB ampli- fiers [1]–[5] by using the figure of merit (FOM) from [5] FOM = SR · C load P V μs pF μW . Parameter [1] [2] [3] [4] [5] This work Units Technology 0.5 0.5 0.25 0.13 0.18 0.18 μm Supply 2 2 1.2 1.2 0.8 1.8 V DC gain 43 45 69 70 51 72 dB C load 80 25 4 5.5 8 200 pF GBW 0.725 11 165 35 0.057 86.5 MHz Phase margin 89.5 N/A 65 45 60 50 ° Slew rate, SR 89 20 329 19.5 0.14 74.1 V/μs Static power, P 0.12 0.04 5.8 0.11 0.0012 11.9 mW Area 0.024 0.012 N/A 0.012 0.057 0.07 mm 2 FOM 59.33 12.50 0.28 0.98 0.93 1.25 V μs pF μW The works [1], [2] report higher FOM, but at the cost of requiring integrated resistors, which makes them more sensitive to technol- ogy parameter variations, and of a considerable lowering of their DC gain, which may be incompatible with high-precision appli- cations. The works using MOS-only devices [3]–[5] present lower FOM and DC gain. Therefore, a contribution to the improvement of MOS-only Class-AB OpAmps is demonstrated. Experimental Results • A new family of Class-AB OpAmps has been presented. • The architecture is based on a single-stage topology. • The circuits do not need any internal frequency compensation. • The Class-AB current peaks are produced in the output tran- sistors only. • The resulting OpAmps exhibit low sensitivity to the technology parameter variations. • Good performance is achieved using a simple design flow. • The Type II has been successfully used in a 16-bit 100-kS/s DΣ ADC. Conclusions References [1] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, “Low- Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1068– 1077, 2005. [2] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan, and A. Lopez-Martin, “A Free But Efficient Low-Voltage Class-AB Two-Stage Operational Amplifier,” IEEE Transactions on Circuits and Systems II: Expressed Briefs, vol. 53, pp. 568–571, 2006. [3] M. Yavary and O. Shoaei, “Very Low-Voltage, Low-Power and Fast-Settling OTA for Switched-Capacitor Applications,” in Proceedings of the Interna- tional Conference on Microelectronics, 2002, pp. 10–13. [4]M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes, “A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, pp. 1591–1603, 2011. [5] M. R. Valero, S. Celma, N. Medrano, B. Calvo, and C. Azcona, “An Ul- tra Low-Power Low-Voltage Class AB CMOS Fully Differential OpAmp,” in Proceedings of the IEEE International Symposium on Circuits and Systems, 2012, pp. 1967–1970.
Transcript of Class-AB Single-Stage OpAmp for Low-Power Switched ...pserra/cnm/2015 - Class-AB Single-Stage... ·...
Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor CircuitsS. Sutula1, M. Dei1, L. Terés1,2 and F. Serra-Graells1,21Integrated Circuits and Systems Group, IMB-CNM(CSIC) 2Dept. of Microelectronics and Electronic Systems
A new family of Class-AB OpAmp circuits based on single-stagetopologies with non-linear current amplifiers is presented. Theproposed architecture is characterized by generating all Class-AB current in the output transistors only. It exhibits low sensitiv-ity to technology parameter variations and avoids the need forinternal frequency compensation. It is suitable for low-powerswitched-capacitor circuits and optimized for a fast on-off op-eration and multi-decade load-capacitance specifications. Acomplete OpAmp design example is integrated in a standard0.18-µm 1P6M CMOS technology. Compared to the MOS-onlystate-of-the-art Class-AB OpAmps, the presented architectureobtains the highest figure of merit.
Abstract
A single-stage-OpAmp architecture is proposed with two com-plementary Class-AB control paths for the NMOS and PMOSoutput transistors.
Supposing strong inversion operation for all boxed devices, eachnon-linear current amplifier behaves as√IonpD
=
√IinpA
+
√nβ
2Vcp D
.=
AB
A + BFrom the Class-AB viewpoint, the wanted functionality for thesevoltage-controlled current mirrors is:Ioutp ≡ 0 Vcp ≡ Vxp Ionp ≡ Iinp ≡ Itail
2 Bias pointIoutp 6≡ 0 Vcp 6≡ Vxp
Ionp� Iinp
Ionp� Iinp
Class-AB operation
Architecture
A cross-coupled pair (B-B) is introduced to provide the positivefeedback for the Class-AB operation, while a crossing transistor(C) play the role of a feedback limiter.
Iinp =B
(2√
IonnD −
√IonpD +
√IinpA
)(√IonpD −
√IinpA
)+C
(√2ItailD −
√IonpD
−√
IonnD +
√IinpA +
√IinnA
)(√IonpD −
√IonnD −
√IinpA +
√IinnA
)The process parameters β and n disappear from the current-amplifier equation. Hence, independence from technology isachieved. Under Class-AB high modulation, common-modecurrents can be injected to prevent a possible self-latch.
Type-I Circuit
Here, the crossing transistor (C) of the Type-I circuit is replacedby two split counterparts (C-C), which are auto-biased. Thus,extra reference circuits are not needed and power consumption isreduced.
Iinp =[2
(B√
IonnD +C
√IonpD
)−(B+C)
(√IonpD −
√IinpA
)](√IonpD −
√IinpA
)
D.=
A(B+C)A+B+C Imax '
1+AC
1+ AB+C
Itail > Itail
Independence from the technology parameters is also preserved.
Type-II Circuit
Type-II architecture is chosen for the design example in a 0.18-µmCMOS technology node.
−1 0 1
Ionn Ionp
Iinp
0
4
8
[mA
]
Iinn [mA]
As shown, the number oftransistor groups is mini-mized and minimum devicelengths can be used. In thisparticular case, optimizationfinds the best performancefor A=4, B=3 and C=1.The Class-AB behavior isdemonstrated for the NMOSoutputs.The OpAmp is stable for a wide range of load capacitance values.
0 0.4 0.8 1.2 1.6 2
−1
0
1
Time × Input Frequency [-]
50 nF at 1 kHz
Diff
. Out
put
Volta
ge [V
] 650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz
The OpAmp is integrated using a standard 0.18-µm 1P6M CMOStechnology, achieving an overall area of 0.07-mm2. The circuitlayout includes additional common-mode feedback (CMFB)averaging capacitors for switched-capacitor applications.
Practical Design
−1
0
1SimulatedMeasured
0 0.4 0.8 1.2 1.6 20
5
10Isupply
Iopp Iopn
Cur
rent
[mA
]
0 40 80 120 160 200−2
−1
0
1
2
Time [ms]
IdealSimulatedMeasured
1
2
Diff
.Out
put
Volta
ge [V
]D
iff. O
utpu
t Vo
ltage
[V]
Operating at a 1.8-V power supply, a remarkable differential fullscale of 3.3 Vpp is measured. The performance of the proposedOpAmp is compared with others from published Class-AB ampli-fiers [1]–[5] by using the figure of merit (FOM) from [5]FOM =
SR · Cload
P
[ Vµs pFµW].
Parameter [1] [2] [3] [4] [5] Thiswork UnitsTechnology 0.5 0.5 0.25 0.13 0.18 0.18 µmSupply 2 2 1.2 1.2 0.8 1.8 VDC gain 43 45 69 70 51 72 dBCload 80 25 4 5.5 8 200 pFGBW 0.725 11 165 35 0.057 86.5 MHzPhase margin 89.5 N/A 65 45 60 50 °Slew rate, SR 89 20 329 19.5 0.14 74.1 V/µsStatic power, P 0.12 0.04 5.8 0.11 0.0012 11.9 mWArea 0.024 0.012 N/A 0.012 0.057 0.07 mm2FOM 59.33 12.50 0.28 0.98 0.93 1.25 Vµs pFµWThe works [1], [2] report higher FOM, but at the cost of requiringintegrated resistors, which makes them more sensitive to technol-ogy parameter variations, and of a considerable lowering of theirDC gain, which may be incompatible with high-precision appli-cations. The works using MOS-only devices [3]–[5] present lowerFOM and DC gain. Therefore, a contribution to the improvementof MOS-only Class-AB OpAmps is demonstrated.
Experimental Results
• A new family of Class-AB OpAmps has been presented.• The architecture is based on a single-stage topology.• The circuits do not need any internal frequency compensation.• The Class-AB current peaks are produced in the output tran-sistors only.• The resulting OpAmps exhibit low sensitivity to the technologyparameter variations.•Good performance is achieved using a simple design flow.• The Type II has been successfully used in a 16-bit 100-kS/sΔΣ ADC.
Conclusions
References[1] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, “Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate andPower Efficiency,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1068–1077, 2005.[2] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan, and A. Lopez-Martin, “AFree But Efficient Low-Voltage Class-AB Two-Stage Operational Amplifier,”
IEEE Transactions on Circuits and Systems II: Expressed Briefs, vol. 53, pp.568–571, 2006.[3] M. Yavary and O. Shoaei, “Very Low-Voltage, Low-Power and Fast-SettlingOTA for Switched-Capacitor Applications,” in Proceedings of the Interna-tional Conference on Microelectronics, 2002, pp. 10–13.[4] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, andJ. Goes, “A Two-Stage Fully Differential Inverter-Based Self-Biased CMOSAmplifier With High Efficiency,” IEEE Transactions on Circuits and SystemsI: Regular Papers, vol. 58, pp. 1591–1603, 2011.[5] M. R. Valero, S. Celma, N. Medrano, B. Calvo, and C. Azcona, “An Ul-tra Low-Power Low-Voltage Class AB CMOS Fully Differential OpAmp,” inProceedings of the IEEE International Symposium on Circuits and Systems,2012, pp. 1967–1970.
