Chapter 4 Combinational Logic
description
Transcript of Chapter 4 Combinational Logic
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Digital System Ch4-1
Chapter 4 Combinational Logic
Ping-Liang Lai (賴秉樑 )
Digital System數位系統
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Digital System Ch4-2
Outline of Chapter 4
4.1 Introduction 4.2 Combination Circuits 4.3 Analysis Procedure 4.4 Design Procedure 4.5 Binary Adder-Subtractor 4.6 Decimal Adder 4.7 Binary Multiplier 4.8 Magnitude Comparator 4.9 Decoders 4.10 Encoders 4.11 Multiplexers 4.12 HDL Models of Combination Circuits
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Digital System Ch4-3
4.1 Introduction (p.138)
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.
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Digital System Ch4-4
4.2 Combinational Circuits (p.138)
Logic circuits for digital system Sequential circuits
» Contain memory elements.» The outputs are a function of the current inputs and the state of the memory
elements.» The outputs also depend on past inputs.
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Digital System Ch4-5
Combinational Circuits (p.139)
A combinational circuits 2
n possible combinations of input values
Specific functions» Adders, subtractors, comparators, decoders, encoders, and multiplexers.» MSI circuits or standard cells.
CombinationalLogic Circuit
n inputvariables
m outputvariables
….. …..Figure 4.1 Block diagram of combinational circuit
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Digital System Ch4-6
4-3 Analysis Procedure (p.139)
A combinational circuit Make sure that it is combinational not sequential
» No feedback path. Derive its Boolean functions (truth table) Design verification A verbal explanation of its function
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Digital System Ch4-7
A Straight-forward Procedure (p.140)
F2 = AB+AC+BCT1 = A+B+CT2 = ABCT3 = F2'T1
F1 = T3+T2
Figure 4.2 Logic Diagram for Analysis Example
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Digital System Ch4-8
F1 = T3+T2 = F2'T1+ABC = (AB + AC + BC)'(A + B + C) + ABC = (A' + B')(A' + C')(B' + C')(A + B + C) + ABC = (A' + B'C') (AB' + AC' + BC' + B'C) + ABC = A'BC' + A'B'C + AB'C' + ABC
A full-adder F1: the sum
F2: the carry
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Digital System Ch4-9
The Full-adder
The truth table
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Digital System Ch4-10
4-4 Design Procedure (p.142)
The design procedure of combinational circuits State the problem (system spec.) Determine the inputs and outputs The input and output variables are assigned symbols Derive the truth table Derive the simplified Boolean functions Draw the logic diagram and verify the correctness
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Digital System Ch4-11
Design Procedure
Functional description Boolean function HDL (Hardware description language)
» Verilog HDL» VHDL
Schematic entry Logic minimization
Number of gates Number of inputs to a gate Propagation delay Number of interconnection Limitations of the driving capabilities
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Digital System Ch4-12
Code Conversion Example (p.143)
BCD to excess-3 code The truth table
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Digital System Ch4-13
The Maps (p.144)
Figure 4.3 Maps for BCE to Excess-3 Code Converter
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Digital System Ch4-14
(p.145)
The simplified functions z = D' y = CD +C'D' x = B'C + B'D+BC'D' w = A+BC+BD
Another implementation z = D' y = CD +C'D' = CD + (C+D)' x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)' w = A+BC+BD
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Digital System Ch4-15
BCD to Excess-3
The logic diagram
Fig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter
z = D' y = CD +C'D' = CD + (C+D)' x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)‘w = A+BC+BD
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Digital System Ch4-16
4-5 Binary Adder-Subtractor (p.146)
Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10 Two input variables: x, y Two output variables: C (carry), S (sum) Truth table
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Digital System Ch4-17
Half Adder
S = x'y+xy' C = xy
The flexibility for implementation S = xy S = (x+y)(x'+y') S' = xy+x'y' S = (C+x'y')' C = xy = (x'+y')'
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Digital System Ch4-18Figure 4.5 Implementation of Half-Adder
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Digital System Ch4-19
Full-Adder (p.147)
Full-Adder The arithmetic sum of three input
bits. Three input bits
» x, y: two significant bits.» z: the carry bit from the previous
lower significant bit. Two output bits: C, S
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Digital System Ch4-20Fig. 4-7 Implementation of Full Adder in Sum of Products
Fig. 4-6 Map for Full Adder
Full-Adder
S C
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Digital System Ch4-21
Full-Adder
S = x'y'z+x'yz'+ xy'z'+xyz C = xy+xz+yz S = z(xy) = z'(xy'+x'y)+z(xy'+x'y)'= z'xy'+z'x'y+z((x'+y)(x+y')) =
xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy
Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate
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Digital System Ch4-22
Binary Adder (p.149)
Figure 4.9 Full-bit adder
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Digital System Ch4-23
Carry propagation
When the correct outputs are available The critical path counts (the worst case) (A1, B1, C1) → C2 → C3 → C4 → (C5, S4) When 4-bits full-adder → 8 gate levels (n-bits: 2n gate levels)
Figure 4.10 Full Adder with P and G Shown
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Digital System Ch4-24
Parallel Adders
Reduce the carry propagation delay Employ faster gates Look-ahead carry (more complex mechanism, yet faster) Carry propagate: Pi = AiBi
Carry generate: Gi = AiBi
Sum: Si = PiCi
Carry: Ci+1 = Gi+PiCi
C0 = Input carry
C1 = G0+P0C0
C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
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Digital System Ch4-25
Carry Look-ahead Adder (1/2)
Logic diagram
Fig. 4.11 Logic Diagram of Carry Look-ahead Generator
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Digital System Ch4-26
Carry Look-ahead Adder (2/2)
4-bit carry-look ahead adder Propagation delay of C3, C2
and C1 are equal.
Fig. 4.12 4-Bit Adder with Carry Look-ahead
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Digital System Ch4-27
Binary Subtractor
A - B = A+(2’s complement of B) 4-bit Adder-subtractor
M=0, A+B; M=1, A+(B’+1)
Fig. 4.13 4-Bit Adder Subtractor
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Digital System Ch4-28
Overflow The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow
Example:
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Digital System Ch4-29
4-6 Decimal Adder
Add two BCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out
Design approaches A truth table with 29 entries Use binary full Adders
» The maximum sum ← 9 + 9 + 1 = 19» Binary to BCD
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Digital System Ch4-30
BCD Adder (1/3)
BCD Adder: The truth table
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Digital System Ch4-31
BCD Adder (2/3)
Modifications are needed if the sum > 9 If C = 1, then sum > 9
» K = 1, or
» Z8Z4 = 1 (11××), or
» Z8Z2 = 1 (1×1×).
Modification: (10)d or + 6
C = K +Z8Z4 + Z8Z2
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Digital System Ch4-32
BCD Adder (3/3)
Block diagram
Fig. 4-14 Block Diagram of a BCD Adder
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Digital System Ch4-33
Binary Multiplier (1/2)
Partial products AND operations
Fig. 4.15 Two-bit by two-bit binary multiplier
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Digital System Ch4-34
Binary Multiplier (2/2)
4-bit by 3-bit binary multiplier
Fig. 4.16 Four-bit by three-bit binary multiplier
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Digital System Ch4-35
4-8 Magnitude Comparator
The comparison of two numbers Outputs: A>B, A=B, A<B
Design Approaches The truth table of 2n-bit comparator
» 22n
entries - too cumbersome for large n Use inherent regularity of the problem
» Reduce design efforts» Reduce human errors
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Digital System Ch4-36
Algorithm → logic A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1 and A1=B1
» Equality: xi= AiBi+Ai'Bi'
» (A=B) = x3x2x1x0=1
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Implementation xi = (AiBi'+Ai'Bi)'
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Digital System Ch4-37Fig. 4.17 Four-bit magnitude comparator.
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Digital System Ch4-38
4-9 Decoder
A n-to-m decoder A binary code of n bits = 2
n distinct information
N input variables; up to 2n output lines
Only one output can be active (high) at any time
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Digital System Ch4-39
An implementation
Fig. 4.18 Three-to-eight-line decoder
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Digital System Ch4-40
Combinational logic implementation Each output = a minterm. Use a decoder and an external OR gate to implement any Boolean function
of n input variables.
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Digital System Ch4-41
Demultiplexers A decoder with an enable input. Receive information on a single line and transmits it on one of 2
n possible
output lines.
Fig. 4.19 Two-to-four-line decoder with enable input
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Digital System Ch4-42
Decoder/demultiplexers
第三版內容,參考用 !
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Digital System Ch4-43
Expansion Two 3-to-8 decoder: a 4-to-16 decoder
Fig. 4.20 4 16 decoder constructed with two 3 8 decoders
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Digital System Ch4-44
Combination Logic Implementation
Each output = a minterm Use a decoder and an external OR gate to implement any Boolean function
of n input variables A full-adder
» S(x, y, z) = (1,2,4,7)» C(x, y, z) = (3,5,6,7)
Fig. 4.21 Implementation of a full adder with a decoder
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Digital System Ch4-45
Two possible approaches using decoder» OR(minterms of F): k inputs (k minterms)
» NOR(minterms of F'): 2n k inputs
In general, it is not a practical implementation
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Digital System Ch4-46
4-10 Encoders
The inverse function of a decoder
1 3 5 7
2 3 6 7
4 5 6 7
z D D D D
y D D D D
x D D D D
The encoder can be implemented with three OR gates.
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Digital System Ch4-47
An implementation
Limitations » Illegal input: e.g. D3=D6=1» The output = 111 (¹3 and ¹6)
第三版內容,參考用 !
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Digital System Ch4-48
Priority Encoder
Resolve the ambiguity of illegal inputs Only one of the input is encoded
D3 has the highest priority D0 has the lowest priority X: don't-care conditions V: valid output indicator
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Digital System Ch4-49
The maps for simplifying outputs x and y
Fig. 4.22 Maps for a priority encoder
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Digital System Ch4-50
Implementation of priority
Fig. 4.23 Four-input priority encoder2 3
3 1 2
0 1 2 3
x D D
y D D D
V D D D D
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Digital System Ch4-51
4-11 Multiplexers
Select binary information from one of many input lines and direct it to a single output line
2n input lines, n selection lines and one output line
e.g.: 2-to-1-line multiplexer
Fig. 4.24 Two-to-one-line multiplexer
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Digital System Ch4-52
4-to-1 line multiplexer
Fig. 4.25 Four-to-one-line multiplexer
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Digital System Ch4-53
Note: 2n-to-1 multiplexer n-to- 2
n decoder
Add the 2n input lines to each AND gate
OR (all AND gates) n selection lines An enable input (an option)
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Digital System Ch4-54Fig. 4.26 Quadruple two-to-one-line multiplexer
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Digital System Ch4-55
Boolean Function Implementation
MUX: a decoder + an OR gate 2
n-to-1 MUX can implement any Boolean function of n input variable
A better solution: implement any Boolean function of n+1 input variable» n of these variables: the selection lines» The remaining variable: the inputs
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Digital System Ch4-56
An example: F(A, B, C) = (1, 2, 6, 7)
Fig. 4.27 Implementing a Boolean function with a multiplexer
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Digital System Ch4-57
Procedure: Assign an ordering sequence of the input variable The rightmost variable (D) will be used for the input lines Assign the remaining n-1 variables to the selection lines w.r.t. their
corresponding sequence Construct the truth table Consider a pair of consecutive minterms starting from m0
Determine the input lines
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Digital System Ch4-58
Example: F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
Fig. 4.28 Implementing a four-input function with a multiplexer
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Digital System Ch4-59
Three-state Gates
A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts)
Fig. 4.29 Graphic symbol for a three-state buffer
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Digital System Ch4-60
Example: Four-to-one-line multiplexer
Fig. 4.30 Multiplexer with three-state gates
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Digital System Ch4-61
4-12 HDL Models of Combinational Circuits
Modeling Styles Gate-level modeling using instantiations of predefined and user-defined
primitive gates. Dataflow modeling using continuous assignment statements with the
keyword assign. Behavioral modeling using procedural assignment statements with the
keyword always.
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Digital System Ch4-62
Gate-level Modeling
The four-valued logic truth tables for the and, or, xor, and not primitives
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Digital System Ch4-63
Gate-level Modeling
Example:
The first statement declares an output vector D with four bits, 0 through 3.
The second declares a wire vector SUM with eight bits numbered 7 through 0.
output [0: 3] D;wire [7: 0] SUM;
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Digital System Ch4-64
HDL Example 4-1
Two-to-one-line decoder
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Digital System Ch4-65
HDL Example 4-2
Four-bit adder: bottom-up hierarchical description
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Digital System Ch4-66
HDL Example 4-2 (continued)
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Digital System Ch4-67
Three-State Gates
Statement: gate name (output, input, control);
Fig. 4.31 Three-state gates
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Digital System Ch4-68
Three-State Gates
Examples of gate instantiation
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Fig. 4.32 Two-to-one-line multiplexer with three-state buffers
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Digital System Ch4-70
Dataflow Modeling
Verilog HDL operators
Example:
assign Y = (A & S) | (B & ~S)
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Digital System Ch4-71
HDL Example 4.3
Dataflow description of a 2-to-4-line decoder
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Digital System Ch4-72
HDL Example 4-4
Dataflow description of 4-bit adder
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Digital System Ch4-73
HDL Example 4-5
Dataflow description of 4-bit magnitude comparator
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Digital System Ch4-74
HDL Example 4-6
Dataflow description of a 2-to-1-line multiplexer
Conditional operator (?:)
Condition ? True-expression : false-expression
Example: continuous assignment
assign OUT = select ? A : B
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Digital System Ch4-75
if statement: if (select) OUT = A;
HDL Example 4-7 Behavioral description of a 2-to-1-line multiplexer
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Digital System Ch4-76
HDL Example 4-8
Behavioral description of a 4-to-1-line multiplexer
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Digital System Ch4-77
Writing a Simple Test Bench
Initial block
Three-bit truth table
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Digital System Ch4-78
Writing a Simple Test Bench
Interaction between stimulus and design modules
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Digital System Ch4-79
Writing a Simple Test Bench
Stimulus module
System tasks for display
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Digital System Ch4-80
Syntax for $dispaly, $write, and $monitor:
Example:
Example:
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Digital System Ch4-81
HDL Example 4-9
Stimulus module
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Digital System Ch4-82
HDL Example 4-9 (Continued)
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Digital System Ch4-83
HDL Example 4-10
Gate-level description of a full adder
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Digital System Ch4-84
HDL Example 4-10 (Continued)