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Transcript of Chapter 4 Combinational Logic Design Principles. Overview Objectives -Define combinational logic...
![Page 1: Chapter 4 Combinational Logic Design Principles. Overview Objectives -Define combinational logic circuit -Analysis of logic circuits (to describe what.](https://reader030.fdocuments.in/reader030/viewer/2022033022/56649f0e5503460f94c233b3/html5/thumbnails/1.jpg)
Chapter 4
Combinational
Logic Design Principles
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OverviewObjectives- Define combinational logic circuit- Analysis of logic circuits (to describe what
they do)- Design of logic circuits from word
definition- Minimization or Simplification of logic
circuits- Mathematical Foundation of logic circuits (Boolean Algebra and switching theory)
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Introduction
• Two types of logic circuits– Combinational : output depends only on current inputs– Sequential : depends on current and past inputs
• Purpose of this chapter: conduct analysis on logic circuits to better understand them and to simplify circuits by:– Reducing the number of gates needed– And reducing the number of inputs of each gate
• Methods– Boolean algebra– Karnaugh or K-Maps– Tabular methods
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4.1. Boolean algebra(Switching Algebra )
• 1854: Georges Boole invented a two-valued algebraic system, now called Boolean algebra
• 1938: Claude E. Shannon adapted boolean algebra to analyse and describe circuit behavior
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4.1 Boolean algebra
• a.k.a. “switching algebra”– deals with boolean values -- 0, 1
• Positive-logic convention– analog voltages LOW, HIGH --> 0, 1
• Negative logic -- seldom used
• Signal values denoted by variables(X, Y, FRED, etc.)
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4.1 Boolean algebraBoolean operators
• Complement: X (opposite of X)• AND: X Y• OR: X + Y
• Axiomatic definition: A1-A5, A1-A5
binary operators, describedfunctionally by truth table.
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4.1 Boolean algebra Definitions
• Literal: a variable or its complement– X, X, FRED, CS_L
• Expression: literals combined by AND, OR, parentheses, complementation– X+Y– P Q R– A + B C– ((FRED Z) + CS_L A B C + Q5) RESET
• Equation: Variable = logic expressionExample: P = ((FRED Z) + CS_L A B C + Q5) RESET
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4.1 Boolean algebra Logic symbols
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4.1.1 Axioms (Basic Laws)
A1 X=0, if X 1 A’1 X=1, if X 0
A2 if X=0, then X’=1 A’2 if X=1 then X’=0
A3 0.0 = 0 A’3 1+1 = 1
A4 1.1 = 1 A’4 0+0 = 0
A5 0.1 = 1.0 = 0 A’5 1+0 = 0+1 = 1
Duality
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4.1.2 Single-Variable Theorems• Theorems for a single variable
T1 X+0 = X T1’ X.1 = X Identity
T2 X+1 = 1 T2’ X.0 = 0 Null
T3 X+X = X T3’ X.X = X Idempotency
T4 (X’)’ = X T4’ ----- Involution
T5 X+X’=1 T5’ X.X’=0 Complements
• Proof: X + 0 = X[X=0] 0+0 = 0 True, Axiom A’4 (0+0 = 0)[X=1] 1+0 = 1 True, Axiom A’5 (1+0 = 1)
All of the above can be proved using perfect induction
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4.1.3 Two- and three-Variable Theorems
T6 X+Y=Y+X T6’ X.Y=Y.X
T7 (X+Y)+Z=X+(Y+Z) T7’ (X.Y).Z=X.(Y.Z)
T8 X.Y+X.Z=X.(Y+Z) T8’ (X+Y).(X+Z)=X+Y.Z
T9 X+X.Y=X T9’ X.(X+Y)=X
T10 X.Y+X.Y’=X T10’ (X+Y).(X+Y’)=X
T11 X.Y+X’.Z+Y.Z T11’ (X+Y).(X’+Z).(Y+Z)= X.Y+X’.Z = (X+Y).(X’+Z) Consensus
Commutativity
Associativity
Distributivity
Covering
Combining
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4.1.3 Two- and three-Variable Theorems
• Proof of the covering theorem:
X + X . Y = X1) X + X . Y = X . 1 + X . Y (according to T1’)
2) = X . ( 1 + Y ) (according to T8)
3) = X . 1 (according to T2)
4) = X (according to T1’)
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4.1.3 Two- and three-Variable Theorems
• N.B. T8, T10, T11
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4.1.4 N-Variable Theorems
T12 X+X+…+X = XT12’ X . X . … . X = XT13 (X1.X2. … .Xn)’ =X1’+X2’+…+Xn’T13’ (X1+X2+…+Xn)’=X1’.X2’. … .Xn’
‘De Morgan’s Theorems are the most commonly used of all the theorems of switching algebra’
De Morgan’sTheorems
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4.1.4 N-variable Theorems
• Prove using finite induction• Most important: DeMorgan theorems
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4.1.4 n-Variable Theorems
Theorem T13 says:
An n-input AND gate whose output is complemented is equivalent to an n-input OR gate whose inputs are complemented
Examples: De Morgan’s Theorem
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4.1.5 DeMorgan Symbol Equivalence
Equivalent to
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4.1.5 De Morgan symbol …. Likewise for OR
Equivalent to
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4.1.5 DeMorgan Symbols
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4.1.6 Duality• Swap 0 & 1, AND & OR
– Result: Theorems still true
• Why?– Each axiom (A1-A5) has a dual (A1-A5
• Counterexample:X + X Y = X (T9)X X + Y = X (dual)X + Y = X (T3)????????????
X + (X Y) = X (T9)X (X + Y) = X (dual)(X X) + (X Y) = X (T8)X + (X Y) = X (T3)parentheses,operator precedence!
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4.1.6 Duality
• Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and . and + are swapped throughout.
• 0 –> 1, - –> +, 1 –> 0, + –> -• Example: duality: X+Y’+Z = X’.Y.Z’• Example:
F=(X’.Y’.Z’) + (X.Y’.Z’) + (X’.Y.Z)
By T10 (Y’.Z’) + (X’.Y.Z)
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4.1.6 Duality
• Example:F = A’BC’D’+ABC’D’ + ABC’D’+AB’C’D’+ABC’D+AB’C’D
F = BC’D’ + AC’D’ + AC’D
F = BC’D’ + AC’
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4.1.6 Standard Representation of Logic Functions
• Literal: variable or complement of variable– Ex: X, Y, X’, Y’
• Product term: literal or product of literal– Ex: Z’, X.Y, X.Y.Z
• Sum of products: logical sum of product terms– Ex: Z’+X.Y’+X.Y.Z’
• Sum term: literal or sum of literals– Ex: Z’, X+Y, X+Y’+Z
• Product of sums– Ex: Z.(X+Y).(X+Y’+Z)
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Standard Representation of Logic Functions
• Normal term: product or sum term in which no variable appears more than once– Ex: X.Y.Z– BAD ex: X.X’.Y.Z
• n-variable minterm: normal product term using n literals– Ex: 4-variable minterm (24 combinations)– WXYZ’, WXY’Z, WX’YZ’
• n-variable maxterm: normal sum with n literals– Ex: W+X+Y’+Z, W+X’+Y+Z’
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Standard Representation of Logic Functions
•Relation between minterms and maxterms
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4.2 Combinational-circuit analysis
• Canonical sum: sum of minterms corresponding to rows– Ex: F = x,y(0,1,2) = X’.Y’+X’.Y+X.Y’
• Canonical product: product of maxterms– Ex: F= x,y(1,3) = (X+Y’).(X’+Y’)
Row X Y F 0 0 0 1 1 0 1 0 2 1 0 0 3 1 1 1
Minterm X’.Y’X’.YX.Y’X.Y
Maxterm X+YX+Y’X’+YX’+Y’
•Representation of a 2-input function
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4.2 Combinational-circuit analysis
• The goal is to analyse and then reduce circuit.
• Several methods can be used :– boolean algebra – Karnaugh-Maps (K-Maps)
• Analysis– We can manipulate circuits using algebra– Then prove equality with truth tables
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4.2 Combinational-circuit analysis
Function F = ((X+Y’).Z) + (X’.Y.Z’)
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4.2 Combinational-circuit analysis
1 2 3 F X Y Z X’ Y’ Z’ X+Y’ 1.Z X’.Y.Z’ 2+30 0 0 1 1 1 1 0 0 00 0 1 1 1 0 1 1 0 10 1 0 1 0 1 0 0 1 10 1 1 1 0 0 0 0 0 01 0 0 0 1 1 1 0 0 01 0 1 0 1 0 1 1 0 11 1 0 0 0 1 1 0 0 01 1 1 0 0 0 1 1 0 1
Truth table
Function F = ((X+Y’).Z) + (X’.Y.Z’)
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4.2 Combinational-circuit analysis
Function F = ((X+Y’).Z) + (X’.Y.Z’)
Determine corresponding output values for different combinationsOf input values
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Combinational-circuit analysis
• Now, change to a sum of products
F = ( (X+Y’) . Z ) + (X’.Y.Z’)
F = X.Z + Y’.Z + X’.Y.Z’
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4.2 Combinational-circuit analysis
Function F = X.Z + Y’.Z + X’.Y.Z’
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4.2 Combinational-circuit analysis
1 2 3 F X Y Z X’ Y’ Z’ X.Z Y’.Z X’.Y.Z’ 1+2+30 0 0 1 1 1 0 0 0 00 0 1 1 1 0 0 1 0 10 1 0 1 0 1 0 0 1 10 1 1 1 0 0 0 0 0 01 0 0 0 1 1 0 0 0 01 0 1 0 1 0 1 1 0 11 1 0 0 0 1 0 0 0 01 1 1 0 0 0 1 0 0 1
Truth table
Function F = X.Z + Y’.Z + X’.Y.Z’
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4.2 Combinational-circuit analysis
There are many ways to make the same circuit by manipulating the functions or using equivalent gates to change circuit
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4.2 Combinational-circuit analysis
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4.3.3 Combinational circuit minimization
• Boolean Algebra Simplification
Example 1: F= A’(A+B)
F= (A’.A) + (A’.B) Distributivity T8
F= 0 + (A’.B) Complements
F= A’.B
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4.3.3Combinational circuit minimization
Example 2 : F= (A+B).(A+C)+A’.(A+B)F= A+(B.C) +A’.(A+B) Distributivity
T’8
F= A+(B.C) + (A’.B) Example 1
F= A + (A’.B) + (B.C) Change order
F= (A+A’).(A+B) + (B.C) Distribution
F= A+B + (B.C) Complements
F= A + B Covering
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4.3.3Combinational circuit minimization
Example 3 : F= ( ( (A.B)’.A)’.( (A.B)’.B)’)’
1) Use De Morgan: (A+B)’= A’.B’ or (A.B)’=A’+B’F= ((A.B)’.A) + ((A.B)’.B)
2) Use De Morgan:F= (A’+B’).A + (A’+B’).B
3) DistributivityF= A.A’ + A.B’ + A’.B + B.B’
4) ComplementF= A.B’+A’B
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4.3.4 Karnaugh Maps (K-Maps)
• A K-map is a graphical representation of a logic function truth table– The k-map is a standard method for
simplification of, the sum-of-products, or product-of-sums
– Based on combining adjacent minterm/maxterm
• Ex: (2-variable) mintermx
y 10
0
1
0
1
2
3
AA
B 10
0
1
1
0
1
0BA’.B’+A.B’=B’
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4.3.4 Example: 3-variable Karnaugh map
Y is 1 in this region, other columns represent y’
Z is 1 in this row, other row represents Z’
X is 1 in this region, other columns represent X’
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4.3.4 Karnaugh Maps (K-Maps)xy
z 01000
11 100
1 1 3 7 5
462
X
Z
Y B
ABC 0100 11 10
0
1
A
C
11
A B C minterms 0 0 0 A’B’C’ 0 0 1 A’B’C 0 1 0 A’BC’ 0 1 1 A’BC 1 0 0 AB’C’ 1 0 1 AB’C 1 1 0 ABC’ 1 1 1 ABC
A’BC’+ABC’=BC’
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4.3.4 Karnaugh-map usage
• Plot 1s corresponding to minterms of function.• Circle largest possible rectangular sets of 1s.
– # of 1s in set must be power of 2– OK to cross edges
• Read off product terms, one per circled set.– Variable is 1 ==> include variable– Variable is 0 ==> include complement of variable– Variable is both 0 and 1 ==> variable not included
• Circled sets and corresponding product terms are called “prime implicants”
• Minimum number of gates and gate inputs
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4.3.4 Karnaugh Maps (K-Maps)
WXYZ 0100
011 10
00
011
3
2
W
Z
X
4
5
7
6
12
13
15
14
8
9
11
10
11
10Y
ABCD 0100 11 10
00
01
A
D
B
11
10
C
1
1 1
1
1
Reduce from 5 terms sum: A’B’C’D+A’B’CD+AB’C’D’+AB’C’D +AB’CDTo a 2 terms sum: AB’C’ + BD’
Example: 4-variable
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4.3.4 Karnaugh Maps (K-Maps)
ABCD 0100 11 10
00
01
A
D
B
11
10
C
1
1 1
1
1
1
Reduce from 6 terms sumto 2 terms sum:BD + AB’D’
Example: 4-variable
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4.3.4 Karnaugh Maps (K-Maps)
ABCD 0100 11 10
00
01
A
D
B
11
10
C
1
1
1
11
11
Example: use K.maps to reduce the following:
F = ABCD+A’BCD+AB’CD+ABC’D+AB’C’D+A’B’CD’+A’B’C’D’
A’B’D’+BCD+AD
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4.3.4 Example: F = (1,2,5,7)
Corresponding Truth table
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4.3.4 Another example
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4.3.4 Yet another example
• Distinguished 1 cells• Essential prime implicants
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Prime implicant(Definitions)
• Prime implicant P is a normal product term that is an implicant of function F such that if any variable is removed from P, then the resulting product term does not imply F
• Prime implicant theorem: The sum of Prime implicants is the minimal sum
• Distinguished 1-cell: It is a cell that is covered by only one prime implicant
4.3.5 Minimizing Sums of Products
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• Essential Prime Implicant: it is the prime implicant that covers one or more distinguished 1-cells.
Prime implicant(Definitions)
4.3.5 Minimizing Sums of Products
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• Ex: F= W,X,Y,Z(1,3,4,5,9,11,12,13,14,15)
• Identify distinguished 1-cell and the corresponding essential prime implicant. If all of 1 are covered, stop we have the minimal sum.
• Remove essential prime implicant off => reduced map
• Select PIs (larger groups) to cover the remaining ones
0100 11 10
00
01
11
10
1
1
1
11
1
1
1
1
1
WXYZ 0100
011 10
00
011
3
2
W
Z
X
4
5
7
6
12
13
15
14
8
9
11
10
11
10Y
4.3.5 Minimizing Sums of Products
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Example: F= W,X,Y,Z(0,1,2,3,4,5,7,14,15)
0100 11 10
00
01
11
10
1
1
1
1
1
1
1
11
0100 11 10
00
01
11
10
1Try to put this 1 in the largest possible group
• Identify distinguished 1-cell and the corresponding essential prime implicant. If all of 1 are covered, stop we have the minimal sum.
• Remove essential prime implicant off => reduced map
• Select PIs (larger groups) to cover the remaining ones
4.3.5 Minimizing Sums of Products
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4.3.7 Don ’t care conditions
x1 x2 x3 x4 y1 y2 y3 y4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 … … 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 d d d d … … 1 1 1 1 d d d d
BCDgenerator
We don’t care what the Output value is for these rows
4.3.5 Minimizing Sums of Products
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Don ’t care conditions
• Sometimes the specification of a CLN is such that its output does not matter for certain input combinations.
These cases called do not care conditions. Any d can be treated as either 0 or 1. They are useful during simplification.
4.3.5 Minimizing Sums of Products
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Brute-force design
• Truth table --> canonical sum (sum of minterms)
• Example:prime-number detector– 4-bit input, N3N2N1N0
row N3 N2 N1 N0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 010 1 0 1 0 011 0 0 1 1 112 1 1 0 0 013 1 1 0 1 114 1 1 1 0 015 1 1 1 1 0
F = (1,2,3,5,7,11,13)
4.3.6 Example of design
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Minterm list --> canonical sum4.3.6 Example of design
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Algebraic simplification
• Theorem T8,
• Reduce number of gates and gate inputs
4.3.6 Example of design
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Resulting circuit4.3.6 Example of design
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Prime-number detector (again) K-map solution
4.3.6 Example of design
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• When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.
Prime-number detector (again) K-map solution
4.3.6 Example of design