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Chapter 11 (I)access.ee.ntu.edu.tw/course/vlsi_design_92first/ppt... · 2010. 7. 14. · Arithmetic...
Transcript of Chapter 11 (I)access.ee.ntu.edu.tw/course/vlsi_design_92first/ppt... · 2010. 7. 14. · Arithmetic...
EE1411
Arithmetic Circuits
Chapter 11 (I)Chapter 11 (I)
Arithmetic Circuits:Arithmetic Circuits:Adder DesignsAdder DesignsRev. 1.0 05/12/2003Rev. 2.0 06/05/2003Rev. 2.2 12/31/2003
EE1412
Arithmetic Circuits
A Generic Digital ProcessorA Generic Digital Processor
MEM ORY
DATAPATH
CONTROL
INPU
T-O
UT
PUT
EE1413
Arithmetic Circuits
Building Blocks for Digital ArchitecturesBuilding Blocks for Digital Architectures
Arithmetic and Unit- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory- RAM, ROM, Buffers, Shift registers
Control- Finite state machine (PLA, random logic.)- Counters
Interconnect- Switches- Arbiters- Bus
EE1414
Arithmetic Circuits
Intel MicroprocessorIntel Microprocessor
9-1
Mux
9-1
Mux
5-1
Mux
2-1
Mux
ck1
CARRYGEN
SUMGEN+ LU
1000um
b
s0
s1
g64
sum sumb
LU : LogicalUnit
SUM
SEL
a
to Cachenode1
REG
Itanium has 6 integer execution units like this
EE1415
Arithmetic Circuits
BitBit--Sliced DesignSliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Reg
ister
Add
er
Shift
er
Mul
tiple
xer
ControlD
ata-
In
Dat
a-O
ut
Tile identical processing elements
Word Data Word Data
EE1416
Arithmetic Circuits
ItaniumItanium IntegerInteger DatapathDatapath
Fetzer, Orton, ISSCC’02
EE1417
Arithmetic Circuits
AddersAdders
EE1418
Arithmetic Circuits
Several Implementations of AddersSeveral Implementations of AddersOne-Bit Full Adder (Cell)Carry-Ripple AdderBit-Serial AdderMirror AdderTransmission-Gate AdderManchester AdderCarry-bypass (Carry-skip) AdderCarry-Select AdderCarry lookahead AdderConditional-sum Adder (supplement material)
EE1419
Arithmetic Circuits
FullFull--Adder (FA)Adder (FA)A B
Cout
Sum
Cin Fulladder
Generate (G) = AB
Propagate (P) = A ⊕ B
Delete = A B
EE14110
Arithmetic Circuits
Boolean Function of Binary FullBoolean Function of Binary Full--Adder Adder
iiii
i
ABCCBACBACBA
CBAS
+++=
⊕⊕=
ACBCABC iiO ++=A B
Cout
Sum
Cin Fulladder
)( iii CBACABCS +++=
)( BACABC iO ++= For CMOS Implementation
EE14111
Arithmetic Circuits
Express Sum and Carry as a function of P, G, DExpress Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = ABPropagate (P) = A ⊕ BDelete = A B
Can also derive expressions for S and Co based on D and P
Propagate (P) = A + BNote that we will be sometimes using an alternate definition for
EE14112
Arithmetic Circuits
CarryCarry--Ripple AdderRipple Adder
Worst-case delay is linear with the number of bits
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(= Ci,1)
Co,1 Co,2 Co,3
td = O(N)tadder = (N-1)tcarry + tsum
CriticalPath
• Propagation delay (or critical path) is the worst-case delay over all possible input patterns
• A= 0001, B=1111, trigger the worst-case delay• A: 0 1, and B= 1111 fixed to set up the worst-
case delay transition.
EE14113
Arithmetic Circuits
Complimentary Static CMOS Full AdderComplimentary Static CMOS Full Adder
•Logic effort of Ci is reduced to 2 (c.f., A and B signals)•Ci is late arrival signal near the output signal•Co needs to be inverted Slow down the ripple propagate
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
SOC=
28 Transistors
EE14114
Arithmetic Circuits
Inversion PropertyInversion Property
A B
S
CoCi FA
A B
S
CoCi FA
EE14115
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages
•Exploit Inversion Property•Reduce One inverter delay in each Full-adder (FA) unit
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3Co,2
EE14116
Arithmetic Circuits
SubtractorSubtractor[ ] 11)'1(
)'2(++=++=
+=−
BABofsABofsABA
EE14117
Arithmetic Circuits
BitBit--Serial AdderSerial Adder
012345 aaaaaaA =
012345 bbbbbbB =
012345 ssssssS =
• Bit-serial design trades time for area efficiency• Circuit operates at bit rate (N times faster than
word rate for an N-bit data)• Need a controller (counter) for counting the serial data bits
EE14118
Arithmetic Circuits
A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder
Exploring the “Self-Duality” of the Sum and Carry functions
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors!
)( iii CBACABCS +++=
)( BACABC iO ++= )( BACABC iO ++=
)( iii CBACABCS +++=
EE14119
Arithmetic Circuits
Mirror Adder: Stick DiagramMirror Adder: Stick Diagram
CiA B
VDD
GND
B
Co
A Ci Co Ci A B
S
EE14120
Arithmetic Circuits
Mirror Adder DesignMirror Adder Design•The NMOS and PMOS chains are completely symmetrical
•A maximum of two series transistors can be observed in the carry-generation circuitry for good speed.
•The transistors connected to Ci are placed closest to the output.
•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co.
•The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six input gate capacitances, in the connecting adder cell .
EE14121
Arithmetic Circuits
Sizing for Mirror AdderSizing for Mirror Adder• Increase the size of the Carry Stage to about 3 or 4
times the size of the Sum Stage (PMOS/NMOS ratio of 2 is assumed)
EE14122
Arithmetic Circuits
Review of TGReview of TG--based 6T XOR Gatebased 6T XOR Gate
011101110000
FBA
B
B
Truth Table
A=0: Pass B SignalA=1: Inverting B Signal
B
B
EE14123
Arithmetic Circuits
Review of FullReview of Full--Adder (FA)Adder (FA)A B
Cout
Sum
Cin Fulladder
Generate (G) = AB
Propagate (P) = A ⊕ B
Delete = A B
EE14124
Arithmetic Circuits
TransmissionTransmission--Gate Full Adder (24T)Gate Full Adder (24T)
•Same delay for Sum and Carry Good for Multiplier design
BAP ⊕=
ii
i
PCCP
CPS
+=
⊕=
APCPC iO ⋅+⋅=
EE14125
Arithmetic Circuits
Manchester CarryManchester Carry--Chain AdderChain Adder
CoCi
Gi
DiPi
Pi
VDD
CoCi
Gi
Pi
VDD
φ
φ
Static CircuitsDynamic Circuits
iiiO DGCPC ⋅+⋅= )(
+⋅==
==
,,1
,1,0
iiiO
O
GCPC
C
φ
φ
EE14126
Arithmetic Circuits
Manchester Carry ChainManchester Carry Chain
G2
φ
C3
G3Ci,0
P0
G1
VDD
φ
G0
P1 P2 P3
C3C2C1C0
Ci = 4 diffusion cap + 2 gate cap
EE14127
Arithmetic Circuits
Manchester CarryManchester Carry--Chain AdderChain Adder
Pi + 1 Gi + 1 φ
Ci
Inverter/Sum Row
Propagate/Generate Row
Pi Gi φ
Ci - 1Ci + 1
VDD
GND CCRR
RCNN
RCt
ij
i
jj
N
iiP
==
+=
⋅= ∑∑
==
, where2
)1(69.0
69.011
EE14128
Arithmetic Circuits
Manchester Adder Circuits (Cont.)Manchester Adder Circuits (Cont.)
Dynamic stageWhen CLK is low, the output node is pre-charged by the p pull-up transistor.When CLK goes high, the pull-down transistor turns on.If carry generate G=AB is true → the output node discharges.If carry propagate P=A+B is true → a previous carry may be coupled to the output node, conditionally discharging it.
Static stageThis requires P to be generated as A⊕BThe Manchester adder stage improves on the carry-lookahead implementation.
EE14129
Arithmetic Circuits
CarryCarry--Bypass (CarryBypass (Carry--skip) Adderskip) Adder
Idea: If (P0 ^ P1 ^ P2 ^ P3 = 1), then Co,3= C0
else ”kill” or “generate”
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
ti pl e
xer
BP=PoP1P2P3
EE14130
Arithmetic Circuits
Manchester Bypass Adder Circuits Manchester Bypass Adder Circuits
Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free
The control signals T1,T2,and T3 shown in Fig6(b) are generated by:
T1 = -(P0P1P2)P3T2 = -P3T3 = P0P1P2P3
Wired-OR node
EE14131
Arithmetic Circuits
Delay DefinitionDelay Definitiontsetup: the fixed overhead time to create the “generate” and “propagate” signalstcarry: the propagation delay through a single bit. The worst case carry-propagation delay through a single stage of M bits is approximately M times largertbypass: the propagation delay through the bypass multiplexer of a single stagetsum: the time to generate the sum of the final stage
EE14132
Arithmetic Circuits
CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)
Carrypropagation
SetupBit 0–3
Sum
M bits
tsetup
tsum
Carrypropagation
SetupBit 4–7
Sum
tbypass
Carrypropagation
SetupBit 8–11
Sum
Carrypropagation
SetupBit 12–15
Sum
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
M bits form a Section (N/M) Bypass Stages
EE14133
Arithmetic Circuits
Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass
N
tp
ripple adder
bypass adder
4..8
Wordlength (N) > 4~8 is better for Bypass Adder
EE14134
Arithmetic Circuits
CarryCarry--Select Adder (4Select Adder (4--bit stage) bit stage) Setup
"0" Carry Propagation
"1" Carry Propagation
Four 2-to-1 Multiplexer
Sum Generation
Co,k-1 Co,k+3
"0"
"1"
P,G
Carry Vector
EE14135
Arithmetic Circuits
CarryCarry--Select AdderSelect Adder
Fig7. Carry-select adder:(a) basic architecture (b) 32-bit carry-select adder example
EE14136
Arithmetic Circuits
Carry Select Adder: Critical PathCarry Select Adder: Critical Path
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry
Setup
Ci,0 Co,3 Co,7 Co,11 Co,15
S0–3
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry
Setup
S4–7
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry 0-Carry
Setup
S8–11
0
1
Sum Generation
Multiplexer
1-Carry
Setup
S12–15
summuxcarrysetupadd ttMtMNtt +⋅+⋅
+=
EE14137
Arithmetic Circuits
Linear Carry Select Linear Carry Select
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
S0-3 S4-7 S8-11 S12-15
Ci,0
(1)
(1)
(5)(6) (7) (8)
(9)
(10)
(5) (5) (5)(5)
EE14138
Arithmetic Circuits
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13
S0-1 S2-4 S5-8 S9-13
Ci,0
(4) (5) (6) (7)
(1)
(1)
(3) (4) (5) (6)
Mux
Sum
S14-19
(7)
(8)
Bit 14-19
(9)
(3)
Square Root Carry SelectSquare Root Carry Select
N-bit adder with P stages, 1st stage adds M bits
NPPNMPPPPMP
PMMMMN
22
)21(
22)1(
)1()2()1(22
≈⇒≈⇒−+=−
+=
−+++++++=
summuxcarrysetupadd ttNMttt +++= )2(
EE14139
Arithmetic Circuits
Adder Delays Adder Delays -- Comparison Comparison
Square root select
Linear select
Ripple adder
20 40N
t p(in
uni
t del
ays)
600
10
0
20
30
40
50
EE14140
Arithmetic Circuits
CarryCarry--LookaheadLookahead AddersAdders
The linear growth of adder carry-delay with the size of the input word for n-bit adder maybe improved by calculation the carries to each stage in parallel.
EE14141
Arithmetic Circuits
Carry of the ith stage ---
Ci=Gi + PiCi-1Gi=AiBi generate signalPi=Ai + Bi propagate signal
ExpandingCi= Gi + PiCi-1 + PiPi-1Gi-2 + ….. + Pi…P1P0
For four stages, the appropriate term :
C0= G0 + P0CIC1= G1 + P1G0 + P1P0CIC2= G2 + P2G1 + P2P1G0 + P2P1P0CIC3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI
Carry-Lookahead Adders (Cont.)
Fig1. Generic carry-lookahead adder
eDecorrelat),,( 03 ⇒= CPGfC ii
EE14142
Arithmetic Circuits
EE14143
Arithmetic Circuits
LookLook--ahead Adder ahead Adder -- Basic IdeaBasic IdeaAN-1, BN-1A1, B1
P1
S1
• • •
• • • SN-1
PN-1Ci, N-1
S0
P0Ci,0 Ci,1
A0, B0
)))((()(
),,(
0,00111,
2,11,
1,1,,
ikkkkkO
kOkkkkkO
kOkkkOkkkO
CPGPPGPGCCPGPGC
CPGCBAfC
++⋅+⋅+=
⋅+⋅+=
⋅+==
−−
−−−
−−
…
EE14144
Arithmetic Circuits
Static CMOS CircuitsStatic CMOS Circuits
Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=
Co k, Gk Pk Gk 1– P k 1– … P1 G0 P0 Ci 0,+( )+( )+( )+=
Expanding Lookahead equations:
All the way:
Co,3
Ci,0
VDD
P0
P1
P2
P3
G0
G1
G2
G3
EE14145
Arithmetic Circuits
Dynamic Carry Gates
• The worst-case delay path in this circuit has six n-transistor in series.
EE14146
Arithmetic Circuits
Carry-Lookahead Adders
• The size and fan-in of the gates needed to implement this carry-lookahead scheme can clearly get out of hand as bit number increases.
• The number of stages of lookahead is usually limited to about 4.
• The circuit and layout are quite irregular compared with Ripple-carry Adder
EE14147
Arithmetic Circuits
Conditional Sum AddersConditional Sum AddersThe switch-like structuresUsing pass-transistor logic to achieve an addition time significantly faster than a ripple-carry adder.This operation cannot be completed until ci-1, the carry-out of the (i-1)-th position, is available.Instance of waiting for the arrival of the carry value, conditional sum and conditional carry are generated by considering both possible values of the carry-in bit.All conditional sums and conditional carries can be generated in parallel
1
011
00
++=
++=
iiii
iiii
baSCbaSC
EE14148
Arithmetic Circuits
Example 1Example 1A=(1101101)2 and B=(0110110)2
Sum=(10100011)2 , Cout=1
01
10
1
0
Bit1
01
11
01
01
11
01
Si1
Ci1
10
01
10
10
01
10
Si0
Ci0
010110B
111011A
Bit0Bit2Bit3Bit4Bit5Bit6
C-1=0
EE14149
Arithmetic Circuits
Example 2Example 2A=(1101101)2 and B=(0110110)2
Sum=(10100011)2 , Cout=1
0
11
0
Bit1
01
11
001
101
Si1
Ci1
10
01
110
001
Si0
Ci0
010110B
111011A
Bit0Bit2Bit3Bit4Bit5Bit6
C-1=0
EE14150
Arithmetic Circuits
MultiMulti--levels levels The number of bits grouped together is equal to 2l at level l.
10
101
11001
Si0(2)
Ci0(2)
01
011
00101
Si1(2)
Ci1(2)
10
101
110
001
Si0(1)
Ci0(1)
01
011
001
101
Si1(1)
Ci1(1)
01
01
11
01
01
11
01
Si1(0)
Ci1(0)
10
10
01
10
10
01
10
Si0(0)
Ci0(0) C-1=0
EE14151
Arithmetic Circuits
TwoTwo--level 3level 3--bit Conditional Sum Adderbit Conditional Sum Adder
ConditionalCell
ConditionalCell
ConditionalCell
MUX MUX MUX MUX MUX MUX
MUX MUX MUX
a2 b2 a1 b1 a0 b0
C21 C20 S21 S20 C11 C10 S11 S10 C01 C00 S01 S00
c-1
c2 s2 s1 s0
EE14152
Arithmetic Circuits
Summary Summary Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs.Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.For details, check “Advanced VLSI Design”notes, or “Computer Arithmetic” textbooks