Lab07 Memory Controller - access.ee.ntu.edu.tw

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Memory ControllerMemory Controller

Speaker: Lung-Hao Chang 張龍豪Advisor: Prof. Andy Wu 吳安宇教授

April 16, 2003

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

SoC Design Laboratory PP. 104/16/2003

Goal of This LabGoal of This Lab

Ø Familiarize with ARM Integrator memory mapØ How to access memory



OutlineOutline

Ø The ARM Memory Interface [1]Ø ARM Integrator System Memory Map [2] [3]Ø Lab – Memory Controller



Simple Memory InterfaceSimple Memory Interface

Ø The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM).

Ø 8-bit memory types, so four parts of each type are required to form a 32-bit memory.

Ø Since the bottom two address lines, A[1:0], are used for byte selection, they are used by the control logic and not connected to the memory.

Ø Although the ARM performs reads of both bytes and words, the memory system can ignore the difference and always simply supply a word quantity.



Basic ARM Memory SystemBasic ARM Memory System

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

control

D[7:0]

D[31:0] D[31:24] D[23:16] D[15:8] D[7:0]

A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2]

A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2]

RAMoe

RAMwe3 RAMwe2 RAMwe1 RAMwe0

ROMoe

ARM

D[31:0]

A[31:0] oe we

A[n

:0]

oe we

A[n

:0]

oe we

A[n

:0]

oe we

A[n

:0]

A[n

:0]

oeA[n

:0]

oeA[n

:0]

oeA[n

:0]

oe

A[3

1:0]

vario

us



Control LogicControl Logic

Ø It decides when to activate the ARM and when to activate the ROMqA[31] = 0 => access ROMqA[30] = 1 => access RAM

Ø It controls the byte write enables during a write operationqWord write / half-word write / byte

Ø It ensures that the data is ready before the processor continuesqThe simplest solution is to run mclk slowly enough to ensure

that all the memory devices can be accessed within a single clock cycle



Simple ARM Memory System Control LogicSimple ARM Memory System Control Logic

RAMwe0

RAMwe1

RAMwe2

RAMwe3

mclk

A[0] A[1]mas[0] mas[1]

RAMoe

ROMoe

A[31]

r/w



Transfer WidthsTransfer Widths

Half word (RAMwe2, RAMwe3)

Half word (RAMwe0, RAMwe1)

Word (RAMwe0, RAMwe1,RAMwe2, RAMwe3)

None

Output signal

×

×

×

×

×

A[0]

1

0

×

×

×

A[1]

1

1

0

1

0

mas[0]

0

0

1

1

0

mas[1]



DRAM memory organizationDRAM memory organization

ras

cas

A[n:0]

dataout

array ofmemory

cells

mux

latc

hla

tch

deco

der



DRAM Timing IllustrationDRAM Timing Illustration

mclk

A[31:0]

seq

wait

ras

cas

A A+4 A+8

S cycle S cycleN cycle

D[31:0]



OutlineOutline

Ø The ARM Memory InterfaceØ ARM Integrator System Memory MapØ Lab – Memory Controller



Core Module Memory MapCore Module Memory Map

Ø The nMBDET signal is permanently grounded by the motherboard so that it is pulled LOW on the core module when it is fitted.

Ø The REMAP bit only has effect if the core module is attached to a motherboard (nMBDET = 0).



Core Module Memory Map (cont.)Core Module Memory Map (cont.)

256MB

256KB

8MB

8MB



Core Module Alias AddressCore Module Alias Address



Memory Map for Core ModuleMemory Map for Core Module

Ø REMAP = 0: Default following reset. Accesses to addresses 0x00000000 to 0x0003FFFFq S1[1] = ON: the access is to boot ROMq S1[1] = OFF: the access is to flash

Ø REMAP = 1: Accesses to address 0x00000000 to 0x0003FFFF



Memory Map for Logic ModulesMemory Map for Logic Modules

Ø S[1] = ON: the EBI resources are mapped into the bottom 256MB of the system memory map.

Ø S1[1] = OFF: the flash is mapped repeatedly into bottom 256MB of the system memory map.



System Memory Map (1/3)System Memory Map (1/3)



OutlineOutline

Ø The ARM Memory InterfaceØ ARM Integrator System Memory MapØ Lab – Memory Controller



Lab 7: Memory ControllerLab 7: Memory ControllerØ Goalq Realize the principle of

memory map and internal and external memory

Ø Principlesq System memory mapq Core Module Control

Registerq Core Module Memory Map

Ø Guidanceq We use a simple program

to lead student understanding the memory.

Ø Requirements and ExercisesqModify the memory usage

example. Use timer to count the total access time of several data accessing the SSRAM and SDRAM. Compare the performance between using SSRAM and SDRAM.

Ø Discussionq Discuss the following items

about Flash, RAM, and ROM.vSpeed vCapacity v Internal /External



ReferencesReferences

[1] ARM System-on-Chip Architecture by S.Furber, Addison Wesley Longman: ISBN 0-201-67519-6.

[2] http://www.arm.com/arm/User_Guides/DUI0098B_AP_UG.pdf.

[3] http://www.arm.com/support/4XHLQX/$File/DUI0126B_CM7TDMI_UG.pdf

Lab07 Memory Controller - access.ee.ntu.edu.tw

Documents

Transcript of Lab07 Memory Controller - access.ee.ntu.edu.tw