COURSE STRUCTURE & SYLLABUS M.Tech ECE VLSI, VLSI Design ...
Chapter 3 VLSI Design -...
Transcript of Chapter 3 VLSI Design -...
-
10/21/2003 Devices
Chapter 3Chapter 3VLSI DesignVLSI Design
The DevicesThe Devices
March 28, 2003Rev.1: 3/29/03Rev.2: 10/20/03
-
10/21/2003 Devices
Goal of this chapterGoal of this chapter
Present intuitive understanding of device operationIntroduction of basic device equationsIntroduction of models for manual analysisIntroduction of models for SPICE simulationAnalysis of secondary and deep-sub-micron effectsFuture trends
-
10/21/2003 Devices
The DiodeThe Diode
n
p
p
n
B A SiO2Al
A
B
Al
A
B
Cross-section of pn - junction in an IC process
One-dimensionalrepresentation diode symbol
Mostly occurring as parasitic element in Digital ICs
-
10/21/2003 Devices
Depletion RegionDepletion Regionhole diffusion
electron diffusion
p n
hole driftelectron drift
ChargeDensity
Distancex+
-
ElectricalxField
x
PotentialV
ξ
ρ
W2-W1
ψ0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostaticpotential.
-
10/21/2003 Devices
Forward BiasForward Bias
x
pn0
np0
-W1 W20p n
(W2)
n-regionp-region
Lp
diffusion
Typically avoided (seldom used) in Digital ICs
Excess Minority Carrier
-
10/21/2003 Devices
Reverse BiasReverse Bias
x
pn0
np0
-W1 W20n-regionp-region
diffusion
The Dominant Operation Mode
-
10/21/2003 Devices
Diode Current (Ideal Diode Equation)Diode Current (Ideal Diode Equation)
•Is: Saturation Current• : Thermal Voltage•VD: Voltage drop over Diode
Tφ 300Kat 26/ mVqkTT ≈=φ
-
10/21/2003 Devices
Models for Models for Manual AnalysisManual Analysis
VD
ID = IS(eVD/φT -1)+
-
VD
+
-
+
-VDon
ID
(a) Ideal diode model (b) First-order diode model
•1st-order model is important for early-stage analysis•VD,on = 0.7V for manual analysis•Otherwise, you need to solve non-linear equations to find ID
-
10/21/2003 Devices
Dynamic, or Transient BehaviorDynamic, or Transient Behavior
Junction Capacitance in Reversed BiasJunction Capacitance in Reversed Bias
m : grading coefficient
-
10/21/2003 Devices
Diffusion Capacitance (forward bias)Diffusion Capacitance (forward bias)
-
10/21/2003 Devices
Secondary Effects of DiodeSecondary Effects of Diode
–25.0 –15.0 –5.0 5.0VD (V)
–0.1
I D(A
)0.1
0
0
Avalanche Breakdown
-
10/21/2003 Devices
Diode ModelDiode Model
ID
RS
CD
+
-
VD
Symbol
For Circuit Simulation(IC Designers)
Modeling(SPICE)
IC Manufacturer(TSMC, UMC)
-
10/21/2003 Devices
SPICE MODELS• SPICE: Simulation Program with Integrated Circuit
Emphasis, by UCB in early 1970’s.• Level 1: Long Channel Equations - Very Simple
• Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations (Short channel considered)
• Level 3: Semi-empirical - Based on curve fitting to measured devices
• Berkeley Short-Channel IGFET Model (BSIM3v3): Empirical – Industrywide standard for modeling deep-submicron MOSFET transistors.
• Full-fledged BSIM3v3 model (denoted as LEVEL 49) covers over 200 parameters.
-
10/21/2003 Devices
SPICE ParametersSPICE Parameters
-
10/21/2003 Devices
What is a Transistor?What is a Transistor?
VGS ≥ VTRon
S D
A Switch!
|VGS|
An MOS Transistor
-
10/21/2003 Devices
The MOS TransistorThe MOS TransistorPolysilicon
Aluminum/Cu
-
10/21/2003 Devices
MOS Transistors MOS Transistors --Types and SymbolsTypes and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS withBulk Contact (4-terminal MOS)
-
10/21/2003 Devices
Threshold Voltage: ConceptThreshold Voltage: Concept
n+n+
p-substrate
DSG
B
VGS+
-
DepletionRegion
n-channel
-
10/21/2003 Devices
Threshold VoltageThreshold Voltage
-
10/21/2003 Devices
Body Effect (New Tool for LowBody Effect (New Tool for Low--Power Design)Power Design)
-2.5 -2 -1.5 -1 -0.5 00.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
VBS
(V)
VT (V
)
-
10/21/2003 Devices
Transistor in LinearTransistor in Linear
n+n+
p-substrate
D
SG
B
VGS
xL
V(x) +–
VDS
ID
MOS transistor and its bias conditions
-
10/21/2003 Devices
Transistor in SaturationTransistor in Saturation
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
Pinch-off
-
10/21/2003 Devices
CurrentCurrent--Voltage RelationsVoltage Relations(Long(Long--channel Device)channel Device)
QuadraticRelationship
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
Linear/
-
10/21/2003 Devices
CurrentCurrent--Voltage RelationsVoltage RelationsLongLong--Channel DeviceChannel Device
Kn: gain factor of the MOS
-
10/21/2003 Devices
A model for manual analysisA model for manual analysis
-
10/21/2003 Devices
CurrentCurrent--Voltage RelationsVoltage RelationsThe DeepThe Deep--SubmicronSubmicron Era (short channel MOSEra (short channel MOS
LinearRelationship
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
-
10/21/2003 Devices
Velocity SaturationVelocity Saturation
ξ (V/µm)ξc = 1.5
υn
( m/s
)
υsat = 105
Constant mobility (slope = µ)
Constant velocity
S/D: only need 2V to reach the saturation point in 0.25um process
-
10/21/2003 Devices
PerspectivePerspective
IDLong-channel device
Short-channel device
VDSVDSAT VGS - VT
VGS = VDD
VDSAT: VDS whenVelocity saturationhappen
-
10/21/2003 Devices
IIDD versus Vversus VGSGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10-4
VGS(V)
I D(A
)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10-4
VGS(V)
I D(A
)
quadratic
quadratic
linear
Long Channel Short Channel
-
10/21/2003 Devices
IIDD versus Vversus VDSDS
-4
VDS(V)0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10-4
VDS(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
Long Channel Short Channel
-
10/21/2003 Devices
Unified model for manual analysisUnified model for manual analysis
S D
G
B
-
10/21/2003 Devices
Simple Model versus SPICE Simple Model versus SPICE
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VDS (V)
I D(A
)
VelocitySaturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
Solid Line:Simple model
Dotted Line:SPICE SimulationResults(Empirical)
-
10/21/2003 Devices
A PMOS TransistorA PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D(A
)
Assume all variablesnegative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
-
10/21/2003 Devices
Transistor Model Transistor Model for Manual Analysisfor Manual Analysis
-
10/21/2003 Devices
SubSub--Threshold ConductionThreshold Conduction
0 0.5 1 1.5 2 2.510
-12
10-10
10-8
10-6
10-4
10-2
VGS (V)
I D(A
)
VT
Linear
Exponential
Quadratic
Typical values for S:60 .. 100 mV/decade
The Slope Factor
ox
DnkTqV
D CCneII
GS
+=1 ,~ 0
S is ∆VGS for ID2/ID1 =10
-
10/21/2003 Devices
VDS from 0 to 1.0V
SubSub--Threshold Threshold IIDD vsvs VVDSDS( )DSkT
qVnkT
qV
D VeeIIDSGS
⋅+
−=
−λ110
-
10/21/2003 Devices
( )DSkTqV
nkTqV
D VeeIIDSGS
⋅+
−=
−λ110
VGS from 0 to 0.3V
SubSub--Threshold Threshold IIDD vsvs VVGSGS
-
10/21/2003 Devices
Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions
Strong Inversion VGS > VTLinear (Resistive)
VDS < VDSATSaturated (Constant Current)
VDS ≥VDSATWeak Inversion (Sub-Threshold) VGS ≤VT
Exponential in VGS with linear VDS dependenceLeakage current cannot be ignored
-
10/21/2003 Devices
MOS Transistor as a SwitchMOS Transistor as a SwitchVGS ≥ VT
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
)(21
Omideq RRR +=
-
10/21/2003 Devices
MOS Transistor as a Switch (contMOS Transistor as a Switch (cont’’d)d)
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req
(Ohm
)
VDS
-
10/21/2003 Devices
The Transistor as a SwitchThe Transistor as a Switch
-
10/21/2003 Devices
MOS CapacitancesMOS Capacitances
-
10/21/2003 Devices
Dynamic Behavior of MOS TransistorDynamic Behavior of MOS Transistor
DS
G
B
CGDCGS
CSB CDBCGB
-
10/21/2003 Devices
The Gate CapacitanceThe Gate Capacitance
tox
n+ n+
Cross section
L
Gate oxide
xd xd
L d
Polysilicon gate
Top view
Gate-bulkoverlap
Source
n+
Drain
n+W
Overlap Capacitance
WCWxCACCC
dOX
OXGDGS
0
00
====
000 gdgs CCC == : overlap cap
per unit transistor width
-
10/21/2003 Devices
Gate Capacitance (Cg)Gate Capacitance (Cg)
S D
G
CGCS D
G
CGCS D
G
CGC
Cut-off Resistive Saturation
Cutoff SaturationTriode
WCCCCC gdgsgbg 02)( +++=
-
10/21/2003 Devices
Diffusion (Junction) Capacitance: S/DDiffusion (Junction) Capacitance: S/D
Bottom
Side wall
Side wallChannel
SourceND
Channel-stop implantNA+
Substrate NA
W
xj
L S
-
10/21/2003 Devices
Junction CapacitanceJunction Capacitance
m: grading coefficient
-
10/21/2003 Devices
Capacitances in 0.25 Capacitances in 0.25 µµm CMOS m CMOS processprocess
-
10/21/2003 Devices
Parasitic ResistancesParasitic Resistances(Source(Source--Drain Resistance)Drain Resistance)
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
Employ Silicidation: Slicided Source/Drain
3.47) (Eq.,, CDS
DS RRWL
R += ∆
-
10/21/2003 Devices
SecondSecond--order Effect in Deep Suborder Effect in Deep Sub--Micron MOS TransistorMicron MOS Transistor
Threshold Variations (p.114)Hot-Carrier Effects (p.115)For reference only
-
10/21/2003 Devices
SPICE Transistors Parameters
-
10/21/2003 Devices
MAIN MOS SPICE PARAMETERS
-
10/21/2003 Devices
SPICE Parameters for Parasitics
-
10/21/2003 Devices
SPICE Model for NMOS and PMOSSPICE Model for NMOS and PMOS
-
10/21/2003 Devices
SPICE Deck for a CMOS InverterSPICE Deck for a CMOS Inverter
-
10/21/2003 Devices
SPICE Simulation ResultSPICE Simulation Result
-
10/21/2003 Devices
Process VariationProcess Variation
Variations in process parameters: impurities, oxide thickness, diffusion depth, etc. sheet resistance, Vt,…Variations in dimensions of the devices: due to limited resolution of lithography W, L, Width of Interconnection wiresFast and slow device models are created in addition to the nominal ones larger of smaller currents of the device (3 variations)σ
-
10/21/2003 Devices
Process VariationsProcess Variations
-
10/21/2003 Devices
Future PerspectivesFuture Perspectives
25 nm FINFET MOS transistor
-
10/21/2003 Devices
SummarySummaryTransistor Modeling is important for CMOS circuit design (updated by IC manufacturing companies based on ongoing technologies).
SPICE parameters provide a good link between manufacturer and IC designers.SPICE model/parameters need to be updated to reflect the behavior of the MOS in deep sub-micron technology.
Recently, capacitor/inductor modeling become important for Radio-frequency (RF) designs.