CET335 MICROPROCESSOR INTERFACINGjsumey/CET335/notes/Ch1-MCUoverview.pdf · the HC08 and HC/S12...

CET335

MICROPROCESSOR INTERFACING

Chapter 1:

MPU Architecture Overview

Microprocessor Interfacing Ch. 1: HC11 Overview

Copyright © 2011 J. Sumey – 8/29/2011 1

Introduction Before we begin our journey of microprocessor interfacing, we will start with an overview of our MCU’s architecture. Most of the following information should be a review from the previous intro course. The Freescale (a 2004 spin-off of Motorola) HC11 family has been an immensely popular microcontroller that has been the mainstay of application designs for decades. It has been heavily used in the automotive and commercial products sectors. Although the HC11 has been superseded by other Freescale MCUs such as the HC08 and HC/S12 families, it remains an excellent device to study microprocessor architecture and interfacing principles. Also, the 16-bit HC/S12 (S12 for short) family has been designed to be upward compatible and 100% source code compatible with the HC11. This means that any assembly program written for the HC11 can be assembled with an S12 assembler and run on an S12 MCU with the same result as with the HC11. Primary differences from the HC11 to the S12 include a 16-bit processing unit, memory addressability beyond 64 KB, faster program execution, 9 additional indexed addressing modes, and more instructions. Some key features of the HC11 include:

advanced 8-bit HCMOS MCU

operates from D.C. to 2 MHz

16-bit address bus 64KB (65,536) memory map size

68HC11E9 has 12 KB ROM, 512 bytes EEPROM, 512 bytes RAM; all internal

on-board I/O: A/D, SCI, SPI, 16-bit Timer, general purpose I/O ports

uses internal bank of 64 ($40) addresses for I/O locations (control registers)

memory-mapped I/O (no special I/O instructions or I/O address modes)

upward 6800 compatible + 91 new opcodes

1.1 Microprocessor Architecture When learning to program a microprocessor in assembly language, there are three aspects of the microprocessor architecture that must be reviewed. This review is less important when programming in a high-level language such as ‘C’; however, it is still useful to be familiar with the underlying architecture. Even when using a high-level language, there may arise times when it would be better to implement a particular code sequence in low-level assembly. Examples of this are timing-sensitive I/O device control and interrupt service routines. The three processor architectural aspects of concern to the programmer are:

processor register set

addressing modes

instruction set

1.1.1 Register Set In order to drive an automobile, it is given that one needs to be familiar with the various functions and controls of the vehicle. It would be ill-advised for someone to get behind the wheel who does not understand the difference between brake and accelerator. Similarly, to successfully program a given computer, an assembly language programmer must be familiar with the register set and of its proper usage. Register sets are typically presented in the form of a programming model as shown in figure 1-1 for the HC11 / S12 processors. The registers are explained in the paragraphs that follow.



Fig. 1-1: HC11 Programming Model

A, B: Accumulators A and B are 8-bit wide general purpose registers that are used for arithmetic calculations and data manipulations such as Boolean logic and shift operations. For the HC11, accumulators A and B may also be used in concatenated form as a 16-bit register; in this case named D (“double”). When used in this fashion, A is the high byte and B is the low byte of D.

IX, IY: Index registers X and Y are 16-bit registers that are typically used as address pointers in indexed addressing. An 8-bit offset embedded in the instruction is added to the register value to form an effective address (EA) which is the ultimate address of an instruction’s operand. The 8-bit offset is treated as unsigned (0..255) and the addition is only temporary; it does not affect the value of the index register. These registers may also be used as counters particularly when using their associated efficient increment and decrement instructions (INX, DEX, INY, DEY).

SP: The 16-bit Stack Pointer register is initialized to an area of RAM where a FILO (first-in last-out) data structure is maintained by the processor. Register bytes are pushed onto or pulled from the stack automatically by the CPU for subroutines and interrupts and also programmatically via PSH and PUL instructions. The HC11 uses a post-decrement/pre-increment protocol; thus the SP always points to next free stack location.

PC: The very important Program Counter is another 16-bit register that always contains the memory address of the next program code byte to be fetched and executed. At reset, the PC is initialized automatically from the reset vector and is maintained by the CPU throughout program execution; it is not normally directly modified by the programmer. The HC11’s reset vector is at $FFFE:FF which happens to be ROM on our HC11 boards and contains the starting address of the BUFFALO monitor.

CCR: The Condition Code Register is an 8-bit register that houses three control bits (S, X, I) and five status “flag” bits (H, N, Z, V, C). The flags bits are used to indicate various results of the previous operation for most instructions that involve accumulators, but not all. Pushes, pulls, transfers and exchanges do not affect the flag bits. The definition of each CPU instruction indicates which flags are affected and how.



1.1.2 Addressing Modes The second architectural aspect that an assembly language programmer must also be familiar with is the processor’s addressing modes. Simply put, an instruction’s addressing mode determines how the instruction’s operand is accessed or where it lives in memory, i.e. the effective address. In the cases of branches, jumps and subroutine calls, the effective address specifies where execution is to proceed. For monadic processors like the HC11, only a single operand is operated on per instruction. Dyadic processors support two operands in a given instruction. For example, the S12 processor has a memory-to-memory copy instruction that allows a memory byte to be copied from a source to a destination location in a single instruction: MOV Here,There The EA for each of the two operands Here and There may be specified in a number of different address modes. Although some processors have upwards of a dozen or more address modes, the HC11 has a rather modest total of six modes. Each mode is explained in the following paragraphs along with example instructions.

1. Inherent aka implied An inherent instruction is one in which everything the CPU needs to know for execution is

implied or contained within the 1- or 2-byte opcode. These are typically instructions that use only accumulators or index registers or are control instructions without arguments. There is no EA for inherent addressing.

ex: INCA, DEX, LSRA, CLC, RTS

2. Immediate With immediate addressing, the operand is contained in the byte(s) immediately following the

opcode. The number of bytes needed for the operand will match the size of the register involved. A load immediate to accumulator B will require one operand byte while a load immediate to an index register (or D) will require two bytes. The EA of an immediate address mode instruction will be the address following the opcode itself.

ex: CMPD #$4A2C ;compare D with hex 4A2C

3. Direct In direct addressing, the operand is assumed to live in page 0, i.e. $0000-$00FF. Thus, the

EA high byte is zero and only the EA low byte needs to be encoded into the instruction after the opcode. Most HC11 assemblers will automatically choose direct addressing if the operand lives in page 0; however, they may also be forced to use direct via the ‘<’ symbol in the operand column. The advantages of direct over extended addressing are that one less opcode byte is required and execution time is one cycle faster. A common exploitation of these advantages is to place RAM or I/O registers in page 0 which effectively optimizes those accesses.

ex: INC <25 ;bump memory location $0025 by one

4. Extended When the direct addressing cannot be used (or even if it can be), extended addressing mode

comes to the rescue. Here, the complete 16-bit EA is encoded into the instruction after the opcode. Nothing in the memory map can evade the long arm of extended addressing. However, extended address instructions will always be one byte and one cycle longer than



when using direct. HC11 assemblers can be forced to use extended by placing the ‘>’ symbol in the operand column.

ex: STY $50FC ;store Y at $50FC (hi) and $50FD (lo)

5. Relative Relative addressing is relatively simple (sorry!) in that it is only used in branch (not jump)

instructions. Excluding BRA and BRN, a branch instruction will test some condition and if true, will add an 8-bit signed offset (-128..+127) contained in the instruction to the current PC value, which by then will be the address of the following opcode. This effectively causes a program control transfer (a teleport?). In the event the condition evaluates to false, control simply proceeds to the next instruction as usual. All branch instructions for the HC11 are 2-bytes in length; however, other processors such as the S12 have a “long” variant of each branch that can reach anywhere in the memory map. In the following example, the zero flag is evaluated and if false, execution proceeds to label LOOP.

ex: BNE LOOP ;branch to LOOP if not equal (Z=0)

6. Indexed Arguably the most complex address mode is indexed and for this reason, is also the most

confusing. Some other processors even have numerous variants of indexed addressing. This confusion probably stems from the fact that the EA of an indexed addressing instruction is formed by summing two parts: a 16-bit base address from one of the index registers and an 8-bit unsigned offset (0..255) encoded in the instruction. It is relevant to note that an offset of zero degenerates to what is known as “register indirect” addressing in other architectures. To illustrate indexed addressing, the following example clears the 5th byte beyond the address pointed to by the Y register; in other words it zeros memory location 1008. Note that the index register is unaffected by the indexed instruction so register Y will still contain 1003 after the CLR.

ex: LDY #1003 ;Y=1003

CLR 5,Y ;clear 1008 (1003+5)

For the S12, nine additional variations of indexed addressing provide more efficient access to operands using various offset lengths and auto pre/post decrement/increment operations.

1.1.3 Instruction Set The third and final processor architectural aspect and of utmost importance to the assembly language programmer is the instruction set. Microprocessors may have anywhere from a couple dozen instructions to many hundreds! The HC11 sports about 109 different instruction operations while the S12 adds about 65 additional instructions. Instruction sets are typically presented in summary chart form as shown below and sometimes in explicit detail on an instruction-by-instruction basis. The snippet in figure 1-2 shows the first three instructions from the HC11 instruction set charts as found in the M68HC11E Series Programming Reference Guide. S12 instruction set charts are similar. Left-to-right, the chart gives:

the mnemonic form of the instruction as used in a source code file

a description of the instruction’s operation

a Boolean algebraic description of the instruction

the addressing mode(s) available for the instruction

the opcode for the instruction in a given address mode

a code describing the operand, i.e. ii=2 immediate nibbles, dd=1-byte direct address, etc.

the number of program code bytes and execution cycles required by that opcode variant



effects, if any, on the various CCR bits (‘─’ means unaffected, ‘↕’ means set or cleared as appropriate)

Mnemonic Operation Boolean

Description

Addr.

Mode

Instruction

Byte

s

Cycle

s

Condition Codes

Opcode Operand S X H I N Z V C

ABA Add Accumulators

A+B→A INH 1B ─ 1 2 ─ ─ ↕ ─ ↕ ↕ ↕ ↕

ABX Add B to X IX+(00:B)→IX INH 3A ─ 1 3 ─ ─ ─ ─ ─ ─ ─ ─

ABY Add B to Y IY+(00:B)→IY INH 18 3A ─ 2 4 ─ ─ ─ ─ ─ ─ ─ ─

ADCA (opr) Add with Carry to A

A+M+C→A A IMM A DIR A EXT A IND,X A IND,Y

89 99 B9 A9

18 A9

ii dd hh ll ff ff

2 2 3 2 3

2 3 4 4 5

─ ─ ↕ ─ ↕ ↕ ↕ ↕

Fig. 1-2: HC11 Instruction Set Chart Snippet For example, an Add with Carry to A (ADCA) extended instruction is a 3-byte instruction comprised of the opcode $B9 followed by the operand EA high byte (hh) followed by the low byte (ll), requires 4 execution cycles, and modifies the H, N, Z, V, and C flags according to the result of the addition. In order to succeed at assembly language programming, you must be familiar with the CPU’s instruction set charts – the more time you spend studying these charts, the better programmer you will become and less time will be required for the programming task. Just as you’ve learned not to look for car parts in a grocery store or pretzels and beer in an auto parts store, you should know what operations are available for which registers and in which addressing modes. As learning a processor’s instruction set can be a daunting task in itself, another way to become familiar with the instruction set is to review the instructions by functional category. The following paragraphs break down the HC11 instruction set into four major categories each with a number of subgroups.

1. Accumulator / Memory Broadly speaking, this category includes instructions that use or affect accumulators or memory

locations. Subgroups include:

a. loads / stores / transfers CLRx, LDAx, LDD, PHSx, PULx, STAx, STD, Txx, XGDX, XGDY

b. arithmetic ABx, ADDx, ADCx, CBA, CMPx, CPD, DAA, DECx, INCx, NEGx, SUBx, SBCx, TSTx

c. multiply / divide

MUL (8x816), IDIV, FDIV

d. logic – the usual Boolean operations ANDx, BITx, COMx, EORx, ORAx

e. data test / bit manipulation BITx, BCLR, BSET, BRCLR, BRSET

f. shifts / rotates ASLx, ASRx, LSLx, LSRx, ROLx, RORx (only ASL, LSL, LSR for D)

2. Stack / Index Register This category includes instructions that manipulate the index registers or stack pointer.

a. load / store LDS, LDX, LDY, STS, STX, STY

b. adds / compares ABX, ABY, CPX, CPY

c. push / pull index registers PSHX, PSHY, PULX, PULY



d. increment / decrement INS, INX, INY, DES, DEX, DEY

e. transfers / exchanges TSX, TSY, TXS, TYS, XGDX, XGDY

3. Condition Code Register This category includes instructions that manipulate the condition code register bits. These

instructions all use a single opcode byte and use the inherent mode exclusively.

a. set / clear CLC/SEC, CLV/SEV, CLI/SEI

b. transfers TAP, TPA (‘P’=”processor status word”, i.e. CCR)

4. Program Control / Misc. These instructions implement program control by effecting control transfers.

a. branches – always use relative addressing Bxx (‘xx’ = CC,CS,EQ,GE,GT,HI,HS,LE,LO,LS,LT,ME,NE,PL,RA.RN,VC,VS)

b. jump JMP

c. subroutine handling BSR, JSR, RTS

d. interrupt handling RTI, SWI, WAI

e. miscellaneous NOP, STOP (freezes MCU clocks), TEST (factory use only)

The S12 CPU similarly breaks down the instruction set, but in quite a few more categories as follows.

1. Load / Store 2. Transfer / Exchange 3. Move Instructions 4. Addition / Subtraction 5. Binary-Coded Decimal (BCD) 6. Decrement / Increment 7. Compare and Test 8. Boolean Logic 9. Clear / Complement / Negate 10. Multiplication / Division 11. Bit Test and Manipulation 12. Shift / Rotate 13. Fuzzy Login Instructions 14. Minimum / Maximum Instructions 15. Multiply and Accumulate (MAC) 16. Table Interpolation 17. Branch Instructions 18. Loop Primitives 19. Jump and Subroutine 20. Interrupt Instructions 21. Index Manipulation 22. Stacking Instructions 23. Pointer and Index Calculations 24. Condition Code Instructions 25. Stop / Wait 26. Background mode / Null operations



For details of the instruction set, refer to the programming reference guide – it is the authoritative reference and should be used accordingly!

1.2 Reverse Engineering Using instruction set charts as discussed in the previous section allows one to manually convert an assembly source program into object code for the processor being used (however, assembler programs are much faster at this!). Occasionally the need arises to reverse engineer a piece of object code back into source form. This is usually referred to as disassembly. This process is tedious, time-consuming and sometimes illegal, but doable. Why would one want to subject oneself to such torture? The usual reason is to see how something works in the absence of the original source program. To cite another reason, I once repaired a non-bootable hard drive by manually reading, disassembling, repairing, and rewriting the damaged boot sector. Obviously, this hard drive was very important to the client! Disassembling HC11 object code is really quite straight-forward, especially with the help of opcode maps also available in the M68HC11E Series Programming Reference Guide. With 8-bit opcodes and only three “extension pages”, the process proceeds by identifying the instruction for the first opcode, then the byte length of the instruction. Opcodes $18, $1A, and $CD are really prebytes of a 16-bit opcode where the LSB indicates the real instruction from extension page 2, 3, or 4 respectively. Once the addressing mode and operand are decoded, the source instruction may be written and the process repeated. For example, consider the following sequence of program memory bytes in hexadecimal: 4F 16 F3 80 0A 1A 83 10 00 Starting with the opcode map for “page 1” (always start here for each new instruction), the $4F represents a CLRA instruction which uses only a single program byte. The $16 is a TAB instruction, again using a single byte. Next, the $F3 is an ADDD instruction using the extended addressing mode. Thus, the next two program bytes, $80 $0A, is the effective address ($800A) of the operand which is added to register D. The forth instruction begins with $1A which is a “page 3” prebyte. Switching to opcode map page 3, the $83 represents a CPD instruction using immediate addressing. Since D is a 2-byte register, the next two bytes, $1000, is the immediate value being compared to D.

1.3 Instruction Timing As previously mentioned, instruction set charts give the number of execution cycles required for each instruction/addressing mode combination. Although you may have not been overly concerned with this specification in the past, instruction timing can become very significant when interacting with input/output ports and devices. Another reason to understand instruction timing is for simple delay loops, typically required when interfacing fast processors to slow homosapiens! Consider blinking an LED on an output port: what is the minimum amount of time the LED must be held on in order to be detected by the human eye? The average person can discern flickering up to approximately 30 Hz; frequencies above this will appear steady or nearly smooth to the human eye. If driven at 50% duty cycle, the minimum on time would therefore be one-half of 1/30Hz or 16 2/3 ms. Blinking an LED at 40 Hz, that is 12.5 ms on and 12.5 ms off, would give the illusion of a steadily lit LED although at ½ of its full brightness. In the instruction sequence shown in figure 1-3, the HC11 assembler has been instructed to display the number of execution cycles (~) for each line. A quick summation of the cycles yields a total of 15 CPU cycles.

CE 00 64 3~ 1 ldx #100 ;initialize X as a counter

7C 00 00 6~ 2 label1 inc 0 ;bump contents of location 0

09 3~ 3 dex ;decrement X by 1

26 FA 3~ 4 bne label1 ;repeat until 0 is reached

Fig. 1-3: Example instruction sequence



However, everything changes in the presence of loops! The last BNE instruction says to branch back up to line 2 if the result of the previous DEX operation is non-zero (Z=0). This will be true for 100 iterations because X was initialized to 100 in line 1. So in reality, we have line 1 being executed once at 3 cycles followed by a 12 cycle loop repeated 100 times yielding a grand total of [3~ + (100 * 12~)] or 1203 cycles. Be careful of this, be very careful! Instructors are notorious for trying to trick students on this… One caveat here to be aware of is variations in number of CPU cycles at execution time. The S12 short branch instructions, for example, require 3 cycles if the branch is taken but only 1 cycle if not. This is all fine and dandy, but how does this relate to the real world that we live in? Simple - recall that the processor runs at a particular clock frequency, let’s say 1 MHz for this discussion. Remember p=1/f ? The period (p) of a 1 MHz frequency (f) is 0.000,001 second or 1 µs. This is the amount of time for each of those cycles (~) given in the instruction set charts! Therefore, the 1203~ sequence in the above example maps to 1.203 ms of real time. Putting things into perspective, most PCs today run at multi-gigahertz speeds which are three orders of magnitude larger than our example here. But don’t worry – most microcontrollers do not run Windows so they need not be nearly so powerful or fast. Challenge: what value would have to be loaded into X on line 1 in order to achieve a 1 second delay? Do you foresee any problem here? If so, what is the solution?

1.4 MCU, not MPU A common question often asked when learning microprocessor technology is “what is the difference between a microprocessor (MPU) and a microcontroller (MCU)?” Technically, the term MPU refers to a central processing unit on a single integrated circuit including the register set, arithmetic/logic unit, and sequence controller. It still requires external connections to memories and I/O peripherals via address and data buses to become a functional system. On the other hand, a MCU adds memory and various I/O peripherals right on-board the same integrated circuit (IC) as the MPU. Thus, it can become a complete, stand-alone system with just the addition of a power supply. In the case of the HC11 MCU we are using, we find RAM, ROM, EEPROM, serial I/O, parallel I/O, A/D converter, and timer modules provided. Other HC11 family variants provide different mixes of peripherals including multiple serial ports, more timers, USB, CAN and even Ethernet. With the presence of memory and an array of I/O peripherals internal to the integrated circuit, many systems no longer require external address, data, and control buses. Therefore, the pins that would normally implement these buses can be replaced with that many more I/O pins. Some MCUs including the HC11 even allow the designer to select between these two functional groups. With the increase in complexity of MCUs, it is common for manufacturers to show the overall architecture in the form of a block diagram. The diagram in figure 1-4 shows the ‘E’ variant of the HC11 MCU as used on the CME11 evaluation board.



Fig. 1-4: M68HC11 ‘E’ Series Block Diagram Most of the MCUs in the HC11 family allow programmer selection of ports B and C as being either address/data buses or general purpose I/O lines. In order to support this, the HC11 can come out of reset in a number of different operational modes such as single-chip and expanded/multiplexed. This is determined by the logic states of the MODA and MODB pins at reset time. Single chip mode provides ports B and C as digital I/O pins while expanded/multiplexed mode trades these I/Os for a multiplexed address/data bus that may connect to conventional memory and I/O devices.



1.4.1 Memory Map With 16-bit address registers (PC, SP, X, Y) and a 16-bit address bus; the CPU can address 2

16 or 65,536

unique locations. Because the data bus is 8 bits, each location contains a single byte yielding a memory map size of 64KB. This address space is shared by various memory devices as well as I/O peripherals which may exist either internally or externally to the chip. Some processors (ala Intel) additionally provide an “I/O map” via special instructions and control signals to implement I/O devices in a dedicated space separate from the main memory map. Also, more powerful processors may have up to 32-bits for an address bus which yields 2

32 or 4,294,967,296 locations (4 GB) in the memory map.

Details of the HC11’s operational modes and memory map options are found in the HC11 reference manuals; however, a summary of the default map conditions is show in figure 1-5.

RANGE FUNCTION DESCRIPTION

0000-01FF 512 bytes RAM stack & BUFFALO use (0-FF), user (100-1FF)

1000-103F 64-byte register block configuration/status, peripheral I/O

B600-B7FF 512 bytes EEPROM user non-volatile storage, small non-volatile programs

D000-FFFF 12KB ROM factory programmable only (BUFFALO at E000-FFFF)

Fig. 1-5: HC11 Memory Map Summary The register block contains registers for all on-board peripherals as well as MCU control. One register, INIT, allows programmer selection of memory map positions for the RAM and register block ranges, but modifying the INIT register must be done within the first 64 cycles after reset. For example, the following instructions would reverse the placement of the RAM and register blocks. LDAA #$10 ;RAM at $1000, registers at 0

STAA INIT

1.4.2 Hardware Implementation The E-series of HC11 MCUs are available in a number of package styles like leaded chip carrier (LCC), quad flat pack (QFP), and dual in-line package (DIP) with pin counts of 48, 52, 56 and 64 pins. In comparison, high end processors like the Intel Core 2 Pentium have in excess of 700 pins! The pinout of the 52-pin PLCC version of the HC11 on our evaluation board is shown in figure 1-6. The chart in figure 1-7 gives a brief summary of the pin functions. Note that numerous pins are dual-function depending on the operational mode of the MCU.



Fig. 1-6: Pinout for 52-Pin Plastic Leaded Chip Carrier

Group # Pins Name Description Comments

Power 2 VDD, VSS +5VDC power & ground needs good bypassing

“ 2 VRH, VRL A/D reference hi & lo voltages

may be +5V & ground

Mode Select

2 MODA / LIR’ MODB / VSTBY

Determines operation mode at Reset

have dual purpose1

Osc. 3 EXTAL, XTAL, E clock/crystal source, bus frequency (E)

clock freq. = 4 (E) E used for 68xx peripherals

Control 1 RESET’ Reset processor is bi-directional!

“ 2 IRQ’, XIRQ’ external interrupt inputs XIRQ is level, IRQ is level or falling-edge sensitive

I/O Ports

8 PB0-PB7 / A8-A15

8 GP outputs or ADDRH depends on operation mode

“ 8 PC0-PC7 / AD0-AD7

8 GP I/Os or ADDRL / DATA multiplexed by AS

“ 2 STRA / AS STRB / R/W’

I/O strobes or Address Strobe & R/W’ lines

depends on mode2

“ 8 PA0-PA7 GP I/O or Timer pins exclusive use

“ 6 PD0-PD5 6 GP bidir I/O pins or SCI / SPI I/O lines

exclusive use

“ 8 PE0-PE7 / AN0-AN7

8-bit GP input port or 8 analog inputs

ADC actually has 16 channels

Fig. 1-7: MC68HC11E Series (52-pin PLCC) Pinout Overview

Notes: 1. MODA/MODB are only defined at Reset time, these pins become LIR’/VSTBY afterwards. 2. STRA/AS is an Input Strobe in Single-Chip mode, Address Strobe in Expanded mode; STRB/RW’ is an Output Strobe in Single-Chip mode, Read/Write’ in Expanded.



The two mode select pins, MODA and MODB, have the special purpose during a CPU reset of setting the HC11’s operational mode. The logic levels of these pins are read and latched internally in the HPRIO register by the HC11 at the beginning of the reset sequence. The four possible selections are shown in figure 1-8. In practice, only the bottom two rows are commonly used.

MODB MODA Operational Mode

0 0 Bootstrap

0 1 Special test (factory)

1 0 Single chip

1 1 Expanded / multiplexed

Fig. 1-8: Mode Select Pin Options To create a usable HC11-based platform, certain connections must be made according to operational mode. The diagrams in figures 1-9 through 1-11 show recommended basic connections for both single-chip and expanded modes. The power, crystal, reset, and interrupt connections (the left side) are basically the same in both modes and the primary difference is the use of ports B and C pins. Also note the mode select pins configured appropriately for each mode. In expanded mode, the 8-bit data bus is time multiplexed with the low byte of the address bus according to the output pulses on the AS (address strobe) line while the R/W’ (read/write) pins determines the direction of data transfer on the data bus. This is the reason for including the 74HC373 octal latch which grabs the address low byte emitted by the HC11 in the early part of each memory map access. These recommended connections are exactly what are implemented on the CME11E9 evaluation board used in lab. The CME11 also provides a number of additional features such as memory expansion, a RS232 serial communication port and a LCD interface port. Refer to the CME11 schematic for the CME11E9 board for details. Challenge: referring to the expanded mode connection diagrams, determine the external memory map organization of the three external memory devices.



Fig. 1-9: Basic Single-Chip Mode Connections



Fig. 1-10: Basic Expanded Mode Connections (1 of 2)



Fig. 1-11: Basic Expanded Mode Connections (2 of 2)



1.5 Software Development In the previous course, you initially learned to program the HC11 manually using BUFFALO monitor commands. Although a very slow and laborious process, it does readily demonstrate the operation of the processor and the instruction set. Later, you learned a much better PC-hosted method of HC11 software development. Illustrated in figure 1-12, this process involved using a PC editor to create a .asm source code file, then having it assembled to object code by the CAS11 cross-assembler, and finally using a communication program such as Hyperterm to download the resulting .s19 object code to the HC11 for execution and evaluation.

Fig. 1-12: Software Development Process You were also introduced to SIM11, a Windows-based simulator for the HC11 that mimics the operation of the CME11 board in a virtual environment (figure 1-13). Fortunately, this course will continue to use the PC-hosted HC11 development process for laboratory work. However, because the majority of labs in this course will involve real hardware interfaces and I/O devices, SIM11 will be of limited usefulness.

Fig. 1-13: Example SIM11 Session

myprog.s19 myprog.asm

CAS11 Notepad Hyperterm CME11

EVB



1.6 Application Example The previous sections of this chapter have overviewed the HC11 microcontroller from both software and hardware perspectives. As an example of implementing a real-world system based on the HC11, this section presents a solution for a traffic light controller. This example also provides a perfect segue to the next chapter on I/O architecture. The photo in figure 1-14 shows the demonstration prototype that implements an open-loop traffic light controller for a two-way intersection using the CME11E9 evaluation board. Because we are mainly interested the HC11 implementation here, we use simple LEDs to represent the red/yellow/green lights for each of the two directions. We will look at a more realistic output circuit in a later chapter.

Fig. 1-14: Traffic Light Controller Demonstration An open-loop system is one which lacks feedback, such as under-pavement magnetic loop sensors or a camera vision system in the case of our traffic light controller. The addition of such feedback would convert this example into a closed-loop system with the potential of yielding better performance. For example, the green time could be shortened once the controller determined that all cars moving in that direction have cleared the intersection. Since this implementation is open-loop, the light timing is controlled by the processor in a fixed duty cycle fashion as tabulated in figure 1-15. Our controller is to activate the appropriate color lights for each direction for a given time as specified in each row of the table. Upon reaching the end of the table, the controller must jump back to the first row and repeat the whole process. Because the north-south direction of the intersection is a primary road, it is given a longer green time of 90 seconds compared to the 60 seconds of the east-west secondary road. We also see the specification of 2 seconds of “red both ways” before advancing to a green state. In some cities (Detroit for example!), I have witnessed seemingly different road rules wherein a traffic light turning yellow means “speed up” to approaching vehicles and turning red means “do you feel lucky?” The pause with 2-way red before turning green may be a strategy to help deal with such misguided drivers.



N-S State E-W State Time (sec)

green red 90

yellow red 5

red red 2

red green 60

red yellow 5

red red 2

Fig. 1-15: Light Timing Specifications In terms of software implementation, figure 1-16 shows a properly commented assembly listing of the solution to this application example. The interesting feature of this solution is that it is table-driven, with the data values taken directly from the specifications of figure 1-15. This is significant because not only is this solution much shorter than an algorithm driven approach, maintenance is also drastically simplified. If our controller were to be used in different city that required different timing or perhaps a future Detroit that switches to 4-color lights with the addition of an orange state, the only software changes necessary would be in the table itself. Absolutely no algorithmic changes to the program would be needed in this situation. Table-driven processing is an important programming technique that simplifies the implementation of many real-world interfaces and control systems. It is also a key to the implementation of finite state machines. A brief description of this program is as follows.

lines 12-13: The equate pseudo-op is used to create symbolic names for the HC11’s port B and for the

memory location were this program is placed. Note that because port B is a fixed output-only port, no data direction register initialization is necessary as is typical with other I/O ports.

lines 17-25: This is the “main loop” of the controller. Index register X is used as a memory pointer to fetch

output light patterns and time delays from the table. It is initialized to the beginning of the table then incremented each time a byte is read from the table until the “end of table marker” is seen at which time the main loop is restarted.

lines 31-34: Subroutine “DelayN” provides a programmatic time delay for the number of seconds given in

accumulator A when it is called. The actual delay is performed by calling the next 1-second delay subroutine N times.

lines 40-54: Subroutine “Delay1” performs a 1-second software time delay based on a 2 MHz CPU clock

frequency. Each instruction’s cycle length is taken into consideration to yield a reasonably accurate time delay. You may note the vulnerability here to clock frequency changes or lost time due to interrupt processing; we will revisit this in a later chapter and discover a much better method of performing processor time delays.

lines 58-64: This is where the timing specification table from figure 1-15 is implemented. Two important bits to

notice here are the use of the octal prefix ‘@’ for the output patterns and the use of a zero for output pattern to demark the end of the table. The output patterns are written in base 8 to more easily map to the 3-bit groupings of port B output bits and the zero byte is used as an end-of-table marker because an output pattern of all lights on does not make sense and should never occur! Also, the output patterns assume negative-true logic as the port B outputs connect to LED cathodes and must output logic lows to turn LEDs on.



1 * Traffic Light Controller Demonstration

2 * by J.S.Sumey

3 *

4 * This program implements the traffic light controller for a

5 * fixed duty cycle, 2-way (North-South/East-West) intersection.

6 * A bank of 6 active-low LEDs are interfaced to port B as follows:

7 * PB5: N-S Red PB2: E-W Red

8 * PB4: N-S Yellow PB1: E-W Yellow

9 * PB3: N-S Green PB0: E-W Green

10

11 * Memory map definitions

=1004 12 PORTB EQU $1004 ;HC11 I/O Port B

=0100 13 CODE EQU $0100 ;where our code can begin on EVB

14

15 * beginning of main program code

0100 16 ORG CODE ;set assembly PC

0100 CE 01 28 17 Begin ldx #LEDTBL ;point X to start of LED output table

0103 A6 00 18 Loop ldaa ,X ;get output pattern

0105 27 F9 19 beq Begin ;restart sequence if end-of-table

0107 B7 10 04 20 staa PORTB ;send pattern to output LEDs

010A 08 21 inx ;bump table pointer to delay time

010B A6 00 22 ldaa ,X ;get delay time for this pattern

010D 08 23 inx ;bump table pointer to next pattern

010E 8D 02 24 bsr DelayN ;delay that number of seconds

0110 20 F1 25 bra Loop ;repeat main loop

26

27 * DelayN: delay 'N' seconds

28 * in: A = 'N', number of seconds to delay (0=256 sec.)

29 * out: A = 0, all other registers not affected

30

0112 8D 04 31 DelayN bsr Delay1 ;go delay 1 second

0114 4A 32 deca ;decrement 'N'

0115 26 FB 33 bne DelayN ;continue if not done

0117 39 34 rts

35

36 * Delay1: delay 1 second via software,

37 * assumes F=2.0 MHz (and no interrupts)

38 * all registers preserved for caller

39

0118 36 40 Delay1 psha ;3~ preserve registers used here

0119 3C 41 pshx ;4~

011A 86 0A 42 ldaa #10 ;2~ (10) 100ms. intervals per sec.

43 ;=== outer loop

011C CE 82 34 44 Dly100 ldx #33332 ;3~ iterations of Dloop for 100ms.

45 ;--- inner loop (100ms)

011F 09 46 Dloop dex ;3~ \

0120 26 FD 47 bne Dloop ;3~ / 33,332 * 6~ = 199,992~

48 ;--- inner loop

0122 4A 49 deca ;2~ 199,992~ + 8~ = 200k~ = 100ms.

0123 26 F7 50 bne Dly100 ;3~

51 ;=== outer loop

0125 38 52 pulx ;5~ recover used registers

0126 32 53 pula ;4~

0127 39 54 rts ;5~

55

56 * LED output table: 6 rows x 2 columns

57 * 1st col is LED output pattern, 2nd col is delay in seconds

0128 33 5A 58 LEDTBL FCB @63,90 ;N-S green, E-W red

012A 2B 05 59 FCB @53, 5 ;N-S yellow, E-W red

012C 1B 02 60 FCB @33, 2 ;N-S red, E-W red

012E 1E 3C 61 FCB @36,60 ;N-S red, E-W green

0130 1D 05 62 FCB @35, 5 ;N-S red, E-W yellow

0132 1B 02 63 FCB @33, 2 ;N-S red, E-W red

0134 00 64 FCB 0 ;end-of-table marker

65

0135 66 END

Fig. 1-15: Traffic Light Controller Solution [end of chapter]

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