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CSW 353 (Assembly Language)

Computer Architecture

Dr. Salma Hamdy s.hamdy@cis.asu.edu.eg

Computer System Architecture

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Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Register Transfer and Microoperations

Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control

Chapter 8: CPU

Chapter 11: I/O Organization

Chapter 12: Memory Organization

Basic Computer Organization and

Design - II 1. Memory-Reference Instructions 2. Register Reference Instructions 3. Input-Output and Interrupts 4. Design of Basic Computer 5. Design of Accumulator Logic

The three types of instructions, their register transfer statements, and their control functions. Connecting all into a basic computer.

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1. Memory-Reference Instructions

• 𝑰𝑹(12-14) to decoder outputs 𝑫𝟏𝑫𝟐…. 𝑫𝟔 which specifies one of 7 operations.

• Effective address was stored in 𝑨𝑹 during 𝑻𝟐 (when 𝑰 = 𝟎), or during 𝑻𝟑 (when 𝑰 = 𝟏).

• Execution starts with timing sequence 𝑻𝟒.

• Actual execution requires a sequence of microoperations as data stored in memory cannot be processed directly.

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1. Memory-Reference Instructions – (cont.)

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1. Memory-Reference Instructions – (cont.)

And to 𝑨𝑪

• Performs the AND logic operation on the pair of bits in 𝑨𝑪 and the memory specified by the effective address.

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1. Memory-Reference Instructions – (cont.)

BUN (Branch Unconditionally)

• Transfers the program to the instruction specified by the effective address (jump).

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1. Memory-Reference Instructions – (cont.)

BUN (Branch Unconditionally)

• Transfers the program to the instruction specified by the effective address (jump).

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1. Memory-Reference Instructions – (cont.)

BSA (Branch and Save Return Address)

• Branches to a subroutine or procedure (call).

– Stores the address of the next instruction of the main program, in a memory location specified by effective address (top of subroutine).

–Branches to address of first instruction of subroutine (the one right after the effective address).

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1. Memory-Reference Instructions – (cont.)

BSA Example

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1. Memory-Reference Instructions – (cont.)

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1. Memory-Reference Instructions – (cont.)

• Only seven timing sequences needed to execute the longest instruction.

• Sequence Counter size?

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2. Register Reference Instructions

• 𝑫𝟕 = 𝟏 and 𝑰 = 𝟎, with timing sequence 𝑻𝟑.

• 𝑰𝑹(0-11) specify one of 12 instructions.

• Let the bits of 𝑰𝑹 be 𝑩𝟏𝟏𝑩𝟏𝟎…. 𝑩𝟎.

• Let the Boolean relation 𝑫𝟕𝑰′𝑻𝟑 = 𝐫.

• Since the control function is distinguished by one of the bits in 𝑰𝑹(0-11), then all control functions can be simply denoted by 𝒓𝑩𝒊.

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2. Register Reference Instructions – (cont.)

• Example: CLA

Hex. 7 8 0 0

Binary 0 111 1000 000 000

Control function that initiates the microoperations for this instruction is: 𝑫𝟕𝑰′𝑻𝟑𝑩𝟏𝟏 = 𝒓𝑩𝟏𝟏

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𝑰’ 𝑫𝟕 𝑩𝟏𝟏

2. Register Reference Instructions – (cont.)

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2. Register Reference Instructions – (cont.)

• 𝑺𝑪 is cleared after the execution of each instruction initiating 𝑻𝟎 (fetch) again that causes a new cycle.

• After a HALT, the start flip-flip must be set manually.

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3. Input-Output Instructions

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Input-Output Configuration

3. Input-Output Instructions – (cont.)

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• 𝑫𝟕 = 𝟏 and 𝑰 = 𝟏, with timing sequence 𝑻𝟑.

• 𝑰𝑹(0-11) specify one of 12 instructions.

• Let the bits of 𝑰𝑹 be 𝑩𝟏𝟏𝑩𝟏𝟎…. 𝑩𝟎.

• Let the Boolean relation 𝑫𝟕𝑰𝑻𝟑 = 𝐩.

• Since the control function is distinguished by one of the bits in 𝑰𝑹(0-11), then all control functions can be simply denoted by 𝒑𝑩𝒊.

3. Input-Output Instructions – (cont.)

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• 𝑺𝑪 is cleared after the execution of each instruction initiating 𝑻𝟎 (fetch) again that causes a new cycle.

Programmed control transfer

3. Input-Output Instructions

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Interrupts

• Instead of wasting time by checking flags, let the external device inform the computer when it is ready for transfer.

• Interrupt enable flip-flop 𝑰𝑬𝑵.

• 𝑰𝑬𝑵 = 𝟎 (with the 𝑰𝑶𝑭 instruction) flags cannot interrupt computer.

• 𝑰𝑬𝑵 = 𝟏 (with the 𝑰𝑶𝑵 instruction) computer can be interrupted.

3. Input-Output Instructions

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Interrupt Cycle

• Interrupt flag 𝑹.

3. Input-Output Instructions

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Interrupt Cycle

• Initiated after last execution phase if 𝑹 = 𝟏.

• That is, if 𝑰𝑬𝑵 = 𝟏, and either 𝑭𝑮𝑰 or 𝑭𝑮𝑶 are 1. Happens with any clock transition except when timing signals 𝑻𝟎, 𝑻𝟏, 𝑻𝟐 are active.

3. Input-Output Instructions

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Interrupt Cycle Example

3. Input-Output Instructions

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Modified Fetch and Decode Phases

• ??

4. Complete Computer Description

• Flowchart of the basic computer operation Fig 5-15.

• Control functions and microoperations of the basic computer Table 5-6.

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5. Design of Basic Computer

Components:

–Memory unit 4096×16.

–Nine registers: 𝑨𝑹, 𝑷𝑪, 𝑫𝑹, 𝑨𝑪, 𝑰𝑹, 𝑻𝑹, 𝑶𝑼𝑻𝑹, 𝑰𝑵𝑷𝑹, 𝑺𝑪.

– Seven flip-flops: 𝑰, 𝑺, 𝑬, 𝑹, 𝑰𝑬𝑵, 𝑭𝑮𝑰, 𝑭𝑮𝑶.

–Two decoders: a 3×8 operation decoder, and a 4×16 timing decoder.

–A 16-bit common bus.

–Control logic gates.

–Adder and logic circuit connected to 𝑨𝑪. 27 11/7/2013

5. Design of Basic Computer – (cont.)

Control Logic Gate

• Input: decoders output, 𝑰𝑹(0-11), 𝑨𝑪, 𝑫𝑹, the 7 flip-flops.

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5. Design of Basic Computer – (cont.)

Control Logic Gate

• Output: – Signals to control the input of the nine registers.

– Signals to control the read and write input of memory.

– Signals to set, clear, or complement the flip-flips.

– Signals for 𝑺𝟐, 𝑺𝟏, and 𝑺𝟎 to select a register for the bus.

– Signals to control 𝑨𝑪 adder and logic circuit.

• The specs of various control signals comes directly from Table 5-6.

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5. Design of Basic Computer – (cont.)

Control for Registers, Memory and Flip-Flops

• Registers control inputs are LD, INR, and CLR.

• Example: to find the gate structure associated with the control inputs of 𝑨𝑹, scan Table 5-6 to find all statements that change content of AR.

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5. Design of Basic Computer – (cont.)

Control for Registers, Memory and Flip-Flops

• Example: control inputs of 𝑨𝑹

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5. Design of Basic Computer – (cont.)

Control for Common Bus

• Each binary number is associated with a Boolean variable 𝒙.

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5. Design of Basic Computer – (cont.)

Control for Common Bus

• Each binary number is associated with a Boolean variable 𝒙.

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5. Design of Basic Computer – (cont.)

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Control for Common Bus

• Example: to find the logic that selects 𝑨𝑹, scan Table 5-6 to find all statement that have 𝑨𝑹 as a source.

5. Design of Basic Computer – (cont.)

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Control for Common Bus

• Example: to find the logic that selects 𝑨𝑹, scan Table 5-6 to find all statement that have AR as a source.

6. Design of Accumulator Logic

Control of 𝑨𝑪 Register

• From Table 5-6 extract all statement that changes the content of 𝑨𝑪.

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6. Design of Accumulator Logic – (cont.)

Control of 𝑨𝑪 Register

• From Table 5-6 extract all statement that changes the content of 𝑨𝑪.

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6. Design of Accumulator Logic – (cont.)

Control of 𝑨𝑪 Register

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𝑫𝟕𝑰′𝑻𝟑 = 𝐫

6. Design of Accumulator Logic – (cont.)

Control of Adder and Logic Circuit (one stage)

• Can be divided into 16 stages, each stage corresponds to one it in 𝑨𝑪.

• Each stage contains seven AND gates (one for each operation), one OR gate (combining all), and a full adder.

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6. Design of Accumulator Logic – (cont.)

Control of Adder and Logic Circuit (one stage)

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Selected Problems

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REMARK: registers on the bus are numbered from 1 to 7, meaning that terminal 0 of MUX (selected by 𝒔𝟐𝒔𝟏𝒔𝟎=000) does not contribute to transfers through the bus.

111

001

010

011

100

101

110

Selected Problems – (cont.)

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Selected Problems – (cont.)

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Selected Problems – (cont.)

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Selected Problems – (cont.)

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Next Lecture

Revision + problem solving.

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Assignment

- Reading: Chapter 5: sections 6-10.

References

- Digital Design, 4th ed, M. Morris Mano, Prentice Hall, 2006.

-http://microcom.kut.ac.kr/ ch05

- God bless Google and Wiki!

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