ARP

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ARP ARP 8/10 - 2004 INF5060: Multimedia data communication using network processors

description

INF5060: Multimedia data communication using network processors. ARP. 8/10 - 2004. Assignment 5. Extend the simple packet bridge from assignment 4 with ARP support build an ARP table to dynamically bind/map an IP address to a mac address and an interface on the card - PowerPoint PPT Presentation

Transcript of ARP

Page 1: ARP

ARPARP

8/10 - 2004

INF5060:Multimedia data communication using network processors

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2004 Carsten Griwodz & Pål HalvorsenINF5060 – multimedia communication using network processors

Assignment 5 Extend the simple packet bridge from assignment 4 with ARP

support

build an ARP table to dynamically bind/map an IP address to a mac address and an interface on the card

check IP address and forward packet to correct interface

be aware of broadcast loops

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2004 Carsten Griwodz & Pål HalvorsenINF5060 – multimedia communication using network processors

ARP Packet

MAC src

MAC destMAC dest MAS src

type

Hardware type = 1 Protocol type = 0x800MACaddr len=6Netaddr len=4 Opcode

Sender MAC addressSender MAC address Sender IP address

Sender IP address Receiver MAC addressReceiver MAC address

Receiver IP address

… only for readability …

Opcode:Request:

1Reply: 2

Sender MAC address: mandatory

Sender IP address: mandatory

Receiver MAC addressRequest: 0Reply: requester’s MAC address

Receiver IP address: mandatory

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2004 Carsten Griwodz & Pål HalvorsenINF5060 – multimedia communication using network processors

Broadcast problem

IXP1

20

0IX

P1

20

0

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2004 Carsten Griwodz & Pål HalvorsenINF5060 – multimedia communication using network processors

ARP caching Most OSes do ARP caching Our bridge does it for building and maintained a

spanning tree Two proposed caches

Address-to-interface mapping

Broadcast suppression

Last refresh cycle count (64 bit) IP address (32 bit) IF (32 bit)

Last seen cycle count (64 bit) IP source (32 bit)

MAC dest (48 bit)

MAC source (48 bit)

xbuf_alloc [$cyclect,2]

csr[read, $cyclect[0], CYCLE_CNT]

xbuf_free[$cyclect]

Microengine clock speed: 232 Mhz

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2004 Carsten Griwodz & Pål HalvorsenINF5060 – multimedia communication using network processors

Allocating cache memory Memory must be allocated by StrongARM Memory offset must be passed to microengines in

shared memory E.g.

e = RmMalloc(RM_SRAM, &ptr, n*4); space for n address-to-IF mapping entriese = RmGetPhysOffset(RM_SRAM, ptr, &sram_offset);

e = RmMalloc(RM_SCRATCH, &ptrptr, 1); space for pointer to cachee = RmGetPhysOffset(RM_SCRATCH, ptrptr, &sramptr_offset);e = RmWrite(RM_SCRATCH, sramptr_offset, sram_offset, 0);

for( i=0; i<6; i++ ) {sym.meNumber = i;bzero(sym.name, MAX_SIZE_OF_IMPORTED_SYMBOL);strncpy(sym.name, CACHE_PTR_STR, MAX_SIZE_OF_IMPORTED_SYMBOL);sym.value = sramptr_offset;e = RmUencPatchSymbol(i,&sym,1);

}