Analysis, Design and Implementation of Phase-Locked-Loop (PLL)...
Transcript of Analysis, Design and Implementation of Phase-Locked-Loop (PLL)...
![Page 1: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/1.jpg)
Analysis, Design and Implementation ofPhase-Locked-Loop (PLL) for Grid-Connected
Inverters
Dinesh Gopinath
Associate ProfessorDepartment of Electrical EngineeringCollege of Engineering Trivandrum
Thiruvananthapuram
Dinesh Gopinath Analysis and Design of PLL
![Page 2: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/2.jpg)
Outline
IntroductionGrid-Connected InvertersPhase-Locked-Loop for grid-connected convertersDifferent PLL schemesSimulation ResultsImplementation in Digital Platform (FPGA)Experimental ResultsConclusion
Dinesh Gopinath Analysis and Design of PLL
![Page 3: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/3.jpg)
Introduction
Inverters are the interfaces for distributed energy sources with the gridControl of grid-connected inverters need the phase information of thesourcePhase of the source can be extracted by a Phase-Locked-LoopPLL can be implemented in SoftwareThere are different schemes of PLL implementationThe issues are:
AccuracySpeedDisturbance rejectionEffect of Harmonics, Phase unbalance etc.
Dinesh Gopinath Analysis and Design of PLL
![Page 4: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/4.jpg)
Three-Phase Inverters
Vdc
Su
Su Su Su
SwSv
u v w
Dinesh Gopinath Analysis and Design of PLL
![Page 5: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/5.jpg)
Fundamentals of inverters
0
Vdc
S
SvpN
t
Vdc
N
vpN
Ton
Ts
Dinesh Gopinath Analysis and Design of PLL
![Page 6: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/6.jpg)
Fundamentals of inverters
0
Vdc
S
SvpN
t
Vdc
N
vpN
Ton
Ts
Dinesh Gopinath Analysis and Design of PLL
![Page 7: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/7.jpg)
Fundamentals of inverters
0
Vdc
S
S
t
Vdc
N
vpN
vpN(t)
vpN
vpN
Ton
Average Voltage
RippleTs
Vdc − vpN
0
− (Vdc − vpN)0
vpN (t) = Vdc · S
vpN = Vdc · Ton
Ts= Vdc · d
S=1 or 0
‘d’ is the duty ratio
vpN (t) = d · Vdc + vpN (h)
Dinesh Gopinath Analysis and Design of PLL
![Page 8: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/8.jpg)
Fundamentals of inverters
If the switch ‘S’ is switched at high frequency, all the harmonics willoccur at the switching frequencyHigh frequency harmonics can be easily filtered by a small low-passfilterOr, if the waveform feeds an R-L load, the current will be mostlyfollowing the average value vpN
Dinesh Gopinath Analysis and Design of PLL
![Page 9: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/9.jpg)
Sine-Triangle Pulse Width Modulation
Vdc
S
SvpN
N
Vdc vAN
N
vBNSA
SA
SB
SB
vpN = d · Vdc
If we choose the duty ratio ‘d’ as:
d = 0.5 + 0.5 ·m · sin (ωt)
Then,
vpN = 0.5Vdc + 0.5 ·m · Vdc · sin (ωt)
Where, ‘m’ is modulation index,0 ≤ m ≤ 1, and ω is the requiredangular frequency.
vAB = vA − vB
vAB = m · Vdc · sin (ωt)
for:
dA = 0.5 + 0.5 ·m · sin (ωt)
dB = 0.5− 0.5 ·m · sin (ωt)Dinesh Gopinath Analysis and Design of PLL
![Page 10: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/10.jpg)
Sine-Triangle Pulse Width ModulationCarrier
‘A’ phase ref ‘B’ phase ref
SA
0.5
1.0
The control law:SA ON: vref > vtriSB ON : −vref > vtri
For three-phase inverter, three sine wave references which are 120o phaseseparated are used.
Dinesh Gopinath Analysis and Design of PLL
![Page 11: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/11.jpg)
Sine-Triangle Pulse Width ModulationCarrier
‘A’ phase ref ‘B’ phase ref
SA
0.5
1.0
The control law:SA ON: vref > vtriSB ON : −vref > vtri
ω is the angular frequency of the required output voltage.ωt = θ is the phase of the output at any instant.
Dinesh Gopinath Analysis and Design of PLL
![Page 12: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/12.jpg)
Sine-Triangle Pulse Width ModulationCarrier
‘A’ phase ref ‘B’ phase ref
SA
0.5
1.0
The control law:SA ON: vref > vtriSB ON : −vref > vtri
For other modulation schemes such as Space Vector PWM also, the phase ofthe output voltage is required to derive the duty ratios.
Dinesh Gopinath Analysis and Design of PLL
![Page 13: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/13.jpg)
Grid-connected inverters
Vdc vinv vgrid
L
Voltage, frequency should be the samePhase can be used to control the power-flow
Dinesh Gopinath Analysis and Design of PLL
![Page 14: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/14.jpg)
Grid-connected inverters
Vdc
L
vw
vv
vu va
vb
vc
Inverter
Rectifier
Voltages, frequency should be the samePhase sequence must be the samePhase can be used to control the power-flow
Dinesh Gopinath Analysis and Design of PLL
![Page 15: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/15.jpg)
Grid-connected inverters
The phase of the grid voltages is a must for active/reactive powercontrolThe phase can be obtained by Phase-Locked-Loop
Dinesh Gopinath Analysis and Design of PLL
![Page 16: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/16.jpg)
Phase-Locked-Loop
Detector VCOLPFPhase ωoωi e(t)
Objective: To synthesize the phase/frequency information of the system ac-curately
Will a Zero-Crossing-Detector (ZCD) do the job?ZCD based tracking is slowQuadrature waveform technique is another methodNot the best method when the frequency is varying/ has harmonics
Dinesh Gopinath Analysis and Design of PLL
![Page 17: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/17.jpg)
3-phase Phase-Locked-Loop: d-q frame based PLL
0
a-b-c α− β
d-q
va
vb
vc
vα
vβα− β
vd
vq
θ
∫ωff
θ
Dinesh Gopinath Analysis and Design of PLL
![Page 18: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/18.jpg)
Phase Locked Loop
vas = Vm cos θ (1)
vbs = Vm cos
(θ − 2π
3
)(2)
vcs = Vm cos
(θ +
2π
3
)(3)
α
β
θ
d
q
b
c
a
vα = vas −1
2vbs −
1
2vcs
=3
2vas (4)
vβ =
√3
2(vbs − vcs) (5)
Dinesh Gopinath Analysis and Design of PLL
![Page 19: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/19.jpg)
Synchronously rotating reference frame, assuming no zero-sequencecomponents,
vd = vα cos θ + vβ sin θ (6)vq = −vα sin θ + vβ cos θ (7)
Let θ be the PLL’s output, which is an estimated value. Then,[vdvq
]=
[cos θ sin θ
− sin θ cos θ
]·[vαvβ
](8)
Substituting the expressions for vα and vβ from Eqns. (4) and (5), we get:
vd =3
2Vm cos(θ − θ) (9)
Let (θ − θ) = δ. Then when the PLL is estimating θ closely,
vd ≈3
2Vm (10)
Dinesh Gopinath Analysis and Design of PLL
![Page 20: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/20.jpg)
3-Phase PLL : Contd...
Similarly we get,
vq =3
2Vm sin(θ − θ) (11)
=3
2Vm sin δ (12)
Now, for very small δ, the loop can be linearised.
Θ(s)
LPF VCO
Θ(s)
∆(s)
1sKf (s)
ˆΩ(s)G32Vm
Now, ω = dθdt = Kf · e.
Where, e = vq =3
2Vm sin δ, and Kf is the gain of the loop-filter.
For θ ≈ θ, sin δ ≈ δ∴ e = 3
2Vm · δDinesh Gopinath Analysis and Design of PLL
![Page 21: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/21.jpg)
3-Phase PLL : Contd...
Closed-loop transfer function is,
Hc(s) =Θ(s)
Θ(s)=
EmKf (s)
s+ EmKf (s)
Where, Em = 32Vm.
We can use a P-I controller for Kf (s), given as:
Kf (s) = Kp +KI
s= Kp
1 + sτ
sτ
Then,
Hc(s) =KpEm · s+
KpEm
τ
s2 +KpEms+KpEm
τ
Dinesh Gopinath Analysis and Design of PLL
![Page 22: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/22.jpg)
3-Phase PLL : Contd...
Comparing with the standard second-order form:The natural frequency,
ωn =
√KpEmτ
and the damping ratio,
ζ = 0.5√KpEmτ
Considering the sampling delays (Ts), the plant T.F is ,
Hplant(s) =1
1 + sTs
1
sEm
The open-loop T.F is then,
HOL(s) = Kp ·1 + sτ
sτ· Em
1
s
1
1 + sTs
Dinesh Gopinath Analysis and Design of PLL
![Page 23: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/23.jpg)
Design of the PI controller
Using the symmetric optimum method, PI controller’s cross-over frequency,ωc = 1
αTs.
and,τ = α2Ts
Kp =1
α· 1
EmTsWhere, α is a scalling factor.For these values,
ζ =α− 1
2
α 2Ts 102.4µsτ 409.6µsVm 339 VKp 9.6ωc 777.12 Hz
For critical damping, ζ = 0.707,ζ 0.707α 2.414Ts 102.4µsτ 596.73µsKp 7.96ωc 643.85 Hz
Dinesh Gopinath Analysis and Design of PLL
![Page 24: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/24.jpg)
An alternate method
Settling time (3 ac cycles),
ts =4
ζωn
Kp = ωnζ2
Em
Tp =4ζ2
KpEm
KI =Kp
Tp
KP (pu) = Kp ·Vbaseωbase
Dinesh Gopinath Analysis and Design of PLL
![Page 25: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/25.jpg)
An alternate method
Settling time (3 ac cycles),
ts =4
ζωn
Kp = ωnζ2
Em
Tp =4ζ2
KpEm
KI =Kp
Tp
KP (pu) = Kp ·Vbaseωbase
Dinesh Gopinath Analysis and Design of PLL
![Page 26: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/26.jpg)
An alternate method
Settling time (3 ac cycles),
ts =4
ζωn
Kp = ωnζ2
Em
Tp =4ζ2
KpEm
KI =Kp
Tp
KP (pu) = Kp ·Vbaseωbase
Dinesh Gopinath Analysis and Design of PLL
![Page 27: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/27.jpg)
An alternate method
Settling time (3 ac cycles),
ts =4
ζωn
Kp = ωnζ2
Em
Tp =4ζ2
KpEm
KI =Kp
Tp
KP (pu) = Kp ·Vbaseωbase
Dinesh Gopinath Analysis and Design of PLL
![Page 28: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/28.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
Dinesh Gopinath Analysis and Design of PLL
![Page 29: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/29.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
Dinesh Gopinath Analysis and Design of PLL
![Page 30: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/30.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Dinesh Gopinath Analysis and Design of PLL
![Page 31: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/31.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Int. op without limit
Dinesh Gopinath Analysis and Design of PLL
![Page 32: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/32.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Int. op without limit
PI op before external limit: ypi
Dinesh Gopinath Analysis and Design of PLL
![Page 33: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/33.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Int. op without limit
PI op before external limit: ypi
PI op after external limit: y(t)
dead-zoneDinesh Gopinath Analysis and Design of PLL
![Page 34: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/34.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Int. op with limit
Dinesh Gopinath Analysis and Design of PLL
![Page 35: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/35.jpg)
PI Controller
Zero steady state errorBetter stability prospects compared to I - controller
K
∫y(t)ypi(t)yp(t)e(t)
yi(t)1Tc
t
e(t)
yp(t)
external limit
Int. op with limitPI op with limit in integrator
Dinesh Gopinath Analysis and Design of PLL
![Page 36: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/36.jpg)
P-I Implementation
AnalogRf
e(t)
-1
Cf
Rin
y(t)
y(t) =Rf
Rine (t) + 1
RinCf
∫e (t) dt
Digital
y(n) = Ke(n) +K
T
[e(n) + e(n− 1)
2
]Ts + y(n− 1)
PI Controller Transfer Function:K(1+sTc)
sTc
Dinesh Gopinath Analysis and Design of PLL
![Page 37: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/37.jpg)
P-I Implementation
AnalogRf
e(t)
-1
Cf
Rin
y(t)
y(t) =Rf
Rine (t) + 1
RinCf
∫e (t) dt
Digital
y(n) = Ke(n) +K
T
[e(n) + e(n− 1)
2
]Ts + y(n− 1)
PI Controller Transfer Function:K(1+sTc)
sTc
Dinesh Gopinath Analysis and Design of PLL
![Page 38: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/38.jpg)
Digital Implementation:Fixed-point Vs Floating-Point
Per-unit systems is adopted for fixed-point implementationsA base value is chosen for all variables (voltage, frequency, phase,current etc)All variables are expressed in p.up.u values are converted in to digital equivalents using fixed-pointarithmeticBase conversion is done as per accuracy requirements
Dinesh Gopinath Analysis and Design of PLL
![Page 39: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/39.jpg)
Digital Implementation: An example
Let the input voltage be varying in the range 230V ± 10%.The maximum voltage is then 357.742VIf the base voltage is chosen as 360V, the maximum possible voltage is0.9937 p.u
Dinesh Gopinath Analysis and Design of PLL
![Page 40: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/40.jpg)
Digital Implementation: An example
In digital implementation, suppose we use a 12 bit ADC with an inputvoltage range ±10V .The ADC will give digital equivalent values as follows:
ADC 12 bit p.u for 5V base p.u for 10V baseinput Digital 5V base 10 V base
voltage output+10 V 7FFh 2 p.u 1 p.u+5 V 3FFh 1 p.u 0.5 p.u
+2.5 V 1FFh 0.5 p.u 0.25 p.u+1.25 V FFh 0.25 p.u 0.125 p.u
0 V 000h 0 p.u 0 p.u-1.25 V F01h -0.25 p. u -0.125 p.u-2.5 V E01h -0.5 p.u -0.25 p. u-5.0 V C01h -1.0 p.u -0.5 p.u-10 V 801h -2.0 p.u -1.0 p.u
Dinesh Gopinath Analysis and Design of PLL
![Page 41: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/41.jpg)
Digital Implementation: An Example
We may choose the input voltage-sensor in different ways.For example:
1 The nominal input voltage range of the ADC is ±10V for themaximum expected input voltage
2 Leave enough room for the input voltage, and choose ±5V as thenominal ADC input voltage range.
In the first case, we must choose the sensor-gain such that the ADC alwaysget a voltage inside its range of ±10V .In the second case, we must choose the sensor-gain in such a way that theADC gets a nominal voltage of 5V when the input voltage is in the nominalrange.Here, however, we can have an unexpected higher voltage signal at the ADCinput upto 2 p.u.Normally, 2 p.u range is kept for signals like current, speed etc.
Dinesh Gopinath Analysis and Design of PLL
![Page 42: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/42.jpg)
Some considerations
Multiplication accuracyIntermediate calculations should be done at higher base values
Changing the base valuesSampling frequency
Dinesh Gopinath Analysis and Design of PLL
![Page 43: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/43.jpg)
FPGA based digital platform
Dinesh Gopinath Analysis and Design of PLL
![Page 44: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/44.jpg)
FPGA platform: features
80 digital I/Os16 Analog input channels (with 6.4 µs A/D conversion time perchannel)8 Analog output channels (with a DAC settling time of 80 ns)ALTERA EP2C70F672C8 FPGA with 68,416 logic elementsUSB and CAN transceiver interfacesOn board SRAM (64K×18)Three clocks at 20 MHz eachJTAG interface
Dinesh Gopinath Analysis and Design of PLL
![Page 45: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/45.jpg)
FPGA platform: Architecture
PC
DAC
ADC
FPGA
config.device
Analog inputs
Analog outputs
Digital I/OBidirectional
Buffers
(20 MHz)
3
SRAM
Clocks
USB & CAN
Figure: Block diagram of FPGA controller
Dinesh Gopinath Analysis and Design of PLL
![Page 46: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/46.jpg)
Experimental results
Dinesh Gopinath Analysis and Design of PLL
![Page 47: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/47.jpg)
Conclusion
Basics of Phase-Locked Loops have been explainedPLLs can be easily implemented in softwareDigital implementation is particularly easy in FPGA platformThere are several PLL methods which vary in complexity and accuracy
Dinesh Gopinath Analysis and Design of PLL
![Page 48: Analysis, Design and Implementation of Phase-Locked-Loop (PLL) …ee.cet.ac.in/downloads/Notes/PE/PLL.pdf · 2019-10-11 · Phase of the source can be extracted by aPhase-Locked-Loop](https://reader034.fdocuments.in/reader034/viewer/2022043008/5f9866cdb5c1c2234f63e347/html5/thumbnails/48.jpg)
Thank You
This presentation was done in LATEX and Beamer
Dinesh Gopinath Analysis and Design of PLL