Semi-Custom Design of Adiabatic Adder Circuits

V S Kanchana Bhaaskaran

S Salivahanan

SSN College of Engineering Chennai 603110

D.S.Emmanuel

Vellore Institute of Technology Vellore 632006

Abstract

The paper presents the design, evaluation andperformance comparison of cell based, low poweradiabatic adder circuits operated by two-phasesinusoidal power clock signals, as against theliteratures providing the operation of variousadiabatic circuits, focusing on inverter circuits andlogic gates, powered by ramp, three phase and fourphase clock signals. The cells are designed for thequasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs forcarry lookahead adders and tree adders weredesigned. The simulations prove that the cell baseddesign of tree adder circuits can save energy rangingfrom 2 to 100 over a frequency range of operation of2MHz to 200MHz against the static CMOS circuitimplementation. The Schematic Edit and T-Spice ofTanner tools formed the simulation environment.

1. Introduction

The power consumption is the principal criterion for

the design and development of portable and high

performance applications. Hence, the trend has been to

search for techniques to reduce the power dissipation,

low power operation, and designing for energy

recovering and recycling. Energy recovery is proving a

promising approach for the design of low power VLSI

circuits. The primary advantage of adiabatic circuits

results from its inherent nature of deriving a constant

current from the power clock and the FETs working

with minimum voltage between the source and drain

terminals [1]. The adiabatic circuits are classified into

fully adiabatic and quasi-adiabatic circuit based on

whether full energy recovery or partial energy recovery

is obtained. The former has no non-adiabatic energy

loss, while the later suffers from both adiabatic and

non-adiabatic energy losses. The power supply

switching noise is generated by the effective

resistance(R) and inductance (Ldi/dt). When a number

of nodes in the circuit switch at the same time, the

effective switching current and hence, the rate of

change of current (di/dt) on the supply line can prove

very large. Since switching occurs with minimum

voltage drop across devices and both the signal and

power supply change slowly, very steep spikes are

effectively removed from the supply current, and this

results in appreciable reduction in switching noise.

The literatures have brought out several types and

genres of adiabatic circuits, namely, 2N-2P, 2N-

2N2P[2], PFAL [9], Pass Transistor Adiabatic Logic

(PAL) [3], Clocked Adiabatic Logic (CAL) [4],

Improved Pass-gate Adiabatic logic (IPGL) [5]

and Adiabatic Differential Switch Logic (ADSL) [6].

They are designed for special functions with custom

oriented designs. Design time is much longer and such

a full custom design is needed only in performance

critical applications. Standard cell-based designing is

therefore preferred for faster design of circuits.

Addition is one of the most commonly used

arithmetic operations. This work aims at cell-based

designing and comparison of 2N-2P, 2N-2N2P, PFAL,

IPGL and ADSL based adiabatic adder circuits.

Schematic designs are made for the individual AND,

XOR, NOT and MULTIPLEXER modules and they are

characterized. They are then employed in the full adder

cell design. This paper presents the design, evaluation,

performance analysis of 8-bit carry look ahead adders

and tree adders constructed using the adder cells

developed.

CIN

CO

A

S

B

Fig. 1 Schematic circuit of one bit full adder

Proceedings of the 19th International Conference on VLSI Design (VLSID’06) 1063-9667/06 $20.00 © 2006 IEEE

VPC

OUTBAR

FBARF

OUT

VPC

OUT

FFB

OUTB

OUT

VPC

F FBAR

OUTB

(a) (b) (c)VPC

FBAR F

OUTBAR

FBARF

OUT

VPCB

VPC

F

VPCB

VPC

OUT OUTB

VPC

FBAR

(d) (e)

Fig.2 Adiabatic circuit families (a) 2N2P

(b) 2N2N2P (c) PFAL (d) IPGL (e) ADSL

2. Adiabatic Cell Design and Design Flow

The realization of full adder is done in a semi-

automatic custom flow as depicted in Fig.1. Fig. 2

depicts the typical circuit arrangement of the adiabatic

circuit families. The individual modules are

constructed using the S-Edit and the designs are

exported to the T-Spice circuit Simulator. The

operational feasibility of the gate is studied for various

frequency ranges and capacitive loads. The functional

block diagram of the full adder circuit is shown in

Fig.3.

3. Adiabatic Adder Designs

The ripple carry adder design was not preferred due

to its reduced speed of operation. Hence the carry

lookahead adder (CLA) structure [7] that possesses

faster carry computation ability and a tree-structured

adder [8] were selected for our study. A cell generator

in C++ program was developed to synthesize the

architecture for structure of the CLA circuit. Fig.4

shows the general schematic arrangement of the

adiabatic 8-bit CLA architecture.

Fig.5 shows the schematic view of a tree adder. The

adder highlighted with a star identifies the full adder

driven by and driving a similar full adder with the

respective sum and carry outputs. We designed a

combinational CMOS one bit adder for comparison.

BBAR

CINBAR

VPC2

XOR

VPC1

A

CIN

SBAR

B

NAND

S

BUFABAR XOR

CO

NAND NAND

COBAR

BUF

Fig.3 Adiabatic Full Adder Block Configuration

S1

CO

B1

B4

S7

A4

S0

S5

S2

A0

B7

B2

A7

S4

A3

B6

B5

A5

B0

A2

S6

A1

B3

A6

S3

Fig. 4. Schematic view of the 8-bit CLA architecture

The literatures provide different one-bit adder

topologies. For a logical evaluation, the same structural

arrangement as followed for adiabatic adders, viz., by

the use of XOR, AND and BUF gate modules was

followed for CMOS adder also.

4. Performance Evaluation and

Comparison

The results of the simulation are presented in this

section. Each of the full adders was analyzed for

energy consumption and the number of transistor

devices employed in the design, which is an indication

of the actual silicon area requirement for the circuit.

The inputs A, B and Ci were supplied as per the

three bit binary counting sequence for uniformity. The

frequency of the power clock was varied from 100Hz

to 200MHz.

The energy dissipation measurement was done from

the simulation outputs, by integrating the power over

the specific period of simulation, which varied from

320ns to 640ms. The average power dissipation of the

circuit was also observed. Fig.6 shows the energy

comparisons made among the adiabatic families

with

S5

B

S5

2 0

1 8

A4

B4

C 4

A4

B

B4

B

C 4

B

A3

B3

C 3

A3

B

B3

B

C 3

B

A2

B2

C 2

A2

B

B2

B

C 2

B

A1

B1

C 1

A1

B

B1

B

C 1

B

A0

B0

C 0

A0

B

B0

B

C 0

B

S0S0

B

S4S4

B

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

1

VPC

2

VPC

2

VPC

1

C BSB C S

12

345678

91 0

1 11 2

1 31 41 5

1 6

2 1

F A

PF

AL

F A

PF

AL

F A

PF

AL

FA

PF

AL

FA

PF

AL

F A

PF

AL

F A

PF

AL

F A

PF

AL

F A

PF

AL

F A

PF

AL

FA

PF

AL

F A

PF

AL

Fig.5 Schematic View of Tree Adder Structure

Proceedings of the 19th International Conference on VLSI Design (VLSID’06) 1063-9667/06 $20.00 © 2006 IEEE

-0.10

-0.05

0.00

200100101

Frequency, MHz

En

erg

y, p

J2N2P 2N2N2P IPGL ADSL CMOS

Fig. 6. Energy comparison of adiabatic adders with

no load capacitances.

-6.E-08

-4.E-08

-2.E-08

0.E+00

0 10 20 30 40 50 60 70 80

Load Capacitance, fF

En

erg

y, J

IPGL 2N2N2P

2N2P CMOS

Fig.7. Energy comparison of 2N2NP, 2N2N2P

AND IPGL adiabatic adders

no load at the sum and carry terminals. The negative

sign indicates the energy dissipated in the circuit. Fig.7

gives the energy consumption for different capacitive

loads for 2N2P, 2N2N2P and IPGL adiabatic adders.

These adders were found to possess higher load-

driving capability than the PFAL and ADSL families,

whose performance is shown in Fig.8. It is to be

pointed out that the PFAL was reported in [9] as

demonstrating the lowest power consumption. Our

work shows that the PFAL adiabatic when driven by

two-phase sinusoidal power clock is more energy

consuming as depicted in Fig. 8 even for low capacity

load conditions.

Figs.9 and 10 show the energy comparisons made

for the 8-bit carry lookahead adder and tree adder

circuits of various adiabatic families The energy

consumption comparisons [9] were made, and the

concept of adiabatic gain G (the ratio between the

energy dissipated by the CMOS gate and the

equivalent adiabatic gate) is used. The Table 1 shows

the transistor counts of the CLA and tree based adder

circuits. The adiabatic gain, G for the case of tree

adder is tabulated in the Table 2 for

comparison.

Table.1 Transistor counts for CLA and Tree Adders

PFAL 2N2P 2N2N2P ADSL

8-BIT CLA 936 700 936 1440

TREE ADDER 648 504 648 936

-8.E-07

-6.E-07

-4.E-07

-2.E-07

0.E+00

0FF 2 4 8 10 14 16

Load Capacitance, fF

En

erg

y,J

PFAL

ADSL

Fig.8. Energy comparison of PFAL and ADSL

adiabatic adders

-3E-07-2E-07-1E-070

300MEG

200MEG

100MEG

Fre

qu

nc

y, M

Hz

Energy, J

2N2N2P 2N2P PFAL ADSL

Fig. 9. Energy comparisons made for 8-bit CLA for

the 2N2P, 2N2N2P, PFAL and ADSL

It can be noted that the adiabatic gain varies from

101.2 at 2MHz to 2.3 at 200MHz as against the

CMOS tree adder.

5. Power Clock Generation

The power clocks used in adiabatic circuits provide

the power for the circuit and behave as clock also.

The resonant energy recovery topology based

on synchronous clock generation is used for clock

generation with the internal time base signals used as

clock timing signals. Current charging as necessitated

for adiabatic circuits is approximated using the

sinusoidal power supply generated by the LC resonant

-1

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.10

200MEG

100MEG

50MEG

20MEG

2MEG

Fre

qu

en

cy

, M

Hz

Energy, pJ

2N2P

2N2N2P

CMOS

PFAL

ADSL

Fig. 10. Energy comparisons made for the tree adders

Proceedings of the 19th International Conference on VLSI Design (VLSID’06) 1063-9667/06 $20.00 © 2006 IEEE

Table.2 Energy consumption and adiabatic gain of

the tree adders with respect to CMOS adders

2N2P2N2N2P

PFAL IPGL

2N CLK

-1.5E-10

-1E-10

-5E-11

0Adiabatic family

En

erg

y, J

Fig. 11. Power dissipation incurred in the adiabatic

inverters and the clock generator circuit

single phase power clock generator circuit of Fig 12.

The circuit modeling was done initially. For a power

loss of , R=LP 2LL IP and C= cDDL fVI2 for a

particular frequency of the clock. The power

conversion efficiency of the clock generator is defined

as the ratio of the total dissipated load power to the total

supply power delivered by the DC supply. It can be

observed that the energy consumed by the clock

generator for its power clock generation is

comparatively less than that consumed by the inverters

of various logic families as shown in Fig. 13.

cf

6. Conclusion

This paper proves the feasibility of operating

the adiabatic circuits by two-phase sinusoidal clock

signals, and, the feasibility of semi custom modular

design approaches for adiabatic designs. The work

compares the adiabatic full adder circuits and multi bit

adder circuits.

For high frequency of operations, the IPGL could

be employed though at higher transistor count and more

area. The 2N-2P and 2N-2N2P circuits provide good

performance at higher frequencies. The Full adder

performance shows that the PFAL circuit experiences

high-energy consumption in high frequency

applications, and ADSL, 2N2P, 2N2N2P and IPGL are

proved to be preferable. The results of Fig. 8 and 9

show that the 2N2P, 2N2N2P and IPGL are more

suitable for operating under high load capacitance

situations as against the ADSL and PFAL based

circuits. It is also observed that the ADSL based adder

is preferable for low voltage and low frequency high

performance applications. The transients in the CMOS

circuits are orders of magnitude higher in comparison

with the adiabatic circuits. The sinusoidal frequency

generates less noise and the skew does not dominate.

Energy savings are achieved in the circuit, even taking

into account the energy consumed for the clock

generation circuitry. The results also show that the

adiabatic circuits could be the most suitable choice,

when the power consumption is considered the primary

criteria for the given range of frequencies.

2N2N2P 2N2P ADSL ADSLM PFAL

200MEG -0.255 -0.229 -0.889 -0.928 -0.604

2.081 2.320 0.598 0.573 0.879100MEG -0.241 -0.127 -0.555 -0.619 -0.529

2.208 4.183 0.958 0.859 1.00550MEG -0.162 -0.093 -0.469 -0.433 -0.302

3.283 5.711 1.132 1.229 1.76120MEG -0.067 -0.048 -0.384 -0.310 -0.122

7.942 10.973 1.383 1.712 4.3722MEG -0.007 -0.005 -0.251 -0.036 -0.010

72.432 101.218 2.113 14.908 50.873

7. Reference

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[3] Vojin G Oklobdzija, Dragan Maksimovic and

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[4] Dragan Maksimovic et al.,. “Clocked CMOS adiabatic

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[6] Y.Z.Zhang, H.H.Chen and J.B.Kuo, “0.8 V CMOS

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Proceedings of the 19th International Conference on VLSI Design (VLSID’06) 1063-9667/06 $20.00 © 2006 IEEE