Full-Adder The Binary Adder - Imperial College London 9 - adders... · Full-Adder E4.20 Digital IC...
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Topic 9 - 1 Nov-22-10 E4.20 Digital IC Design © Prentice Hall Topic 9 Arithmetic Circuits & Datapaths Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected] Topic 9 - 2 Nov-22-10 E4.20 Digital IC Design © Prentice Hall Bit-Sliced Design Topic 9 - 3 Nov-22-10 E4.20 Digital IC Design © Prentice Hall Full-Adder Topic 9 - 4 Nov-22-10 E4.20 Digital IC Design © Prentice Hall The Binary Adder
Transcript of Full-Adder The Binary Adder - Imperial College London 9 - adders... · Full-Adder E4.20 Digital IC...
Topic 9 - 1 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Topic 9 Arithmetic Circuits &
Datapaths
Peter Cheung Department of Electrical & Electronic Engineering
Imperial College London
URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]
Topic 9 - 2 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Bit-Sliced Design
Topic 9 - 3 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Full-Adder
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The Binary Adder
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Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A ⊕ B Delete = A B
Can also derive expressions for S and C o based on D and P
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The Ripple-Carry Adder
Topic 9 - 7 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Complimentary Static CMOS Full Adder
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Inversion Property
Topic 9 - 9 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Minimize Critical Path by Reducing Inverting Stages
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The better structure: the Mirror Adder
Generate (G) = AB Propagate (P) = A ⊕ B Delete = A B
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The Mirror Adder
• The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.
• When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.
• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output. • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
Topic 9 - 12 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Quasi-Clocked Adder
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Manchester Carry Chain
Topic 9 - 14 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Sizing Manchester Carry Chain
Topic 9 - 15 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Carry-Bypass Adder
Topic 9 - 16 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Manchester-Carry Implementation
Topic 9 - 17 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Carry-Bypass Adder (cont.)
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Carry Ripple versus Carry Bypass
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Carry-Select Adder
Topic 9 - 20 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Carry Select Adder: Critical Path
Topic 9 - 21 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Linear Carry Select
Topic 9 - 22 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Square Root Carry Select
Topic 9 - 23 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
Adder Delays - Comparison
Topic 9 - 24 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
LookAhead - Basic Idea
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Look-Ahead: Topology
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The Array Multiplier
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The MxN Array Multiplier — Critical Path
Critical Path 1 & 2
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Carry-Save Multiplier
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Adder Cells in Array Multiplier
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Multiplier Floorplan
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Multipliers —Summary
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The Binary Shifter
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The Barrel Shifter
Area Dominated by Wiring Topic 9 - 34 Nov-22-10 E4.20 Digital IC Design © Prentice Hall
4x4 barrel shifter
Widthbarrel ~ 2 pm M
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Logarithmic Shifter
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A 3
A 2
A 1
A 0
Out3
Out2
Out1
Out0
0-7 bit Logarithmic Shifter
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Design as a Trade-Off
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Layout Strategies for Bit-Sliced Datapaths
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Layout of Bit-sliced Datapaths
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Layout of Bit-sliced Datapaths
