ABC

ABC: A System for Sequential Synthesis and VerificationCurrently under development by Berkeley Logic Synthesis and Verification Group

Contents of this pageIntroductionWhy a new system?What is in the current release?What is not in the current release?Obtaining ABCCompiling and runningCommand summary

Basic commandsFPGA mapping commandsFraiging commandsI/O commandsPrinting commandsStandard cell mapping commandsSynthesis commandsVarious commandsVerification commands

Acknowledgements

IntroductionABC is a growing software system for synthesis and verification of binary sequential logic circuitsappearing in synchronous hardware designs. ABC combines fast scalable logic optimization based onAnd-Inverter Graphs (AIG) with innovative algorithms for integrated sequential optimization andverification. ABC is meant to provide an experimental implementation of these algorithms and, at thesame time, become a convenient programming environment for building similar applications in thefuture. The current experimental release of ABC is the first one in the line of several planned releases.It contains the basic data structures with limited synthesis and verification options. Futuredevelopment will focus on advanced combinational and sequential transformations.

Why a new system?Data structures and algorithms at the heart of a software system determine its capabilities inprocessing data and its efficiency as a programming environment for building new applications.Extensive experience of developing and using SIS, VIS, and MVSIS, made it clear that none of these

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systems provides a flexible programming environment that is efficient enough to implement recentinnovations, such as integrated sequential optimization. Specifically, the SIS environment is outdatedand rather inefficient when handling large circuits. VIS, designed as a formal verification tool formulti-valued specifications, does not provide enough flexibility for binary synthesis. MVSIS wasdeveloped and extensively used by us in the recent years for implementing new synthesis algorithmsfor both multi-valued and binary networks. Finally, we became convinced that (a) the basic datastructures and algorithms of MVSIS can be made considerably simpler and easier to use by assumingbinary networks, and (b) a central place in the new system should be given to a new data structure,AIGs, which promises dramatic improvements in quality and runtime of synthesis and verification.This understanding motivates us to redevelop the core packages of MVSIS resulting in a newprogramming environment named ABC. As the name suggests, the primary goal is to keep datastructures simple and flexible for a wide range of applications. The philosophy of ABC has severalbasic premises. One of them is allowing a variety of functional representations, such as BDDs andSOPs, for solving specialized tasks, while defaulting to AIGs for the mainstream networkmanipulation. Representing logic using AIGs, multi-level networks composed of two-input ANDgates and inverters, leads to a remarkable uniformity in computation and efficient interfacing with theSAT solver for handing Boolean reasoning problems. Another fundamental premise of ABC is thesynergy between synthesis and verification achieved by recording synthesis operations using an AIGdatabase and enabling efficient SAT-based verification relying on the advantageous properties ofAIGs.The current release is the first step of the three-step development process. The release contains thefoundations of the framework and the basics of combinational synthesis. The next two steps are: (1)implementing high-quality yet fast and scalable combinational optimization based on Booleandecomposition, dont-cares, and new ways of sharing logic using AIGs, and (2) developing a fullyintegrated sequential optimization flow, which performs the combinational optimization andtechnology mapping in a combined fashion while optimizing across the latch boundary. The resultsobtained by prototyping these algorithms in MVSIS confirm the practicality of the projected work.The ultimate goal is to provide a public-domain experimental implementation of the above algorithmsand, at the same time, create an open-source environment, in which such applications could be easilydeveloped and experimented with. The experimental implementation should be able to optimize/map/retime for optimal delay and heuristically minimized area, followed by unbounded sequentialequivalence checking, industrial gate-level designs with 100K gates and 10K sequential elements inabout one minute of CPU time on a modern computer. Far-fetched as this goal may sound today, webelieve it will be achieved in the near future.

What is in the current release?- Basic data structures to represent and manipulate combinational and sequential technology-

independent networks in a variety of ways: as a netlist, as an AIG, as a logic network withnodes represented by SOPs (a SIS-style network), as a logic network with nodes representedby BDDs (a BDS-style network), as a technology mapped network, etc.

- Input file parsers for BLIF, BENCH (ISCAS) format, a limited subset of structural Verilog



(needed to read IWLS 2005 benchmarks).- Output file writers for BLIF, BENCH (ISCAS) format, CNF (for combinational miters), and

mapped BLIF (.gate format).- Procedures to perform various manipulations on logic networks: creating combinational and

sequential miters (product machines), unrolling sequential circuits for a number of timeframes,performing fast structural hashing and balancing of AIGs, etc.

- A simple and fast logic synthesis engine, which performs partial collapsing and algebraicfactoring of combinational networks (sequential networks are currently considered ascombinational by cutting at the register boundary).

- Procedures to detect and accumulate structurally different representations of Booleanfunctions (FRAIG package).

- Technology mappers for variable-LUT-size FPGAs and standard cells, applicable totraditional logic networks and logic network with structural choices

- Advanced combinational equivalence checking using FRAIG package- Simple bounded sequential equivalence checking, which unrolls sequential circuits for a given

number of timeframes and performs combinational equivalence of the resulting combinationalcircuits

What is not in the current release?- Advanced combinational logic synthesis (extraction of shared logic, dont-care based

optimization, Boolean decomposition, etc)- Sequential synthesis (retiming, integrated retiming and technology mapping, resynthesis using

subsets of unreachable states, etc)- Unbounded sequential equivalence checking, in particular, equivalence checking based on

information about transformations performed during synthesis

Obtaining ABCThe platform-independent source code can be downloaded and used without restrictions.http://www-cad.eecs.berkeley.edu/~alanmi/abc/abc50729.tar.gz (1.9 Mb)The archive contains the following files:



File name File size Operatingsystem

Descriptionabc.dsp 27,936 Windows Visual Studio project fileabc.dsw 529 Windows Visual Studio project fileabc.opt 52,736 Windows Visual Studio project fileabc.plg 29,454 Windows Visual Studio project fileabc.rc 601 Both ABC resource file

abc50729 4,564,222 Linux Binaryabc50729.exe 430,080 Windows Binary

depends.sh 217 Linux Dependency script (courtesy Satrajit Chatterjee)makefile 1,235 Linux Make file (courtesy Satrajit Chatterjee)

src - Both Directory containing source code

Compiling and runningThe code contained in directory src of the archive compiles on both Windows (with Microsoft VisualStudio 6.0 or higher) and Linux (with GCC). To compile on Windows (assuming that Visual Studio isinstalled), unzip the archive, double-click on abc.dsw, select Project -> Rebuild All. The binarynamed abc.exe will be created in directory _TEMP. To compile on Linux, unzip the archive and runmake. The binary named abc will be created in the root directory. The pre-compiled Window andLinux binaries, abc50729.exe and abc50729, are included in the archive. To make use of standardaliases and settings, resource file abc.rc should be present in the working directory when running theprogram.

Command summaryThis section provided a short description of commands implemented in the current release.

Basic commandsBasic commands are similar to those implemented in SIS, VIS, and MVSIS.alias Creates association of a character or a short word with an available command. For example,once alias ps print_stats is entered on the command line, typing ps at the prompt invokes print_stats.A list of standard aliases is included in the distribution in file abc.rc. This file is automatically loadedwhen the program starts.echo Prints a message to the standard output. Used to add human-readable comments that areprinted on the screen while executing script files. The message should be in quotes. For example, line



echo Synthesis present in the script results in word Synthesis printed on the screen.empty Frees all networks currently stored in memory.help Prints the list of all currently implemented commands.history Prints the list of command lines entered by the user since the program is started.ls (Windows only.) Prints the list of files present in the current directory.quit Exits the program.set Sets a parameter on the command line.source Executes a script. For example, given a script file optimize.scr, the line source optimize.scrwill execute the script. The line source x optimize.scr will execute the script and echo each commandon the screen.time Prints two time measurements: (a) the time the program spent computing since the lastinvocation of command time and (b) the time the program spent computing since it was started.unalias Removes an alias previously set by command alias.undo Sets the current network to the network saved before executing the last command, whichchanges networks. For example, command print_stats does not change the network. So running undoafter print_stats will set the current network to be the one before the last command that has changedit. If the last such command before print_stats was map, the current network after undo will be as itwas before mapping.

FPGA mapping commandsThe FGPA mapping options are currently limited to variable-LUT-size mapping, in which LUT ofeach size is characterized by area and delay. The largest allowed size of a LUT is 6 inputs. Theprogram maps the circuit to achieve optimal delay using classical algorithms for DAG-mapping,followed by a heuristic area recovery. The mapping performed is a generic LUT mapping that doesnot take into account specific FPGA architecture, which typically contains not only programmableLUTs but programmable macrocells as well. The macrocells may contain LUTs mixed with MUXesand other gates. Fine-tuning the mapping process for a specific architecture may significantly improvemapping quality. In the future, an improved version of the FPGA mapper may be developed, whichtakes into account the specific macrocell architecture.fpga Performs FPGA mapping using the currently selected LUT library for the current network. Ifthe current network is an AIG or an AIG with choices, it is used for mapping as it is. If the currentnetwork is a logic network, before mapping this command performs structural hashing of the factoredforms of the nodes (resulting in an AIG) followed by balancing (resulting in an AIG that is



well-balanced for delay). Both balancing and mapping take into account the arrival times of primaryinputs which can be represented in BLIF. Switch a disables area recovery and outputs the network asit is after delay optimal mapping.print_lut Prints the currently selected LUT library. Each LUT size is represented by two numbers(area and delay). The default LUT library is the library of 5-input LUTs.read_lut Read a LUT library from the file and sets it to be the current LUT library. For a simpleexample on representing the LUT library, run print_lut. The print-out has the same format as the inputfile.

Fraiging commandsFRAIG is a software package that constructs And-Inverter Graphs (AIGs) for Boolean functionswhile enforcing functional uniqueness of each AIG node. In the resulting graph, no two nodes havethe same Boolean function, or Boolean functions that are complements of each other. Externally,FRAIG package exposes APIs that are similar to those of a BDD package but internally it usessimulation and SAT. The word fraiging means constructing AIGs in the FRAIG package. Thecapability of FRAIG package to construct functionally reduced AIGs by far exceeds the capability ofthe BDD package to construct BDDs. This makes functionally-reduced AIGs very useful in a varietyof applications in synthesis and verification, and ABC a system possessing unique characteristics notavailable in other tools. The commands in this section provide access to the FRAIG package includedin the current release.fraig Transforms the current network into a functionally-reduced AIG. A variety of command lineoptions available with this command allow for selecting the number of simulation patterns, thenumber of SAT solver backtracks, etc. Command line switch r disables functional reduction. Switchs prevents applying functional reduction to the nodes with sparse functions (the functions, whosesimulation information is composed of all 0s or all 1s.) Switch c toggles recording alternative logicstructures while performing functional reduction.fraig_trust Assumes that the current network was derived by parsing a file, in which the choicenodes (the nodes representing structurally equivalent implementations of logic functions) wererepresented as (multi-input) OR-gates, while all other nodes are two-input AND-gated. Both ORs andANDs can have complemented inputs. This command transforms the network satisfying the aboverestrictions into a functionally reduced AIG in the trust mode (syntactically), without invoking theFRAIG package.fraig_store Stores the current network as one synthesis snapshot in the internal AIG database tobe restored and used for technology mapping later.fraig_restore Converts the currently stored AIG snapshots into a FRAIG and sets it to be thecurrent network, to which technology mapping can now be applied. The AIG database is reset bycalling this command.



fraig_clean Resets the AIG database without restoring it.fraig_sweep Detects functionally equivalent nodes in a logic network. Unlike fraig, whichtransforms the network into a functionally reduced AIG, this command preserves the networkstructure and only merges the functionally equivalent nodes. This command can be applied to themapped network. The resulting network is still mapped but reduced.

Input/Output commandsread Parses an input file using one of the available file readers. The file extension is used todetermine what file parser to invoke. The file extensions that are currently recognized are: .blif,.bench, .v.read_bench Parses the input file in BENCH (ISCAS) format.read_blif Parses the input file in BLIF.read_pla Not implemented in the current release.read_verilog Parses the input file in a subset of structural Verilog, which includes all the keywordsand directives needed for reading IWLS 2005 benchmarks. The parser has several known problems,for example, it does not parse correctly T-latches that are present in some of the designs.write_bench Outputs the current network into a BENCH file.write_blif Outputs the current network into a BLIF file.write_cnf Outputs the current network into a CNF file, which can be used with a variety of SATsolvers. This command is only applicable to combinational miter circuits.write_gate If the current network is mapped using a standard cell library, outputs the currentnetwork into a BLIF file, compatible with SIS and other tools. (The same genlib library has to beselected in SIS before reading the generated file.) The current mapper does not map the registers. As aresult, the mapped BLIF files generated for sequential circuits contain unmapped latches.

Printing commandsprint_factor Prints the factored forms of the nodes in the current network.print_fanio Prints the distribution of nodes by the number of fanins and fanouts.print_io Prints the lists of primary inputs (PI), primary outputs (POs), and latches of the network.



print_stats Prints the statistics of the current networks. The statistics printed depend on the currentnetwork representation.

Standard cell mapping commandsStandard cell mapping implemented in the current release has several important aspects. It is anoptimal-delay DAG mapping based on k-feasible cuts, which is similar to the classical optimal-delayDAG mapping for LUT-based FPGAs. The currently implemented mapping algorithms are gain-based, that is, they find a mapping independent of the load-dependent part of the delay. Thisassumption allows for a simple efficient algorithm, which has a global view of delay. In the future, weplan to implement a load-dependent mapper by post-processing the output of the gain-based mapper.attach Assumes that the current network was mapped but the information about gate assignmentand pin-to-input binding is lost. Attempts to attach the gates from the current library to the logicnodes in such a way that the functionality of the nodes is preserved. The result of this operation is notunique. The delay properties of the resulting network may be different from the original mappednetwork if the gates have different delay-parameters for the pins that correspond to symmetricvariables of the gates. For example, if two pins of NAND2 have different delay-parameters, while thebinding of pins to node inputs is selected arbitrarily, the delay properties will not be preserved.map Performs standard cell mapping of the current network using the current library. If the currentnetwork is an AIG or an AIG with choices, it is used for mapping as it is. If the current network is alogic network, before mapping this command performs structural hashing of the factored forms of thenodes (resulting in an AIG) followed by balancing (resulting in an AIG that is well-balanced fordelay). Both balancing and mapping take into account the arrival times of primary inputs which canbe represented in BLIF. Switch a disables area recovery and outputs the network as it is after delayoptimal mapping. Another useful command, fraig_sweep, is applied after mapping by default (useswitch s to disable) to merge functionally equivalent nodes leading to additional savings in area.print_library Prints the currently selected standard cell library.read_library Reads a standard cell library from a file in GENLIB format.read_super Reads a supergate library from a file using the supergate library format.super Generates supergates for the given standard cell library.super2 Generates input- and delay- limited combinations of two-input ANDs and inverters. Theresulting combinations can be considered technology-independent supergates.unmap Erases the mapping of the current network by replacing each gate by a logic node withfunction equal to the function of the gate.



Synthesis commandsThis section lists several basic synthesis commands implemented in the current release. The availablesynthesis flow is based on repeated application of selective collapsing and algebraic factoring.Currently a logic cone is selected (command renode) and refactored (command strash) while makingno attempts to reduce the number of AIG nodes or factored-form literals. As a result, the synthesisflow is typically 20x faster but gives inferior quality, compared to script.rugged or script.algebraic inSIS and mvsis.rugged in MVSIS. The future releases will address this problem by developing moreintelligent restructuring transformations.Another observation related to synthesis as implemented in the current release, is the deviation fromthe classical approach implemented in SIS and MVSIS. In these tools the node boundaries are alwayskept while optimizing the individual nodes (SIS commands simplify and full_simplify) and whilereshaping one boundary at a time (SIS commands eliminate and resub). In the new system, nodeboundaries are initially destroyed by structural hashing (command strash) and temporarily created(command renode). In a sense, command renode can be seen as a reverse of the SIS commandeliminate because the logic network in ABC is by default completely eliminated while commandrenode creates node boundaries on demand.strash Transforms the current network into an AIG by one-level structural hashing. The resultingAIG is a logic network composed of two-input AND gates and inverters represented as complementedattributes on the edges. Structural hashing is purely combinational transformation, which does notmodify the number and positions of registers.balance Assumes that the input is an AIG and creates an equivalent AIG having the minimumdelay, measured using logic levels of two-input AND-gates. The inverters do not count towards thenumber of logic levels. The resulting AIG is derived by algebraic balancing of the multi-inputAND-gates contained in the original AIG. The balancing is applied in the topological order andselects the minimum delay tree-decomposition of each multi-input AND-gate. Balancing takes intoaccount the arrival times of primary inputs, which can be represented in BLIF.renode Assumes that the input is an AIG. Creates node boundaries in this AIG and collapses theintermediate logic to form larger nodes. After this command is applied, the node functions arerepresented using BDDs.collapse Recursively composes the fanin nodes into the fanout nodes, resulting in a network, inwhich each primary output and latch input is produced by a node, whose fanins are primary inputs andlatch outputs. Collapsing is performed by building global BDD and is therefore limited to relativelysmall circuits. After this command is applied, the node functions are represented using BDDs.cleanup Removes the dangling nodes, that is, the logic nodes that do not fanout into primaryoutputs and latches.

Various commands



bdd If the nodes of the logic network are represented using SOPs, changes the node representationto BDDs.sop If the nodes of the logic network are represented using BDDs, changes the node representationto SOPs.frames Unrolls a sequential circuit for the given number of time-frames. Switch i togglesinitializing the timeframes using the reset values of the latches. If the initialized option is chosen, theresulting network is combinational. If the uninitialized option is chosen, the resulting network is asequential circuit with the same latches and the combinational logic replaced by multiple copies of theoriginal logic.logic Transforms the structural netlist (composed of nets, logic nodes, and registers) into a logicnetwork (composed of logic nodes and registers). In this current version, this command should not becalled by the user. It is called automatically by the system after reading a network from file. As aresult, the user of the current release can only work with AIGs and other types of logic networks.miter Computes the miter of the two networks specified on the command line. If only one circuit isgiven, the miter of this network with the current network is computed. If no network is specified onthe command line, creates the miter of the current network and its spec (the network, which was usedas the starting point for synthesis). If the current network is sequential, computes the sequential miter(the produce machine). The miter has only one primary outputs, which is equal to 1 if and only if thebehavior of the networks differs. The networks, for which the miter computation is called, shouldhave the same number and ordering of PIs, POs, and latches. When sequential miter is computed,there is no restrictions on the number and ordering of latches in the networks.sat Assumes that the current network is a combination miter. Transforms the circuit into CNF andinternally applies a recent version of MiniSat to solve this miter. Alternatively, the miter can bewritten out in CNF (command write_cnf) and solved by an external SAT solver.sis Invokes an external binary of SIS to execute a command or a script for the current ABC network.mvsis Invokes an external binary of MVSIS to execute a command or a script for the current ABCnetwork.

Verification commandsTwo equivalence checking options are currently implemented.cec Combinational equivalence checking compares the PI/PO behaviors of two networks. If latchesare present, the networks are cut at the latch boundary, latch inputs are added to primary outputs, latchoutputs to primary inputs, and the behavior is compared for the extended sets of PIs and POs. Bydefault, a hybrid approach based on fraiging and SAT solving is used to solve the miter. Switch senables a SAT-only approach.



sec Implements bounded sequential equivalence checking for two sequential networks. The productmachine is unrolled for the given number of timeframes specified on the command line using switchf, resulting in a combinational miter. By default, a hybrid approach based on fraiging and SATsolving is used to solve the miter. Switch s enables a SAT-only approach.Since this is the first release of a complex system, it is inevitable that the system has bugs and otherunexpected features. It is highly recommended that verification commands are used as often aspossible during synthesis. Thus, command cec without any arguments can be run between individualsynthesis transformations. Each time this command is invoked, the current network is compared withits specification (derived from the initial file) and the result of comparison is reported to the user.

AcknowledgementsFor stand-alone compilation, the current version of ABC includes the complete source code of thedecision diagram package CUDD (by Fabio Somenzi) and C-language version of MiniSat (by NiklasEn and Niklas Srensson).

Webpage started July 29, 2005, by Alan Mishchenko.



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