A New Space-Vector PWM With Optimal Switching Selection for Multilevel Coupled Inductor Inverters

2354 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010

A New Space-Vector PWM With Optimal SwitchingSelection for Multilevel Coupled Inductor Inverters

Behzad Vafakhah, Student Member, IEEE, John Salmon, Member, IEEE, andAndrew M. Knight, Senior Member, IEEE

Abstract—Multilevel space vector pulsewidth modulation(SVPWM) control is shown to be a very useful tool for cou-pled inductor inverters as six independent pulsewidth modulation(PWM) signals are required, and there is additional complexity ofmeeting the performance requirements for the coupled inductorwhile balancing the winding common-mode dc current and gener-ating high-quality multilevel PWM output voltages. A new multi-level SVPWM technique with a five-segment switching sequence isdescribed, where half-wave symmetrical PWM voltage waveformsare used to balance the inductor common-mode dc voltages andalso to avoid all possible switching states with a high windingcurrent ripple. The proposed SVPWM is shown to have betterinverter performance, compared with traditional carrier-basedand the original multilevel SVPWM schemes at low modulationdepths. Inverter operation with the proposed SVPWM is validatedthrough simulation and experimental results.

Index Terms—Coupled inductor inverter (CII), multilevelinverter, space vector pulsewidth modulation (SVPWM).

I. INTRODUCTION

VARIOUS converter topologies and modulation strategieshave been investigated and implemented for drive appli-

cations. Commonly, a six-switch two-level inverter is used forlow-to-medium-power applications, with the 12-switch multi-level NPC topology being more suitable at higher power levels.Inverter topologies have various advantages and disadvantages,including cost, complexity, and output quality [1]–[5]. If theapplication and power level justify the choice of multileveltopologies [1], [6], one recent alternative multilevel topologyincludes the use of coupled inductors in the output stage of asix-switch inverter [7], [8].

The use of an optimal modulation strategy is essential toassure high-performance operation of the multilevel coupled in-ductor inverter (CII) topology. Initial modulation methods usedfor the CII were based on interleaved sinusoidal pulsewidthmodulation (SPWM) [9], [10] and space vector pulsewidthmodulation (SVPWM) techniques adopted from two-level dis-continuous pulsewidth modulation (PWM) schemes for stan-dard inverters [10]. A modified interleaved DPWM1 schemewas applied to this topology in [7] and [8]. Compared with

Manuscript received March 17, 2009; revised July 19, 2006 and October 5,2009; accepted November 9, 2009. Date of publication January 8, 2010; date ofcurrent version June 11, 2010. This work was supported in part by the CanadianNatural Science and Engineering Research Council.

The authors are with the Department of Electrical and Computer Engi-neering, University of Alberta, Edmonton, AB T6G 2V4, Canada (e-mail:[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2009.2038939

SPWM, DPWM1 can extend the linear modulation range forline-to-line voltages and generates a multilevel voltage withlower harmonic content.

Successful operation of the CII topology over the full mod-ulation range relies on selecting switching states where thecoupled inductor presents a low winding current ripple and ahigh effective inductance between the upper and lower switchesin each inverter leg (high inductance state). In standard SPWMschemes, using either space vector or carrier based, the switch-ing states in each switching cycle are not arbitrarily selectedbut chosen by the reference waveform. Uncontrolled switchingstates can produce low effective inductance connections andproduce a large high-frequency current ripple in the inductorwindings, resulting in high winding Joule losses, core losses,and high-frequency leakage flux outside the magnetic core. Inthis case, even though the output voltage and current wave-forms have low harmonic content, the inverter winding currentcontains high harmonic distortion. Thus, even with high-qualityoutput signals, the overall performance of the CII may be poor,which is a fact that is particularly noticeable at low modulationdepths, as will be shown in this paper. If switching states areuncontrolled, the coupled inductor must be oversized to providesufficient effective inductance in all switching cases.

As an alternative, a multilevel SVPWM scheme based onthose described in [10]–[14] for multilevel inverters has beenapplied to the CII in [15]. With the elimination of some low-inductance states, the multilevel SVPWM is shown to producelower harmonic winding currents. However, this improvementin winding current harmonic content was obtained at the ex-pense of output current quality when compared with interleavedDPWM1.

In this paper, it is shown that winding current harmonicdistortion in a CII is not only dependent to the selection ofswitching states with a high effective inductance but also theswitching sequence and the order of space voltage vectorsin a switching period [10].

A new five-segment multilevel space vector modulationapproach is proposed to eliminate low-inductance switchingstates, minimizing the winding total harmonic distortion (THD)and providing quality outputs for a wide ma operating range.The switching sequence is designed in order to 1) minimize loweffective inductance states; 2) select switching sequence withminimum effects on the inductor winding current deviation;3) balance common-mode dc current; and 4) generate sym-metrical voltage with no even harmonics. The performance ofthe CII topology with the proposed SVPWM is investigatedwith simulation and experimental validation. Comparison with

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VAFAKHAH et al.: NEW SVPWM WITH OPTIMAL SWITCHING SELECTION FOR MULTILEVEL CIIs 2355

Fig. 1. Three-phase multilevel coupled inductor inverter.

previous PWM schemes is included to provide broad insight tothe range of PWM schemes available for the CII topology.

II. CII TOPOLOGY

The multilevel CII topology is shown in Fig. 1. The coupledinductors are placed between the upper and lower switches ineach inverter leg and wound on a three-limb core to eliminateboth fundamental frequency and common-mode dc flux in thecore. This arrangement has a size benefit as the fundamentalfrequency and common-mode dc fluxes are largely canceled,and the total flux density becomes low [17].

In comparison with two-level inverters, a third voltage levelof 1/2Vdc can be achieved when the upper and lower switchesin an inverter leg are simultaneously turned on or off. As aresult, three-level output voltages are possible, when using anappropriate PWM switching control of the upper and lowerswitches in an inverter leg.

As depicted in Fig. 1, a common-mode current icm flowsfrom the upper to the lower coupled inductor in an inverterleg. The common-mode current is the average of the upper andlower winding currents. To produce multilevel signals, optimaloperation of the CII circuit relies on appropriate balancing ofthe common-mode current.

Each of the basic connection options for the three-phaseinductor in the CII are summarized in Fig. 2. It should be notedthat the center tap output connection of each inductor is omittedfrom the diagram for clarity.

Each connection shown in Fig. 2 can be mapped to a voltagevector in the SVPWM, as shown in Fig. 3. The effective induc-tance of a winding in each inverter leg and, hence, the rampingrate of the common-mode current icm depend on which of theseswitching states is being selected [7], [8], [15]. For example,the switching states (a) and (b) in Fig. 2 produce the lowesteffective winding inductance and corresponds to all the inverterswitches being either “on” or “off.” No flux is generated inthe three-limb core, with the much smaller leakage inductancebeing the effective winding inductance. Switching states (a)and (b) frequently occur when using interleaved SPWM orconventional interleaved SVPWM but can be avoided usingDPWM1 [7], [8]. However, the next low-inductance switchingstates, i.e., switching states (f) and (g) in Fig. 2, take place inDPWM1.

The impact of the various switching states on the common-mode winding currents is shown in Table I for phase A.The switching state “P” increases the common-mode windingcurrent icm, and “N” decreases this current by applying +Vdc

and −Vdc across the winding, respectively. Since the inductorwinding is being shorted with the switching states O, no signif-icant change in the common-mode winding current is directlyproduced. However, icm can change in these last two states dueto a small droop caused by semiconductor voltage drops, butmore significantly, magnetic coupling with the windings in theother two inverter legs can cause large changes in icm.

III. SPACE VECTOR MODULATION

SVPWM can be used to choose appropriate switching statesand dwell timing, so that net changes in icm in each phase areavoided using a switching scheme with a zero-average windingvoltage in each phase over a switching cycle Ts while multileveloutput voltages are generated.

A space vector diagram for the three-phase CII is shown inFig. 3 [15]. There are 64 switching states with 19 effectivevoltage space vectors, including a zero-voltage space vector.The three-level voltage space vectors are categorized to zero,small (Vdc/3), medium (Vdc/

√3), and large vectors (2Vdc/3).

This block diagram is similar to a conventional three-levelinverter [10], [11]. However, to obtain the same voltage vectorin each multilevel topology, the switching state is distinct. Forinstance, in this topology, the overlapping switching states area unique feature, eliminating dead-time considerations.

Based on the switching states available for each voltage vec-tor in Fig. 3, combinations of possible inductor configurationsfor each size of voltage vector are given in Table II [15], whichare grouped by the magnitude of the effective coil inductance.Analyzing Table II, the large and medium voltage vectors areonly generated from specific winding configurations. There-fore, there is no freedom in choosing a switching state forvoltage vectors 7–18, indicating that the winding configurationstays the same for large and medium voltage vectors. However,for small voltage vectors (vectors 1–6), using the configurationin Fig. 2(h) is in preference to Fig. 2(i) or 2(j), which are,in turn, preferable to those in Fig. 2(f) or 2(g). Consideringthe zero voltage vector (vector 0), using the configuration inFig. 2(e) is in preference to Fig. 2(c) or 2(d), which are, inturn, preferable to those in Fig. 2(a) or 2(b): the largest effectiveinductance minimizes the winding current and common-modedc current ripples.

IV. PROPOSED APPROACH

SVPWM with a five-segment switching sequence is pro-posed in this paper. The switching sequences are selected tominimize the number of switching occurrences per switchingcycle and the transitions required for Vref when moving fromone sector to another. To choose the switching sequence, thegeneral criteria are summarized as follows:

1) minimizing the effect of the switching state on the induc-tor winding common-mode current deviation.

2) selecting a high-inductance switching state whereverpossible.

3) maintaining half-wave symmetry to cancel even line-to-line voltage harmonics [11], [14].


Fig. 2. Three-phase coupled inductor configurations for various switching states.

Fig. 3. CII space vector diagram including switching states.

TABLE ICOMMON-MODE DC CURRENT VARIATION FOR PHASE A (BASED ON

PHASE B AND C WINDINGS THAT ARE OPEN CIRCUIT)

TABLE IIRANKED SWITCHING STATES FOR EACH VOLTAGE LEVEL BASED ON

THE EFFECTIVE WINDING INDUCTANCE (LARGEST TO

SMALLEST FROM LEFT TO RIGHT)

The original SVPWM scheme for CII [15] eliminated theuse of low-inductance configurations of Fig. 2(a), (b), (f),(g), (i), and (j) in small- and zero-voltage states. The newlyproposed scheme in this paper also eliminates the need to usethe configurations of Fig. 2(b) and (c) in zero-voltage states.

Fig. 4. Proposed new switching sequence.

A. Switching Sequence With Minimal Common-Mode DCCurrent Deviation

To minimize the common-mode current deviation, the dwelltime of a given p-type and n-type switching state in Table Ican equally be distributed over a sampling period. In thispaper, a new switching sequence is designed, as shown inFig. 4. Common-mode current variations are balanced over twosuccessive switching cycles, i.e., cycle “A” and “B.”

In Fig. 4, a switching sequence is formed using three volt-age vectors Vx, Vy , and Vz . dx, dy, and dz are allocateddwell time for voltage vectors of a given triangle (Fig. 3)with vertices Vx, Vy , and Vz , respectively. For both switch-ing cycles “A” and “B,” the space vector voltages are ap-plied in the same order x-y-z-y-x with the same dwell time.This approach ensures that the common-mode winding volt-age is balanced over each pair of switching cycle in a giventriangle.


Fig. 5. Coupled inductor winding voltage and phase voltage in each leg based on switching states in sector I-Δ1. (Common-mode voltages are ±Vdc.)

Fig. 6. Coupled inductor winding voltage and phase voltage in each leg based on switching states in sector I-Δ2. (Common-mode voltages are either ±Vdc.)

B. Implementation

Figs. 5–8 show the proposed five-segment switching se-quence with corresponding winding and phase voltages for eachspecific switching state in cycles A and B in sector I for Δ1, Δ2,Δ3, and Δ4.

By observing the two cycles of five-segment switching se-quences in Figs. 5–8, the average winding voltage is balancedover cycles A and B. For example, in Fig. 5, consider the casewhen Vz1 is {11 00 01} in cycle A and Vz2 is {00 11 01}in cycle B: the two switching states generate the same voltagevector in each inverter leg with opposite effects on icm.

The switching sequences in Figs. 5–8 indicate that the pro-posed method is a continuous SVPWM when ma is lowerthan 0.5 and becomes discontinuous SVPWM when ma ishigher than 0.5. (Note that the maximum ma is 1.0.) Con-tinuous SVPWM is observed in triangle Δ1 and Δ3 whilediscontinuous SVPWM for phases A and C is observed in Δ2

and Δ4, respectively. This transition from continuous SVPWMat low modulation indexes to discontinuous SVPWM at highmodulation indices provides the optimal use of advantages ofeach modulation. Discontinuous SVPWM reduces the switch-ing losses and improves the performance at high modulation




indices, whereas continuous SVPWM generates high-qualityoutputs at low modulation indices. The effect of alternatingp-type and n-type switching sequences from cycles A and B canalso be seen in the waveforms and switching tables, as shown inFigs. 5–8. It can also be seen that the output terminal voltagesin every two successive switching cycles are identical.

As mentioned earlier, not only do the high inductance stateshave significant impacts on common-mode current ripple butalso the sequence of switching states in each switching cycleis important. In the proposed switching, the order of the p-typeand n-type vectors in each cycle has been chosen to minimize

the current ripple in each phase. As an example, if the switchingstate shown in Fig. 7 is rearranged, the new switching stateis obtained, as shown in Fig. 9. When compared, the windingvoltages for phases A and C are swapped; in Fig. 7, for thesame switching frequency, the phase B winding voltage limitsthe current ramping rate in each cycle, whereas, in Fig. 9, thecurrent ripple is the maximum and can be obtained by

Δipeakpeak−max =Vdc

L× 1

2fc(1)

where fc is the switching frequency.


Fig. 9. Alternate winding and phase voltage in sector I-Δ3, with poorly chosen switching sequence. (Common-mode voltages are either ±Vdc.)

Fig. 10. Proposed SVPWM: Upper and lower winding currents and outputcurrent in phase A (ma = 0.9).

V. SIMULATIONS RESULTS

Operation of the CII topology with SPWM, DPWM1, andSVPWM was simulated in Simulink for a range of modulationindices ma, using an inverter with 300-V dc-link voltage and15-kHz switching frequency driving a 15-Ω 1-mH three-phaseload. The coupled inductor upper and lower winding induc-tances are 1.5 mH each, and the coupling factor is 0.45 betweenphases and 0.99 in each phase winding.

Upper and lower winding currents and output current inphase A for SVPWM, SPWM, and DPWM1 are shown inFigs. 10–17. Figs. 10 and 14 show these currents for the pro-posed SVPWM, and Figs. 11 and 15 show the currents for theoriginal SVPWM [15] when ma are 0.9 and 0.4, respectively.The simulation results validate that the new proposed algorithmworks over a wide range of modulation depths. Figs. 12 and 16show these currents for SPWM; Figs. 13 and 17 show those forDPWM1.

At ma = 0.9, the peak-to-peak current ripples in SPWM1and DPWM1 are slightly lower, compared with those inSVPWM. However, it can be observed that, for ma = 0.4,the proposed SVPWM has a significantly lower peak-to-peakcurrent ripple. This has been achieved with further elimination

Fig. 11. Original SVPWM: Upper and lower winding currents and outputcurrent in phase A (ma = 0.9).

Fig. 12. SPWM: Upper and lower winding currents and output current inphase A (ma = 0.9).

Fig. 13. DPWM1: Upper and lower winding currents and output current inphase A (ma = 0.9).


Fig. 14. Proposed SVPWM: Upper and lower winding currents and outputcurrent in phase A (ma = 0.4).

Fig. 15. Original SVPWM: Upper and lower winding currents and outputcurrent in phase A (ma = 0.4).

Fig. 16. SPWM: Upper and lower winding currents and output current inphase A (ma = 0.4).

Fig. 17. DPWM1: Upper and lower winding currents and output current inphase A (ma = 0.4).

of switching states (c) and (d) for a zero-voltage vector at lowmodulation depths in the proposed SVPWM.

Additional simulations compare the harmonic spectra ofthe phase-A current, upper and lower winding currents, andVab line-to-line voltage for all PWM schemes (ma = 0.9), asshown in Figs. 18–25. It can be seen that, for a nominal switch-ing frequency of 15 kHz, the effective switching frequency isseen in the output of interleaved SPWM. In addition, DPWM1is doubled (to 30 kHz) in Figs. 22–25. In contrast, the spectra ofthe original SVPWM scheme shown in Figs. 18 and 19 indicate

Fig. 18. Proposed SVPWM: Harmonic spectrum of the (a) phase-A current,(b) upper winding current, and (c) lower winding current (ma = 0.9).

Fig. 19. Proposed SVPWM: line–line-voltage harmonic spectrum(ma = 0.9).

Fig. 20. Original SVPWM: Harmonic spectrum of the (a) phase-A current,(b) upper winding current, and (c) lower winding current (ma = 0.9).

Fig. 21. Original SVPWM: line–line-voltage harmonic spectrum(ma = 0.9).

that the switching frequency seen in the output signal is half ofthe nominal frequency (7.5 kHz).

In the spectra for the proposed SVPWM scheme in Figs. 20and 21, the switching harmonics seen in the output are atthe nominal switching frequency (15 kHz). Considering thewinding current spectra, it can be seen that the effective averageswitching frequency for the SVPWM schemes is only 7.5 kHz:


Fig. 22. SPWM: Harmonic spectrum of the (a) phase-A current, (b) upperwinding current, and (c) lower winding current in the proposed SVPWM(ma = 0.9).

Fig. 23. SPWM: line–line-voltage harmonic spectrum (ma = 0.9).

Fig. 24. DPWM1: Harmonic spectrum of the (a) phase-A current, (b) upperwinding current, and (c) lower winding current in the proposed SVPWM(ma = 0.9).

Fig. 25. DPWM1: line–line-voltage harmonic spectrum (ma = 0.9).

the choice of switching state to minimize switching losses issuch that the SVPWM schemes are, on average, switching athalf the nominal frequency. It can be seen that, unlike theoriginal SVPWM scheme [15], the new proposed SVPWMscheme is capable of providing an output signal with the lowestswitching harmonics at twice the average actual switching fre-quency. This performance is similar to the SPWM and DPWM1

Fig. 26. SVPWM, DPWM1, and SPWM line–line-voltage THD.

Fig. 27. SVPWM, DPWM1, and SPWM phase-A current THD.

Fig. 28. SVPWM, DPWM1, and SPWM phase-A lower windingcurrent THD.

schemes, although, in these schemes, the effective switchingfrequency is equal to the nominal value. Increasing the nominalswitching frequency of the SVPWM scheme, it may be possibleto produce a signal with winding harmonics at 15 kHz andoutput harmonics at 30 kHz, if that is desired.

To compare the performance of SVPWM with SPWM andDPWM1, the harmonic spectra of the output line–line voltageand output current are illustrated as a function of ma in Figs. 26and 27, respectively. By considering line–line-voltage THD, itcan be seen that the SVPWM THD is superior over the fullrange of ma. However, the phase current THD in DPWM1 issuperior over the full range of ma. The SVPWM current THDis low at higher values of ma. However, at low ma, SVPWMTHD is higher than that in DPWM1 and SPWM THD.

Similar to [15], the THD results show that the selection ofdifferent switching states does not change the output currentand voltage profile in SVPWM, and the current and voltagespectra for the original and proposed SVPWMs are coincidentin Figs. 26 and 27. However, it is shown in Figs. 28 and 29that the newly proposed SVPWM with the elimination of allpossible low-inductance switching states has an overall lowerwinding THD. The switching states with the effective highinductance can reduce the THD in the winding current but donot significantly affect the output current or voltage THD. Acomparison of the upper and lower winding current THDs inFigs. 28 and 29 verifies that the overall performance of the pro-posed SVPWM is better than that of the original SVPWM. The


Fig. 29. SVPWM, DPWM1, and SPWM phase-A upper windingcurrent THD.

Fig. 30. Experimental setup of the CII inverter, combined three limb core,interface boards, and a TI DSP controller.

major harmonic reduction occurs in lower ma (ma < 0.5) dueto additional elimination of the low-inductance switching statesof (c) and (d) in Fig. 2 for a zero-voltage space vector. Sincethese switching states occur in modulation depths lower than0.5, THD is also reduced in this modulation range. WindingTHDs in the proposed SVPWM, as shown in Figs. 28 and 29,are significantly lower, compared with those in DPWM1 andSPWM.

VI. EXPERIMENTAL RESULTS

In order to validate the simulation results, the SVPWM,SPWM, and DPWM1 algorithms are implemented using a TITMS320F2812 digital signal processor (DSP). The experimen-tal tests are carried out using a small power converter system, asshown in Fig. 30, with the following parameters: Vdc = 300 V,fc = 15 kHz switching frequency, Ls = 1 mH filter inductance,and Lt = 4.7 mH couple inductor inductance.

Figs. 31 and 32 show the line–line voltage Vab and phase-Acurrent waveforms with ma at 1.0, 0.8, 0.5, and 0.2 with 60 Hz,respectively. Multilevel voltage output waveforms can clearlybe seen in Fig. 31. Upper and lower winding currents andphase-A currents for the proposed SVPWM, the originalSVPWM, DPWM1, and SPWM are plotted in Figs. 33–36,respectively, when ma is 0.4.

These winding current waveforms are close to the simulationresults for ma = 0.4 given in Figs. 14–17. Comparing theproposed SVPWM current waveforms with SPWM, DPWM1,and original SVPWM, the peak-to-peak winding current rippleis significantly reduced at lower modulation depths. In addition,the simulation results clearly showed that the SVPWM schemescompare well with SPWM and DPWM1 at high modulationdepths. Thus, when the full operating range is required, theproposed SVPWM provides superior inverter performance.

Fig. 31. Experimental SVPWM line-to-line voltage (Vab) with (a) ma =1.0, (b) ma = 0.8, (c) ma = 0.5, and (d) ma = 0.2.

Fig. 32. Experimental SVPWM phase-A current with (a) ma = 1.0,(b) ma = 0.8, (c) ma = 0.5, and (d) ma = 0.2.

Fig. 33. Experimental proposed SVPWM upper and lower winding currentsand phase-A current (ma = 0.4, fc = 15 kHz).

Fig. 34. Experimental original SVPWM: upper and lower winding currentsand phase-A current (ma = 0.4, fc = 15 kHz).

Analysis of the experimental waveforms is carried out toevaluate the THD of the proposed SVPWM, original SVPWM,SPWM, and DPWM1. Analysis is presented in plots inFigs. 37–40 for different modulation indices to validate theTHD simulation results presented in Figs. 26–29. The harmonic


Fig. 35. Experimental SPWM upper and lower winding currents and phase-Acurrent (ma = 0.4, fc = 15 kHz).

Fig. 36. Experimental DPWM1 upper and lower winding currents andphase-A current (ma = 0.4, fc = 15 kHz).

Fig. 37. Experimental SVPWM, DPWM1, and SPWM line–line-voltage THD.

Fig. 38. Experimental SVPWM, DPWM1, and SPWM phase-A current THD.

spectra of output line–line voltage and output current are shownas a function of ma in Figs. 37 and 38, respectively. The exper-imental THD results verify that the output current and voltagespectra for the original and proposed SVPWMs are coincident.The experimental line–line-voltage THD closely agrees withthe simulated voltage THD shown in Fig. 26. Experimentaloutput line current THD plots in Fig. 38 have similar profiles tothe simulations in Fig. 27, but the output current THD is higherfor all modulation strategies. Given the agreement in outputvoltage THD, it appears that the total output inductance seenby the system is lower than expected.

The likely cause for the discrepancy in the results is thefact that the experimental inductor was built with a lowerthan expected leakage inductance. The experimental lower and

Fig. 39. Experimental SVPWM, DPWM1, and SPWM phase-A lower wind-ing current THD.

Fig. 40. Experimental SVPWM, DPWM1, and SPWM phase-A upper wind-ing current THD.

upper winding current THDs are plotted in Figs. 39 and 40,respectively. The experimental data show good agreement withthe simulation results shown in Figs. 28 and 29, and validatethe superiority of the proposed SVPWM at low modulationdepths. Winding current THD is limited by the voltage wave-form and coupled inductor magnetizing inductance; hence, anydiscrepancy in leakage inductance between simulations andexperimental results will not impact these results.

VII. CONCLUSION

SVPWM with a new selection of switching sequencesmethod for three-level coupled inductor inverters has beenpresented. The proposed method eliminates all low-inductanceswitching states that contribute to common-mode current har-monic distortion while balancing common-mode winding dcvoltages and reducing winding harmonic distortion. As thewinding current harmonic content affects both copper lossesand core losses in the coupled inductor, the proposed optimalswitching sequence can allow reduction to the size of thecoupled inductor core due to lower harmonic content and lowerwinding root-mean-square current. In addition, concentratingon high-inductance states may allow redesign of the inductorto have a lower overall inductance, as the coupled inductorneed not be designed to enable operation at the low effectiveinductance states.

A comprehensive performance comparison between SPWM,DPWM1 carrier-based modulations, and SVPWM for coupledinductor inverters has been given. The result shows that the pro-posed SVPWM with selection of all high-inductance switchingstates can improve the quality of the winding current profile,particularly at low modulation depths. Providing high-qualityoutputs, the proposed multilevel SVPWM strategy is shown tohave great potential as variable-speed drives. Computer simula-tions and laboratory results have validated the effectiveness ofthe approach. Future work may focus on interleaved multilevel


SVPWM in the attempt to further increase the effective outputfrequency, reducing the magnitude of the output current ripplewhile providing low winding current THD.

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[16] C. Chapelsky, J. Salmon, and A. M. Knight, “High-quality single-phasepower conversion by reconsidering the magnetic components in the outputstage—Building a better half-bridge,” IEEE Trans. Ind. Appl., vol. 45,no. 6, pp. 2048–2055, Nov./Dec. 2009.

[17] A. M. Knight, J. Ewanchuk, and J. C. Salmon, “Coupled three-phaseinductors for interleaved inverter switching,” IEEE Trans. Magn., vol. 44,no. 11, pp. 4119–4122, Nov. 2008.

Behzad Vafakhah (S’07) received the B.Sc. degreein electrical engineering from K. N. Toosi Universityof Technology, Tehran, Iran, in 1998 and the M.Sc.degree in electrical engineering from Sharif Univer-sity of Technology, Tehran, in 2000. He is currentlyworking toward the Ph.D. degree in the Departmentof Electrical and Computer Engineering, Universityof Alberta, Edmonton, AB, Canada.

From 2001 to 2004, he was a Research Assistantwith the Power Electronics Laboratory, University ofTehran, Tehran. At the same time, he was a Design

Engineer with the Abrizan Pump Company, Iran. His current research interestsinclude multilevel power converters, electric drives, pulsewidth modulationtechniques, power electronics in renewable energy applications, and hybridelectric vehicles.

Mr. Vafakhah is a member of the Association of Professional Engineers ofAlberta.

John Salmon (S’86–M’86) received the B.Sc. de-gree in engineering from Imperial College, London,U.K., in 1982, the M.Eng. degree from McGill Uni-versity, Montreal, QC, Canada, in 1984, and thePh.D. degree from Imperial College in 1987.

In 1987, he joined the Department of ElectricalEngineering and Computer Engineering, Universityof Alberta, Edmonton, AB, Canada, as an Assis-tant Professor, and has been a Full Professor since1996. He has conducted industrially funded power-electronics research projects covering a wide range

of applications, such as electronic ballasts for fluorescent lamps and metal-halide HID lamps, utility interface of microturbine generators using high-speedpermanent-magnet generators, medium-voltage industrial drive systems, andsoft starters for medium-voltage induction motors. His current research interestsinclude industrial drive systems and their utility interface multipulse utilityrectifiers, multilevel voltage-source converters, high-speed ac drive systems,and multifunctional pulsewidth-modulated converters.

Andrew M. Knight (S’95–A’98–M’99–SM’06) re-ceived the B.A. degree in electrical and informationsciences and the Ph.D. degree in electrical powerfrom the University of Cambridge, Cambridge, U.K.,in 1994 and 1998, respectively.

In 1999, he joined the University of Alberta,Edmonton, AB, Canada, as an Assistant Professor,and is currently an Associate Professor with theDepartment of Electrical and Computer Engineering.His research interests include efficient utilization ofelectrical energy, including energy conversion and

storage, particularly renewable energy and electrical machines and drives. Inaddition to his interest in the practical aspects of analysis and design of electricmachines, he carried out research on the modeling of nonlinear electromagneticsystems and losses in those systems.

Dr. Knight was a recipient of the IEEE Power and Energy Society Prize PaperAward 2008 and two prize papers from the IAS 2008 Annual Meeting.

A New Space-Vector PWM With Optimal Switching Selection for Multilevel Coupled Inductor Inverters

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