A New Delay-Line Sharing Based CMOS Digital PWM … New Delay-Line Sharing Based CMOS Digital PWM...

A New Delay-Line Sharing Based CMOS Digital PWM Circuit

Yu-Cherng Hung, Kuei-Ching Tsai Department of Electronic Engineering, National Chin-Yi University of Technology

Taichung, Taiwan, R.O.C. [email protected]

Abstract

This paper presents a new circuit design for digital pulse-width modulators (DPWM). This method improves the structure of hybrid DPWM to a more compact architecture by utilizing the separation of MSB (most significant bit) and LSB (least significant bit) groups. In addition, a delay-line function block is shared with MSB and LSB groups to reduce power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at 200 MHz clock frequency and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18

micron CMOS process. The layout area of the chip including I/O pads is 461 m×370 m. The new DPWM design carries the advantages of smaller chip area and low power consumption especially for the high resolution required.

Keywords: Digital Pulse-Width Modulators, DPWM, Pulse-Width Modulation, PWM

1. Introduction

In computing and communication applications, techniques of signal modulation are important and useful for signal processing. Methods of analog pulse modulation can be classified as pulse amplitude modulation (PAM), pulse position modulation (PPM), and pulse width modulation (PWM). Based on the magnitude of signal strength, PAM modulates the original message as a series of data pulses according to the amplitude of the message. In a communication system, however, the modulated data is easily spoiled by circuit and environmental noise interference; the modulated pulse trains will then be distorted signals. The method of PPM modulates the sampled message as single data pulse within different time-slots (phases) according to the message signal. The major drawback of the PPM technique is required clock synchronization at the beginning of each sampled message, and this technique is inherently sensitive to multipath interference. On the receiving side, however, the circuit realization for PPM demodulation is not effortless. When function reliability and high-speed operation are required, the total realization cost for a high-performance PPM circuit is higher than PAM and PWM modulations. The last aforementioned technique, PWM, modulates the sampled message as a train of pulses with various pulse widths according to the signal level. PWM circuits have many advantages such as simple circuit structure, high anti-noise capability, and thus exist for a wide range of practical applications. Nowadays, PWM techniques are utilized in designs of power supply switches and industrial controlling to greatly increase power efficiency. In modern industrial controlling and telecommunication systems, PWM functions as an important and widely used technology [1][2].

Figure 1 shows a conceptual block diagram of an analog PWM architecture [3]. The OSC block is

commonly a signal oscillator which puts out a periodic square waveform and sets the status of the S-R flip-flop. The output of the carrier generator is in general a linear ramp waveform of frequency fs like a saw-toothed wave. An analog input signal (or control voltage) is compared with the given carrier wave to evaluate the analog amplitude in the time domain. The output signal of the comparator is used to reset the S-R flip-flop to generate the desired PWM function. According to the input signal’s amplitude, the S-R flip-flop output will be a train of pulses with proper pulse width. The architecture’s advantages include circuit simplicity and easy realization. Unfortunately, the performance of the architecture suffers from high sensitivity to temperature, process variation, noise interference, etc. In order to relieve these drawbacks, as IC technology innovation progresses and the process is continuously scaled-down, it seems to be a better choice by applying digital techniques to accurately modulate pulse-width. An example of digital PWM architecture is shown in Figure 2 [3]. The function of the time quantizer, instead of the analog carrier generator shown in Fig. 1, is to scale time into a number of

A New Delay-Line Sharing Based CMOS Digital PWM Circuit Yu-Cherng Hung, Kuei-Ching Tsai

International Journal of Advancements in Computing Technology(IJACT) Volume4, Number18,October. 2012 doi:10.4156/ijact.vol4.issue18.21

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discrete time slots of length td. Each output waveform from the time quantizer has a time difference of delay td between each other. A specific time slot is selected by a digital control word d[n] to reset the S-R flip-flop. According to the d[n] setting, the output train is set with the desired pulse-width. The digital modulation has these characteristics: low cost and low sensitivity to process variation for low-resolution requirements (small n); however, larger chip area and higher matching constraints of signal delay are required for high-resolution (large n). In recent years, the digital modulation techniques have already been widely used in electrical, communication, and other digital application fields. In this paper, we propose a new digital PWM circuit with the advantages of reducing circuit elements and sharing of delay elements to achieve a smaller chip area.

The paper is organized as follows. Section 2 briefly reviews various techniques for the realization of digital PWM circuits. Section 3 proposes the new digital PWM (DPWM) circuit. Section 4 shows the simulation results and chip measurements. Finally, a brief conclusion is given in Section 5.

OSCfs

Carrier generator

Control voltage

Frequency=fs

ClearR

SQDPWMout

TH

T

Figure 1. Conceptual block diagram of an analog PWM circuit.

Figure 2. Conceptual block diagram of a digital PWM circuit.

2. Previous work on digital PWM architectures

In this section, we explore various techniques in the literature on digital PWM realization. The circuit design techniques are divided into the following categories.

2.1. DPWM Type I–Counter-based method

Figure 3 shows the block diagram of the counter-based method [4]. The architecture is composed of a counter block, zero detection block, D-type flip-flop, and S-R flip-flop. According to the N setting of the desired duty cycle, clock fsw is first used to load N as an initial value and set the S-R flip-flop status. The initial value of the counter is preset by the duty cycle’s N bits. Then the counter is counted down within a clock frequency of fclk until zero is detected by the zero detection block. At this time, the S-R flip-flop is reset by the D-type flip-flop. For the PWM output signal, time duration of the signal high corresponds to the N-bit setting. In this architecture, circuit operation needs two different frequencies of clocks fsw and fclk. In addition, an ultra high frequency fclk is needed if high resolution (larger N) is required. This method has an appropriately small chip area, but it suffers from relatively high power consumption.


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Figure 3. Type I architecture: Counter type.

2.2. DPWM Type II–Delay line method A conceptual diagram of a tapped delay-line PWM is shown in Figure 4 [4]. The functions of

the counter and zero detecting blocks shown in Fig. 3 are replaced by a multiplexer of 2n ×1 scaled and 2n delay elements. For n-bit resolution, the output period Tclk will be divided by 2n time slots by using 2n identical delay elements. These delay elements can be realized by digital circuits or precise analog circuits. That is, each element produces a relatively small (and identical) time delay of Tclk/2

n. Under either a required high fclk (small Tclk) or high n-bit, it is difficult to realize a precise PWM chip; the clock quality (time delay, jitter, rising/falling time, clocking loading balance, etc.) and matching of 2n delay elements will affect the PWM’s overall precision. As a result, many techniques such as delay-locked delay lines (DLL) are proposed to improve the precision of the delay-line type, but these circuits have become sophisticated and complicated [5-8]. This architecture relieves the problem of high power consumption. However, if the n-bit resolution of DPWM is required (pulse width modulated in 2n states), a delay line with length of 2n stages is needed. The chip area will be extensively greater with increased n. In CMOS sub-micro technologies, the parasitic effects and capacitance coupling noise cannot be ignored. For this architecture, clocking time delay and device mismatch will impact PWM performance.

Figure 4. Type II architecture: Tapped delay-line type.

2.3. DPWM Type III–Hybrid method

Figure 5 shows hybrid DPWM architecture, which is a combination of the counter-based and delay-line methods [9][10]. The method was proposed by B. J. Patella et al. in 2003, trying to achieve a compromise between chip area and power consumption. This method partially


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relieves the problem of high power consumption in type I and required large number of precise delay elements in type II. In Fig. 5, the resolution bits n are divided in bits nd and bits nc. That is, n=nd + nc. Bits nd are used in multiplexer of 2nd:1 scaled for proper waveform selection, whereas bits nc are used for comparison of counter value. Figure 5 shows an example of n=4, nd=2, and nc=2, in which the PWM architecture has pulse-width resolution of sixteen. The architecture will also suffer from larger chip area when higher resolution is required.

Figure 5. Type III architecture: Hybrid DPWM.

2.4. DPWM Type IV–Σ-Δ method [11]

The technique was proposed in the 1960s. A conceptual diagram is shown in Fig. 6, in which there are two adders, a delay block, and a truncator block to form a Σ-Δ modulator. Figure 6 shows that a low-resolution DPWM core cooperates with a Σ-Δ modulator to arrive at an effective, high resolution. Symbols d[n] is the setting of required high resolution, and ed[n] represent the difference between truncator output and required resolution d[n]. The inner adder and delay block form a feedback connection and function as an integrator. The integrator is used to calculate the average values of ed[n]. Based on modulator operation and technique of noise shaping, a higher resolution PWM can be arrived at by using lower PWM core circuit and a Σ-Δ modulator. In this example of Fig. 6, the basic DPWM core has 4-bit low resolution and is capable of high switching frequency, and effective 10-bit resolution is achieved for the whole architecture. In recent years, the Σ-Δ modulation techniques have been more popular in communications and oversampling analog-to-digital converters. When PWM high resolution is required, the method is more accurate than other methods but comes at the expense of high circuit complexity and cost.

Figure 6. Type IV architecture: Σ-Δ DPWM.


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Table 1 briefly summarizes the characteristic comparisons of these methods. Hybrid DPWM

and Σ-Δ DPWM techniques today are often applied to realize PWM function, yet these methodologies have drawbacks of high cost and high circuit complexity. In this work, we propose a new PWM design to further simplify the circuit complexity. In addition, common delay-line elements are utilized to share between MSB and LSB parts. As a result, chip area and power consumption are improved.

Table 1. Comparison of DPWM architectures

3. Proposed DPWM architectures

For high-resolution requirements, the number of delay-line elements (such as D-type flip-flop) in conventional hybrid DPWM architecture increases in proportion to resolution bit n. In this work, we try to reduce the number of delay-line elements.

Figure 7. Duty cycle setting of 4-bit DPWM.

Figure 7 describes an example of 4-bit setting DPWM. In this example, 4-bit resolution

allows pulse-width modulated of sixteen statuses, in which pulse width ranges from 0/16, 1/16, 2/16, …, to 15/16. In Fig. 7, we set the bits S3, S2, S1, and S0 as logic 1, 0, 1, and 0, and each binary weight value of the four bits is 23, 22, 21, and 20 respectively. The duty cycle setting of PWM is calculated as

23×1＋22×0＋21×1＋20×0＝8×1＋4×0＋2×1＋1×0＝10. (1) The pulse-width output of the circuit will set at the tenth status; that is, 9/16.

Figure 8. The resolution bit is divided into the MSB and LSB groups.

In Fig. 8, the motivation of this study is that the 4-bit number will be divided into two parts:

the MSB and LSB groups. Each group has the same binary weight values. In this example, the bit number of MSB must be pre-amplified by weight value of 4. After MSB pre-amplification, the MSB value plus the LSB value also equals the result of (1). The procedures are described as

Counter DPWM

Delay-line DPWM

Hybrid DPWM

Σ-Δ DPWM

Design Complexity Low Low for small n High for larger n

Middle High

Chip Area Low Middle Middle High

Power Consumption Middle Low Middle High

Achievable Resolution n (under a reasonable constraint )

Middle Middle Middle High


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23×1＋22×0＋21×1＋20×0＝22×(21×1＋20×0)＋(21×1＋20×0)＝22×(MSB group)＋(LSB group) the value of the LSB group＝2×1＋1×0＝2, (2) and the value of the MSB group＝4×(2×1＋1×0)＝8. (3)

As a result, the value of

pre-amplified MSB part ＋ LSB part＝8＋2＝10. (4)

Based on the concept of division, a new DPWM circuit with 4-bit resolution is proposed, and the circuit architecture is shown in Figure 9. The architecture is composed of a 2-bit delay-line function block, two 2-bit DPWMFDC (digital PWM with frequency dividing circuit) blocks, and a MSB/LSB combination circuit. The delay line block with reset function is realized by cascading two D-type flip-flops, as shown in Figure 10. Figure 11 shows the circuits in detail for the D0 and D1 sub-blocks. In order to reduce the chip area, the function of delay line block is shared between the operations of the two 2-bit DPWMFDC blocks.

Figure 9. Architecture of the 4-bit new DPWM.

Figure 10. Realization of the delay line block.

Q

D

CK

R

Figure 11. D0 circuit (left) and D1 circuit (right).


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In Fig. 9, the 2-bit DPWMFDC block is comprised of a 2-bit DPWM function succeeded by a frequency divider (÷4) circuit, as shown in Figure 12. This figure also shows the function blocks of the 2-bit DPWMFDC, which includes the 2-bit DPWM circuit, a NOR gate, and a divide-by-4 circuit. The resolution of the 2-bit DPWM is set by C0 and C1. When C0 and C1 are set to “00”, the divide-by-4 function is reset. When C0 and C1 are set in the range of “01”-”11”, the frequency of signal Q is divided by 4 to create proper time intervals. Figure 13 shows the circuit design for 2-bit DPWM in detail [12][13].

Figure 12. 2-bit DPWMFDC.

Mu

x

Figure 13. Circuit design of 2-bit DPWM.

Figure 14. MSB/LSB combination circuit.

Table 2. Duty cycle settings

Figure 14 shows the MSB/LSB combination circuit. Based on the circuit, either the output of the 2-bit DPWMFDC (LSB) or the combinational output of LSB+MSB will be selected by


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controlling bits S0-S3. As a result, the modulated PWM 0/16 to 15/16 outputs will be arrived at by using 2-bit LSB data or a combination of 2-bit LSB plus 2-bit MSB data. This means that when PWM high-resolution n-bit is required, the circuit can be realized by combination of two n/2-bit architectures. Therefore, the number of delay element is reduced from 2n to 2(n/2), and the input scale of multiplexer (Mux) is also reduced from 2n to 2(n/2). Obviously, the chip area and power consumption of the proposed architecture are expected to be smaller than the traditional DPWM. According to S0-S3 setting, Table 2 lists the status of various duty cycles. 4. Simulation and measured results

Based on the TSMC 0.18-μm 1-Polysilicon 6-Metal mixed-mode CMOS technology, the circuit function was verified by HSPICE simulations. Post-layout simulation waveforms of the experimental circuit working at clock signal (CK) of 200 MHz for various duty cycles are shown in Figure 15. From the top track to bottom track of Fig. 15 are clocking signal, output of duty cycle 0/16 (0 %), output of 8/16 (50 %), and output of 15/16 (93.75 %), respectively. A layout diagram of the whole chip is shown on the left of Figure 16. Including the I/O pads, the whole chip area is 461 m×370 m, whereas the core area is only approximately 57 m×30 m. The microphotograph of the experimental chip is shown on the right part of Figure 16.

Figure 15. Post-layout simulations of the proposed DPWM.

Figure 16. Layout diagram and chip microphotograph.


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Functional testing using basic instruments on the chip installed in a solderless breadboard, Figs. 17-18 show the measured results for input triggered at a clock signal of 1 MHz. Under a controlling bits S[3:0]=0001 setting, Fig. 17 shows that the duty cycle of output voltage Vo of the experimental PWM chip is 6.23%, in contrast to the theoretical value of 6.25% (1/16 duty setting). The error is only 0.02% of a whole output period. Figure 18 shows the measured waveform under a S[3:0]=0010 setting. In contrast to theoretical value of 12.5% (2/16 duty setting), the measured result of the duty cycle is 12.47%. The measured results indicate that the experimental chip functions at these settings. Due to the qualities of the clock and the resistance of signal connecting lines, the accuracy of the PWM chip will be affected and degraded. Regarding to higher clock rates and various duty settings, further chip measurement testing are in progress. Table 3 summarizes the current characteristics of the experimental chip for post-layout simulation and real measurements.

Figure 17. The measured result for duty cycle 1/16.

Figure 18. The measured result for duty cycle 2/16.

Table 3. Chip characteristics

Post-Layout Simulations

Chip Measured

Supply Voltage 1.8 V 1.8 V

Maximum Operation Frequency

200 MHz 1 MHz

Power Consumption 1.55 mW

@200MHz, 1.8V

0.024 mW

@1MHz, 1.8V

Chip Area 461m ×370 m

5. Conclusions

This paper presented a survey of various PWM techniques and design of a novel digital PWM architecture. The proposed circuit’s advantages include low-power consumption and relatively smaller chip area. HSPICE post-layout simulations indicated that the 4-bit DPWM works successfully at 200-MHz clock frequency by using the 0.18-μm CMOS process. The

whole chip area is 0.461 mm×0.37 mm and power consumption is 24 W@1 MHz. The chip

core area is only approximately 57 m×30 m. Based on the concept of division, when a large


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resolution n-bit is required, it can be first divided into two parts: the MSB group and LSB group. The circuits for each MSB and LSB part can be efficiently realized. The basic concept can be adopted for other PWM architectures to further reduce the circuit complexity. Acknowledgements

The author acknowledges co-partner Kuei-Ching Tsai for related paper research, simulations,

and circuit layout. Additional thanks goes to the support of the National Chip Implementation Center (CIC) that provided chip tape-out service for this design, and to Taiwan Semiconductor Manufacturing Company Limited that provided the 0.18-μm process. 6. References

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[2] Z. Zheng, G. Li , N. Wang, "Research on control strategy of three-phase high power factor PWM rectifier", International Journal of Digital Content Technology and its Applications (JDCTA), vol. 5, no. 8, pp. 365–373, 2011.

[3] A. Syed, E. Ahmed, D.Maksimovic, and E. Alarcon, “Digital pulse width modulator architectures,” in Proc. IEEE PESC Conf., pp. 4689–4695, 2004.

[4] A. P. Dancy and A. P. Chandrakasan, “Ultra low power control circuits for PWM converters,” in Proc. IEEE PESC Conf., pp. 21–27, 1997.

[5] F. Baronti, D. Lunardini, R. Roncella, and R. Saletti, “A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme,” IEEE J. Solid-State Circuits, vol. 39, pp. 384–387, Feb. 2004.

[6] W.W. Wang, Z.H. Shen, X. Tan, N. Yan and H. Min, “Improved delay-line based digital PWM for DC-DC converters,” Electronics Letters, vol. 47, pp.562–564 , April 2011.

[7] G.-Y. Wei and M. Horowitz, “A low power switching power supply for self-clocked systems,” in Proc. Int. Symp. Low Power Electron. Des., pp. 313–317, 1996.

[8] E. O’Malley and K. Rinne, “A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz,” in Proc. IEEE APEC Conf., pp. 53–59, 2004.

[9] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC–DC converters,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 438–446, Jan. 2003.

[10] V. Yousefzadeh, T. Takayama, and D. Maksimovic, “Hybrid DPWM with digital delay-locked loop,” in Proc. IEEE Comput. Power Electron., pp. 142–148, 2006.

[11] Z. Lukic, N. Rahman, and A. Prodic, “Multi Σ−Δ PWM digital controller IC for DC–DC converters operating at switching frequencies beyond 10 MHz,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1693–1707, Sep. 2007.

[12] Y.C. Hung and K.C. Tsai, “High-Stability LED PWM Driver Core with 16 Levels Capability,” Proceedings of the Fourth Intelligent Living Technology Conference, pp.828–831, 2009.

[13] Y.C. Hung and K.C. Tsai, “High-Frequency 700MHz LED PWM Driver Core with 16 Levels Capability,” Conference on Innovative Applications of System Prototyping and Circuit Design, pp. 368–371, 2009.


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A New Delay-Line Sharing Based CMOS Digital PWM … New Delay-Line Sharing Based CMOS Digital PWM...

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