Lecture Outline - Penn Engineering · Lec 13: February 23, 2017 Combination Logic: CMOS Penn ESE...
Transcript of Lecture Outline - Penn Engineering · Lec 13: February 23, 2017 Combination Logic: CMOS Penn ESE...
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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 13: February 23, 2017 Combination Logic: CMOS
Penn ESE 570 Spring 2017 – Khanna
Lecture Outline
! CMOS Gates " 1st order delay of Gates " Gate design
" Sizing, fanin
! CMOS Worst Case Analysis
2 Penn ESE 570 Spring 2017 – Khanna
Review: 1st Order RC Delay Models
3
! Equivalent circuits used for MOS transistors " Ideal switch + “effective” ON resistance + load capacitance
" Define unit resistance, Ru: “effective” ON resistance of transistor with min length and W=Wu (usually min width)
" nMOS has “effective” ON resistance Rn= Run/κn and capacitances κnCd, κnCg " pMOS has “effective” ON resistance Rp= Rup/κp and capacitances κpCd, κpCg
" scale factors κn ≥ 1 and κp ≥ 1, i.e. Wn = κnWun, Wp = κpWup " Cgb = Cg and Cdb = Csb = Cd for the unit n/pMOS transistors
" NMOS and pMOS transistor at minimum gate length (L) " Capacitance directly proportional to gate width (W) # C = W*C " Conductance directly proportional to gate width (W) # G = W*G " Resistance is inversely proportional to gate width (W) # R = R/W
τ PHL ≈ 0.69 ⋅Cload ⋅Rn Cload ≈ Cdbn + Cdbp + Cint + Cgb
Penn ESE 570 Spring 2017 – Khanna
Review: 1st Order Delay Model -τPHL
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κp κp
1 1 A Y
Rn
2Rnu/κp
Cd
Cd
nCg
nκpCg
κpCd
κpCd
VDD VDD
VDD VDD
VDD VDD
where Wn=Wunit => κn=1, Rn=Run
Wp = κpWunit
κp = µn/ µp = 2
Y
Rp = Rpu/κp = Rn
Cs = Cd= Cdiff
1,κp
1,κp
1,κp
n
2
1
Rp
Penn ESE 570 Spring 2017 – Khanna
Review: 1st Order Delay Model -τPHL
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Rn Cd
Cd
nCg
nκpCg
κpCd
κpCd
VDD VDD
VDD VDD
Y
Rp VDD
VDD
κpCd
nκpCg
κnC κnC
Rn/n
Reff,HL = Rn = Rnu Reff,LH = Rp = Rpu/κp = Rn
Rn Cd nCg
Y
Cload = (1 + κp)(Cd + nCg)
τ PHL ≈ 0.69RnCload = 0.69Rn (1+κ p )(Cd + nCg )
τ PHL = τ PLHPenn ESE 570 Spring 2017 – Khanna
Review: Elmore Delay: Distributed RC network
! The delay from source to node i " N = number of nodes in circuit
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Rik = Rj∑ ⇒ (Rj ∈ [path(s→ 4)∩ path(s→ k)])
τ Di = CkRikk=1
N
∑
τ Di =C1(R1)+C2 (R1)+C3(R1 + R3)+C4 (R1 + R3)+Ci (R1 + R3 + Ri )
(0 # 50%)
τ D = RpCload (0 # 63%)
NOTE:
τ p = 0.69τ DPenn ESE 570 Spring 2017 – Khanna
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Combinational Logic
CMOS
Penn ESE 570 Spring 2017 – Khanna
CMOS Combinational Logic
! Complimentary MOSFET " Pull-up/pull-down complimentary networks
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pMOS Net = dual (nMOS Net)
Penn ESE 570 Spring 2017 – Khanna
Two-Input NOR Gate (NOR2)
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For Complimentary CMOS: Pull-up Net = dual (Pull-down Net)
F (VF) A (VA)
Z (VZ)
B (VB)
A (VA)
B (VB)
(A . B)
F (VF)
(A + B)
(A . B) (A + B) = Penn ESE 570 Spring 2017 – Khanna
Data Dependent Delay
! Drive resistance depends on input values " Delay depends on input data " Analyze using worst case delay
10 Penn ESE 570 Spring 2017 – Khanna
1st Order Switch-RC Transistor Models
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nMOS
Rn = Run
Assume: bulk at GND
Cg
Cd
Cd
ON/OFF
(W/L)n
pMOS VDD
VDD VDD Rp = Rup/κp
Assume: bulk at VDD κpCd
κpCd ON/OFF
(W/L)p
κpCg
(W/L)n = κn (W/L)un where typically κn = 1
(W/L)p = κp (W/L)up
For an INV κp = µn/µp
Penn ESE 570 Spring 2017 – Khanna
1st Order Switch-RC Transistor Models
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nMOS
Rn = Run/κn
Assume: bulk at GND
κnCg
κnCd
κnCd
ON/OFF
(W/L)n
pMOS VDD
VDD VDD Rp = Rup/κp
Assume: bulk at VDD κpCd
κpCd ON/OFF
(W/L)p
κpCg
Rup ≈VDDLup
0.69µpCoxWup(VDD− |VT 0 p |)2
Run ≈VDDLun
0.69µnCoxWun (VDD −VT 0n )2
(W/L)n = κn (W/L)un
(W/L)p = κp (W/L)up
Rup= µn/µp Run
Penn ESE 570 Spring 2017 – Khanna
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Data Dependent Delay
! Drive resistance depends on input values " Delay depends on input data " Analyze using worst case delay
! Reminder: " Rn= Run/κn
" Rp= Rup/κp
" Assume: µn=2µp
" What is Rout? " Output drive resistance
13 Penn ESE 570 Spring 2017 – Khanna
Data Dependent Delay
! Drive resistance depends on input values " Delay depends on input data " Analyze using worst case delay
! Reminder: " Rn= Run/κn
" Rp= Rup/κp
" Assume: µn=2µp
" What is Rout? " Depends on input
" What is worst case Rout?
14 Penn ESE 570 Spring 2017 – Khanna
Data Dependent Delay
! Drive resistance depends on input values " Delay depends on input data " Analyze using worst case delay
! Reminder: " Rn= Run/κn
" Rp= Rup/κp
" Assume: µn=2µp
" What is Rout? " Depends on input
" What is worst case Rout? " Choose κp and κn, such that worst-case Rout=Run/2
15 Penn ESE 570 Spring 2017 – Khanna
Data Dependent Delay
! Drive resistance depends on input values " Delay depends on input data " Analyze using worst case delay
! Reminder: " Rn= Run/κn
" Rp= Rup/κp
" Assume: µn=2µp
" What is Rout? " Depends on input
" What is worst case Rout? " What is input capacitance?
16 Penn ESE 570 Spring 2017 – Khanna
NAND2 – 1st Order Models
! Reminder: " Rn= Run/κn
" Rp= Rup/κp
" Assume: µn=2µp
" Choose κp and κn, such that worst-case Rout=Run/2 " What is input capacitance?
17 Penn ESE 570 Spring 2017 – Khanna
1st Order Switch-RC: INV
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INV pull-down Net
VDD
INV pull-up Net VDD
Rout = Rp
Rout= Rn
(W/L)n = κn (W/L)un Rn = κn Run
(W/L)p = κp (W/L)up
Rp = κp Rup
Rup = µn/µp Run
Penn ESE 570 Spring 2017 – Khanna
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1st Order Switch-RC: NOR2
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Rout = 2Rp
VDD VDD
2-input NOR pull-up Net
Rout= Rn/2
2-input NOR pull-down Net
(W/L)n = κn (W/L)un Rn = κn Run
(W/L)p = κp (W/L)up
Rp = κp Rup
Rup = µn/µp Run
OR Rout= Rn
Penn ESE 570 Spring 2017 – Khanna
1st Order Switch-RC: NAND2
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Rout = 2Rn
2-input NAND pull-down Net
Rout = Rp/2
VDD VDD
2-input NAND pull-up Net
(W/L)n = κn (W/L)un Rn = κn Run
(W/L)p = κp (W/L)up
Rp = κp Rup
Rup = µn/µp Run
OR VDD VDD
Rout = Rp
Penn ESE 570 Spring 2017 – Khanna
Series Transistors
21 Penn ESE 570 Spring 2017 – Khanna
Transistor Sizing
! What gate is this? ! Size (κp and κn) equalize rise/fall
times Rout=Run/2? ! Input Capacitance?
22 Penn ESE 570 Spring 2017 – Khanna
Transistor Sizing
! NAND2 sized for Rout=Run/2 " κp=4 and κn=4 " Cin=8Cg
! NAND3 sized for Rout=Run/2 " κp=4 and κn=6 " Cin=10Cg
23 Penn ESE 570 Spring 2017 – Khanna
Increasing Fanin
! What happens to input capacitance as fanin (k) increases " Keeping output drive the same
" E.g. Rdrive=R0/2
! k-input nand gate has what input capacitance?
24 Penn ESE 570 Spring 2017 – Khanna
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Fanin
! Conclude: gates slow down with fanin " Less drive per input capacitance " CInLoad/Ids increases
25 Penn ESE 570 Spring 2017 – Khanna
Transistor Sizing: INV
! Size (κp and κn) equalize rise/fall times Rout=Run/2?
! Input Capacitance?
26 Penn ESE 570 Spring 2017 – Khanna
Which is Faster?
! nand32 Assume: - Rup=2Run and gates are sized for Rout=Run/2 - Input also driven by Rdrive = Run/2
nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 27 Penn ESE 570 Spring 2017 – Khanna
Lesson
! Large gates are slow / inefficient " High capacitive load / drive current
! Small gates can be inefficient " Need many stages
! Staging over moderate size gates minimizes delay ! Exact size will be technology dependent
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And-Or Chain
Penn ESE 570 Spring 2017 – Khanna
Delay of each implementation?
30 Penn ESE 570 Spring 2017 – Khanna
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Take Away?
31 Penn ESE 570 Spring 2017 – Khanna
CMOS NOR2 VTC
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
3 VTC Cases V1 = 0 V; V2 = 0 → VDD V1 = 0 → VDD; V2 = 0 V1 and V2 = 0 → VDD simultaneously
Vout
Vin 0
simultaneous switching
only one input
switches
VDD
Switching Threshold Voltage: V1 = V2 = Vout = Vth
Penn ESE 570 Spring 2017 – Khanna
Switch-RC Transistor Models
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
RnEQV= Rn/2 (W/L)nEQV = 2 (W/L)n
VDD VDD
RpEQV = 2Rp (W/L)pEQV = 1/2 (W/L)p
2-input NOR Nets
Penn ESE 570 Spring 2017 – Khanna
CMOS NOR2 Vth
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2017 – Khanna
k pEQV= k p/2
k nEQV= 2k n
k p
k p
k n k n
Review: CMOS Inverter: Vth
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k 'n2
WL
!
"#
$
%&n
Vin −VT 0n( )2 =k 'p2
WL
!
"#
$
%&p
Vin −VDD −VT 0 p( )2
kR Vth −VT 0n( )2 = Vth −VDD −VT 0 p( )22
Vth =VT 0n +
1kR
VDD +VT 0 p( )
1+ 1kR
Typically, Ln=Lp=Lmin
kR =k 'n W L( )nk 'p W L( )p
=µn W L( )nµp W L( )p
=µnWn
µpWp
Penn ESE 570 Spring 2017 – Khanna
CMOS NOR2 Vth
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Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
Penn ESE 570 Spring 2017 – Khanna
k pEQV= k p/2
k nEQV= 2k n
k p
k p
k n k n
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CMOS NOR2 Vth
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k pEQV= k p/2
k nEQV= 2k n
k p
k p
k n k n
Vth =VDD2
kpEQVknEQV
=1
Symmetric ‘Inv’
&
kp = 4knPenn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD
Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg
RpEQV = Rp2+Rp1 Lumped Model Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD
Elmore Model? Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg
RpEQV = Rp2+Rp1
Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
8
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
τ = (2Cd)(Rp2)+(3Cd+Cint+2Cg)(Rp1+Rp2)
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
45
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0
Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
46
Vx
2Cg
Cdbn1 = Cdbn2 = Cd
Cdbp1 = Cdbp2 = Cd
Csb1p = Csb2p = Cd Cd
Cd
Cd
Cd Cd
V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0
Elmore Model? Penn ESE 570 Spring 2017 – Khanna
Parasitic Caps for NOR2 (worst case)
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Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
Parasitic Caps for NOR2 (worst case)
48
Vx
2Cg
Cd
Cd
Cd
Cd Cd
Penn ESE 570 Spring 2016 – Khanna
τ = (2Cd)(Rp1+Rn2)+(3Cd+Cint+2Cg)(Rn2)
9
49
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
RnEQV= 2Rn (W/L)nEQV = 1/2 (W/L)n
VDD VDD
RpEQV = Rp/2 (W/L)pEQV = 2 (W/L)p
2-input NAND Nets
Switch-RC Transistor Models
Penn ESE 570 Spring 2017 – Khanna
50
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
CMOS NAND2 Vth
k pEQV= 2 k p
k nEQV= kn/2k n
k n
k p k p
Penn ESE 570 Spring 2017 – Khanna
51
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
CMOS NAND2 Vth
k pEQV= 2 k p
k nEQV= kn/2k n
k n
k p k p
Penn ESE 570 Spring 2017 – Khanna
52
Kenneth R. Laker, University of Pennsylvania,
updated 26Feb15
CMOS NAND2 Vth
k pEQV= 2 k p
k nEQV= kn/2k n
k n
k p k p
Vth =VDD2
kpEQVknEQV
=1
Symmetric ‘Inv’
&
4kp = knPenn ESE 570 Spring 2017 – Khanna
53
Vx
V1
V2
2Cg
Cdbp1 = Cdbp2 = Cdbp
Cdbn1 = Cdbn2 = Cdbn
Csb1n = Csb2n = Csbn = Cdbn
Parasitic Caps for NAND2 (worst case)
Penn ESE 570 Spring 2017 – Khanna
54
Vx
V1
V2
2Cg
Cdbp1 = Cdbp2 = Cdbp
Cdbn1 = Cdbn2 = Cdbn
Csb1n = Csb2n = Csbn = Cdbn
Parasitic Caps for NAND2 (worst case)
Penn ESE 570 Spring 2017 – Khanna
10
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Vx
V1
V2
2Cg
Cdbp1 = Cdbp2 = Cdbp
Cdbn1 = Cdbn2 = Cdbn
Csb1n = Csb2n = Csbn = Cdbn
Parasitic Caps for NAND2 (worst case)
V1 = VDD, V2 = VDD-> 0 @t=0 & Vx ≈ Vout= 0 ->VDD
Penn ESE 570 Spring 2017 – Khanna
56
Vx
V1
V2
2Cg
Cdbp1 = Cdbp2 = Cdbp
Cdbn1 = Cdbn2 = Cdbn
Csb1n = Csb2n = Csbn = Cdbn
Parasitic Caps for NAND2 (worst case)
Penn ESE 570 Spring 2017 – Khanna
57
Vx
V1
V2
2Cg
Cdbp1 = Cdbp2 = Cdbp
Cdbn1 = Cdbn2 = Cdbn
Csb1n = Csb2n = Csbn = Cdbn
Parasitic Caps for NAND2 (worst case)
V1 =VDD, V2 = 0 ->VDD @t=0 & Vx≈ Vout=VDD-> 0
Penn ESE 570 Spring 2017 – Khanna
Idea
! CMOS Logic " Complimentary dual pull-up/down networks
! Delay " 1st order model on gates " Size for worst case delay
! Gates have different efficiencies " Drive strength per unit input capacitance " Reason to prefer nand over nor
! Large fanin and fanout slow gates " Decompose into stages " …but not too much
58 Penn ESE 570 Spring 2017 – Khanna
Admin
! HW 5 due Thursday, 3/2 ! Details about midterm exam on Tuesday
59 Penn ESE 570 Spring 2017 – Khanna