A Low-Power Precomputation-Based Parallel CAM Chi-Sheng Lin, Jui-Chang, Bin-Da Liu IEEE2003.
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Transcript of A Low-Power Precomputation-Based Parallel CAM Chi-Sheng Lin, Jui-Chang, Bin-Da Liu IEEE2003.
A Low-Power Precomputation-Based Parallel CAM
Chi-Sheng Lin, Jui-Chang, Bin-Da Liu
IEEE2003
Outline
Intro CAM Design concept of PB-CAM Circuit Design of PB-CAM Improved PB-CAM Experimental Results ConclusionConclusion
Intro
Parallel CAM function is used widelylookup tables, databases, associative computing, data compression, etc.
It need large power to achieve parallel CAM
CAM
Design concept of PB-CAM
To reduce the comparison between input and the stored data.
Add parameter extractor, parameter memory.
Design concept of PB-CAM
Design concept of PB-CAM
With an m words by n bits CAM size
PB-CAM:1th comparison: m*upon[log(n+2)]2th comparison: (m*n)/(n+1)Total=1th+2th
CAM:Total=M*(upon[log(n+2)+1])
Design concept of PB-CAM
Circuit Design of PB-CAM
Traditional dynamic CAM:1) The dynamic circuit needs an extra precharge time for
each data searching operation.
2) The dynamic circuit has some problems, such as charge sharing and noise problems.
3) A clock signal is necessary to handle the circuit operation.
4) The noise margin of dynamic circuit is less than .
Traditional dynamic CAM
Circuit Design of PB-CAM
static pseudo-nMOS circuita) In the data searching operation, if the valid bit i
s invalid(v=1) , then the PM1 is turned off and the NM1 is turned on.
b) Otherwise, PM1 is turned on, and NM1 is turned off.
pseudo-nMOS circuit
Circuit Design of PB-CAM
Another problem of pseudo-nMOS circuit. power dissipation
With an m-words CAM size input data only matches one stored data per dat
a searching operation. m-1 data mismatching between stored data and
input data per data searching operation.
Circuit Design of PB-CAM
Circuit Design of PB-CAM
parameter comparison circuit is used to control the pull-up PM1.
Therefore, the number of PB-CAM word circuits that consume static power is reduced to ((m/n-1)-1) .
Circuit Design of PB-CAM
Traditional CAM cell is constructed by typical nine-transistor
six-transistor SRAM cell to store a data bit, an XOR-type comparison circuit containing two nMOS transistors, and an nMOS pull-down device to drive the word match line
Circuit Design of PB-CAM
Circuit Design of PB-CAM
Proposed PB-CAM cell
five-transistor D-latch device to store a data bit and a NAND-type comparison circuit containing two nMOS transistors to drive the word match line.
To achieve low-voltage operation, the feedback inverter (INV2) is a weak-driving design to allow the input data(BL) to be stored in the D-latch device easily.
Circuit Design of PB-CAM
Circuit Design of PB-CAM
Advantage:
1. Searching time is better
2. Simplifies HW design
3. reduces operating voltage Disadvantage
1. Access performance is poorer
Improved PB-CAM
Because of the parameter extraction function
lot difference between probability of parameters.
Table of 14 bits ones-count parameter extractor
Block XOR approach
Block XOR approach
Table of 14 bits Block XOR PB-CAM
Experimental Results
Experimental Results
Experimental Results
ConclusionConclusion
Based on the precomputation methodology, the circuit reduces most of the comparison operations and transistors to achieve low-power, low-cost, and low-voltage features.