A FOUR ELEMENT PHASED ARRAY ANTENNA SYSTEM …
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The Pennsylvania State University The Graduate School College of Engineering A FOUR ELEMENT PHASED ARRAY ANTENNA SYSTEM MONOLITHICALLY IMPLEMENTED ON SILICON A Thesis in Engineering Science and Mechanics by Taeksoo Ji 2004 Taeksoo Ji Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy August 2004
Transcript of A FOUR ELEMENT PHASED ARRAY ANTENNA SYSTEM …
The Pennsylvania State University
The Graduate School
College of Engineering
A FOUR ELEMENT PHASED ARRAY ANTENNA SYSTEM
MONOLITHICALLY IMPLEMENTED ON SILICON
A Thesis in
Engineering Science and Mechanics
by
Taeksoo Ji
2004 Taeksoo Ji
Submitted in Partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
August 2004
The thesis of Taeksoo Ji was reviewed and approved* by the following: Vijay K. Varadan
University Distinguished Professor of Engineering Science and Mechanics, and Electrical Engineering
Thesis Adviser Chair of Committee Jose A. Kollakompil Assistant Professor of Engineering Science and Mechanics Osama Awadelkarim Professor of Engineering Science and Mechanics Jian Xu Assistant Professor of Engineering Science and Mechanics Jerzy Ruzyllo Professor of Electrical Engineering, and Material Science and Engineering Judith A. Todd P.B. Breneman Head of the Department of Engineering Science and Mechanics *Signatures are on file in the Graduate School
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ABSTRACT
Steadily increasing need for wideband wireless communication services have
promoted the development of wireless communication systems with higher data rates and
increased functionality. Phased array antennas are well suited to satisfy the growing
demand with its ability to increase channel capacity and steer multiple beams. Of the
various types of antennas, microstrip antennas would be a good common element in
constructing the array antenna due to their low cost, low weight, conformability, and easy
integration into arrays or use with microwave integrated circuits.
In this research work, a four element phased array antenna aimed for 15GHz has
been monolithically implemented on silicon substrates using monolithic microwave
integrated circuits (MMICs) technology. The array fabricated herein consists mainly of
microstrip radiating patches and feed networks including coplanar waveguide (CPW) –to-
Microstrip (MS) line transitions, phase shifters, Wilkinson power dividers, and DC
blocking filters for CPW and MS lines. Each component of the fabricated array antenna
was carefully designed for operational efficiency, and validated using a custom
simulation tool. All circuits were realized on a high resistivity silicon (HRS) substrate
surface-stabilized by polysilicon. This configuration achieved a significant reduction in
RF losses by immobilizing the surface charges populated in the interface of SiO2/Si. The
monolithic integration of the array antenna into silicon not only makes the whole
circuitry compact, but also reduces the cost utilizing mature CMOS technology.
A single microstrip patch showing a resonance frequency of 14.8GHz with a
return loss (S11) of 21dB is connected to the feed networks based on CPW lines through
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a CPW-to-MS transition. This transition, as well as DC blocking filters for both CPW
and MS lines exhibited the possibility for wideband applications by showing wide 3dB
bandwidths of 168%, 123%, and 130%, respectively. Two types of phase shifter designs
were constructed to compare performance: a microelectromechanical system (MEMS)
phase shifter, and a ferroelectric phase shifter. Despite a high operating voltage of up to
300V, the ferroelectric phase shifter utilizing permittivity tunability of (Ba,Sr)TiO3 (BST)
films was adopted as the phase shifting device in the array due to its high phase shift
capability (~30o/dB), low leakage current level (~300nA at a bias voltage of 100V) and
notably high operational reliability. The four element phased array antenna completely
integrated on silicon showed a total scan capability of 10o measured at its resonance
frequency, 14.85GHz with a return loss of 32dB.
The phased array antenna presented herein will provide a basic view and
understanding of the process of monolithic integration into silicon using MMIC
technology. Improvements of antenna performance in terms of steering capability, side
lobe level (SLL), half power beam width (HPBW) and bandwidth could be accomplished
by further research on design modification as well as on process optimization for array
antennas.
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TABLE OF CONTENTS
LIST OF FIGURES ....................................................................................................... vii
LIST OF TABLES......................................................................................................... xi
ACKNOWLEDGEMENTS........................................................................................... xii
Chapter 1. INTRODUCTION.......................................................................................... 1 1.1 Purpose of Work............................................................................................ 1 1.2 Background ................................................................................................... 4 1.2.1 Si MMICs............................................................................................. 6 1.2.2 Phase Shifters....................................................................................... 7 1.3 Thesis Organization..................................................................................... 10 Chapter 2. LOSS CHARACTERISTICS OF SILICON................................................ 12 2.1 Introduction ................................................................................................. 12 2.2 Design of coplanar waveguide (CPW)........................................................ 15 2.3 Fabrication of the CPWs ............................................................................. 20 2.4 Loss characteristics...................................................................................... 22 2.5 Summary ..................................................................................................... 25 Chapter 3. MEMS PHASE SHIFTER ........................................................................... 26 3.1 Introduction ................................................................................................. 26 3.2 MEMS bridge switches ............................................................................... 27 3.3 Distributed MEMS transmission line (DMTL) ........................................... 34 3.4 Previous MEMS phase shifter research....................................................... 37 3.5 Fabrication................................................................................................... 39 3.5.1 Process flow....................................................................................... 40 3.5.2 Supercritical point dry........................................................................ 42 3.6 Results and Analysis ................................................................................... 45 3.7 Summary ..................................................................................................... 48 Chapter 4. FERROELECTRIC PHASE SHIFTER....................................................... 50 4.1 Introduction ................................................................................................. 50 4.2 Previous works for BST thin film phase shifters ........................................ 52 4.3 Synthesis and properties of BST films sputter-deposited on silicon........... 53 4.4 Analytic formulations for the BST film based phase shifters ..................... 58 4.4.1 Bilateral interdigital CPW (BI-CPW) phase shifter........................... 59 4.4.2 Bilateral coplanar stripline CPW (BCS-CPW) phase shifter............. 62 4.5 Design parameters of BI- and BCS-CPW phase shifters ........................... 61 4.6 Performances of the BST phase shifters...................................................... 65 4.7 Comparison of MEMS and BST phase shifter............................................ 69 4.8 Summary ..................................................................................................... 71
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Chapter 5. MMIC COMPONENTS FOR THE ARRAY ANTENNA.......................... 72 5.1 Microstrip patch .......................................................................................... 72 5.1.1 Design parameters for the patch radiator ........................................... 73 5.1.2 Return loss, and radiation pattern ...................................................... 74 5.2 CPW-to-MS transition................................................................................. 77 5.2.1 Transition description ........................................................................ 77 5.2.1 Transition characteristics ................................................................... 79 5.3 Wilkinson power divider ............................................................................. 81 5.3.1 Design for ACPS power dividers....................................................... 81 5.3.2 Insertion loss, return loss and isolation of the power divider ............ 84 5.4 DC blocking filters ...................................................................................... 86 5.5 Summary ..................................................................................................... 90 Chapter 6. FOUR ELEMENT PHASED ARRAY ANTENNA.................................... 92 6.1 Introduction ................................................................................................. 92 6.2 Array design ................................................................................................ 93 6.2.1 Linear array factor, side lobe level, and beamwidth.......................... 93 6.2.2 Array tapering by Dolph-Chebyshev distribution.............................. 95 6.2.3 Beam steering .................................................................................. 100 6.3 Implementation of a four element array antenna on silicon...................... 101 6.4 Radiation pattern measurements ............................................................... 104 6.4.1 Equipment set up for measurements ................................................ 104 6.4.2 Radiation pattern and beam steering................................................ 105 6.5 Summary ...................................................................................................109 Chapter 7. CONCLUSIONS AND FUTURE WORKS .............................................. 110 Bibliography ................................................................................................................ 115 Appendix: Non-Technical Abstract ............................................................................. 122
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LIST OF FIGURES
Figure 1-1: Schematic diagram of the four element array antenna fabricated.................. 3 Figure 1-2: K-band 16-element linear phased array antenna using Ba0.6Sr0.4TiO3
on 0.3mm MgO phase shifters and microstrip rectangular patch radiators............ 4 Figure 1-3: Layout of the phased array antenna using single-crystal YIG phase
shifters reported by How et al ................................................................................ 5 Figure 1-4: Schematic diagram of a phase shifter resulting in phase shifts at the
device terminal ....................................................................................................... 8 Figure 1-5: Concept of beam steering showing beam steering depending on the
relative phase relationship between the individual elements of phased array antennas .................................................................................................................. 9
Figure 2-1: Configurations to reduce the insertion loss attributed to silicon by (a) inserting a polyimide layer between the CMOS grade silicon and circuits, and (b) micromachining the oxide layer on HRS................................................. 12
Figure 2-2: Surface charges populated in the interface between the SiO2 and HRS ...... 13 Figure 2-3: Schematic of the HRS substrate that is surface-stabilized by undoped
polysilicon and oxide buffer layers to reduce RF insertion losses ....................... 14 Figure 2-4: Unshielded CPW on (a) a single-layered, or (b) a double-layered
dielectric substrate................................................................................................ 15 Figure 2-5: Shielded CPW on a doubled-layered dielectric substrate............................. 16 Figure 2-6: Conformal mapping for a shielded CPW on a double-layered
substrate................................................................................................................ 16 Figure 2-7: Process flow to fabricate CPWs on a silicon substrate................................. 21 Figure 2-8: Insertion loss characteristics of CPWs fabricated on HRS, standard
CMOS grade Si, and quartz.................................................................................. 23 Figure 3-1: Cross section view of a shunt MEMS switch............................................... 27 Figure 3-2: Schematic of cross section of the bridge switch at the up and down
state....................................................................................................................... 29 Figure 3-3: Plot of change in bridge height versus applied voltage versus applied
voltage as RC is varied from 0 to 2 ....................................................................... 30 Figure 3-4: Photographs of shunt switches using (a) meander or (b) hinge
structures to lower the spring constant ................................................................. 31 Figure 3-5: Plot of Young’s modulus against electrical resistivity for various
materials ............................................................................................................... 32 Figure 3-6: Calculated actuation voltages for metal and polymer bridges ..................... 33 Figure 3-7: Schematic of a DMTL phase shifter with MEMS bridges........................... 34 Figure 3-8: Lumped-element transmission line model with variable and fixed
capacitors with periodic spacing, s....................................................................... 35 Figure 3-9: Three-bit distributed MEMS phase shifter ................................................... 37
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Figure 3-10: (a) Schematic of a phase shifter with MEMS bridges and MIM capacitors, and (b) a cross sectional view of the phase shifter............................. 38
Figure 3-11: Phase shifts of the 2 bit phase shifter showing 0/87/183/270o at 20GHz .................................................................................................................. 38
Figure 3-12: Photographs of (a) the three-bit MEMS phase shifter. (b) the four-bit MEMS phase shifter fabricated by Pillans et al ................................................... 39
Figure 3-13: Process flow for the MEMS phase shifter with polymer bridges............... 40 Figure 3-14: Phase diagram for drying procedures ......................................................... 43 Figure 3-15: Photograph of the CO2 critical point dryer ................................................ 44 Figure 3-16: Photograph of the MEMS phase shifter consisting of a high
impedance CPW, loaded periodically with eleven polymer MEMS capacitors.............................................................................................................. 45
Figure 3-17: Measured phase shifts of the MEMS phase shifters, depending on different actuation voltages .................................................................................. 46
Figure 3-18: Plot of leakage currents versus DC bias voltage for the MEMS phase shifter.......................................................................................................... 47
Figure 3-19: Comparison of insertion loss between the simulated and the measured results ................................................................................................... 47
Figure 4-1: Schematics of (Ba,Sr)TiO3 pervoskite unit cell (a) before, and (b) after polarization under external electric fields.................................................... 50
Figure 4-2: Four-element phase shifter using interdigital capacitors .............................. 52 Figure 4-3: Phase shifters employing BST film varactors periodically loaded on a
CPW line .............................................................................................................. 53 Figure 4-4: Configuration of the substrate on which the phase shifter circuit is
defined. BST films are deposited on HRS that is surface-stabilized by poly-silicon and oxide buffer layers in advance................................................... 54
Figure 4-5: Photograph of the RF reactive sputtering system used for BST deposition ............................................................................................................. 55
Figure 4-6: Schematic of the process chamber of the RF reactive sputtering system................................................................................................................... 56
Figure 4-7: (a) X-ray diffraction pattern, and (b) cross-sectional SEM image of BST film deposited on SiO2/poly-Si/Si substrate................................................. 57
Figure 4-8: Schematic diagrams of (a) the bilateral interdigital, and (b) the bilateral coplanar stripline CPW structures to construct BST phase shifters....... 59
Figure 4-9: Schematic view of the unit cell for the BI-CPW phase shifter fabricated on a two-dielectric substrate. The total capacitance in a unit cell consists of two sections, Ccps and Cend.................................................................. 60
Figure 4-10: Schematic view of the unit cell for the BCS-CPW structure. The total capacitance in a unit cell consists of two sections, Coms and Ccpw................ 62
Figure 4-11: (a) Schematic diagram, and (b) photograph of the BI-CPW phase shifter fabricated on BST film.............................................................................. 63
Figure 4-12: (a) Schematic diagram and (b) photograph of the BCS-CPW phase shifter fabricated on BST film.............................................................................. 64
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Figure 4-13: Loss characteristics of the BI-CPW and the BCS-CPW phase shifter ....... 66 Figure 4-14: Input impedance plotted on a Smith chart of (a) the BI-CPW, and
(b) the BCS-CPW phase shifter............................................................................ 67 Figure 4-15: Measured differential phase shifts of the BI-CPW phase shifter with
bias voltages up to 300V ...................................................................................... 68 Figure 4-16: Measured differential phase shifts of the BI-CPW phase shifter with
bias voltages up to 300V ...................................................................................... 68 Figure 4-17: Measured leakage currents of the BST phase shifters ............................... 67 Figure 5-1: Schematic of the single microstrip antenna with a transition from
CPW to MS .......................................................................................................... 73 Figure 5-2: (a) Return loss, and (b) Input impedance of the single microstrip
antenna. The dot loop around the center of the Smith chart indicates a 2:1 SWR bandwidth ................................................................................................... 75
Figure 5-3: Simulated radiation pattern of the single microstrip antenna....................... 77 Figure 5-4: Photograph of the CPW-to-MS transition fabricated on a silicon
substrate................................................................................................................ 78 Figure 5-5: Layout of (a) the back-to-back transition, and (b) the CPW circuit
used for thru calibration standard......................................................................... 79 Figure 5-6: Simulated and measured S parameters of the CPW-to-MS transition.......... 80 Figure 5-7: Schematic diagram of a typical Wilkinson power divider ........................... 82 Figure 5-8: Dimension parameters for ACPS design...................................................... 83 Figure 5-9: Photograph of the Wilkinson power divider fabricated on HRS.................. 84 Figure 5-10: Layout for the ACPS power dividers used to characterize the
propagation performances. PD1, and PD2 were used to measure the insertion loss, return loss, and isolation, respectively. ......................................... 85
Figure 5-11: Measured S parameters for the Wilkinson power divider fabricated on a surface-stabilized HRS substrate .................................................................. 86
Figure 5-12: Photographs and schematic diagram of the DC blocking filters for (a) CPW, and (b) MS, both of which are built on silicon substrates.................... 87
Figure 5-13: Layout of the back-to-back DC blocks as well as the thru calibration standard circuit for (a) MS, and (b) CPW ............................................................ 88
Figure 5-14: Simulated and measured S parameter results for the CPW DC blocking filter ....................................................................................................... 89
Figure 5-15: Simulated and measured S parameter results for the MS DC blocking filter ....................................................................................................... 90
Figure 6-1: Typical power pattern polar plot in steering ................................................ 95 Figure 6-2: Dolph-Chebyshev synthesized array factors for a four element, λ/2
spaced with (a) -20dB, and (b) -40dB side lobes ................................................. 98 Figure 6-3: Array factor for a four element, λ/2 spaced linear arrays with an
uniform current distribution of 1:1:1:1. The obtained HPBW and SLL are 23.3o and 12dB, respectively. ............................................................................... 99
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Figure 6-4: Simulated radiation patterns of the array antenna showing beam steering according to the phase difference(β) between the elements (a) β=30o, (b) β=60o, (c) β=0o, (d) β=-30o, and (e) β=-60o ...................................... 100
Figure 6-5: Photograph of the four element phased array antenna fabricated on a silicon substrate consisting of power dividers, microstrip patch antennas, phase shifters, DC blocks and CPW-to-MS transitions ..................................... 102
Figure 6-6: Fabrication flow for the phased array antenna system............................... 103 Figure 6-7: Set up for radiation pattern measurements ................................................. 104 Figure 6-8: (a) Return loss, and (b) input impedance of the four element phased
array antenna monolithically fabricated on a silicon substrate. The dot loop around the center of the Smith chart indicates a 2:1 SWR bandwidth....... 106
Figure 6-9: Measured and simulated radiation patterns (at φ =90o cut) of the four element phased array antenna at 14.85GHz ....................................................... 107
Figure 6-10: Measured radiation patters showing the capability of beam steering with a phase tilt of the main beam of 5o on each side ........................................ 108
Figure 7-1: Schematic diagram of an aperture-coupled stacked antenna ..................... 114
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LIST OF TABLES
Table 1.1: Applications of MMICs.................................................................................. 6 Table 3.1: Critical dimensions of the polymer MEMS phase shifter fabricated
herein .................................................................................................................. 45 Table 4.1: Sputtering conditions for BST deposition .................................................... 54 Table 4.2: Design parameters of the BI- and BCS-CPW phase shifters using BST
films.................................................................................................................... 65 Table 4-3: Comparison of properties between the MEMS and the BST phase
shifter.................................................................................................................. 70 Table 5.1: Design parameters of the CPW and the MS section constructing the
CPW-to-MS transition........................................................................................ 79 Table 5.2: Design parameters of the DC blocks for CPW and MS............................... 86 Table 6.2: Current magnitude for linear equally spaced Chebyshev and binomial
arrays. Currents of edge elements are unity ....................................................... 99
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ACKNOWLEDGEMENTS
I would first like to express my sincere gratitude to my advisor, Dr. Vijay K.
Varadan, for his valuable guidance, patience, and support throughout the course
of this research. I would also like to thank Dr. Jose A. Kollakompil, Dr. Osama
Awadelkarim, Dr. Jian Xu, and Dr. Jerzy Ruzyllo for serving on my committee
and for all the helpful discussions. Their suggestions are deeply appreciated.
My special thanks are extended to my colleagues of the Center for the
Engineering of Electronic and Acoustic Materials and Devices for their support
and advice. I owe a debt, especially, to Dr. Hargsoon Yoon for his help and
contributions to this thesis.
Most of all, I am thankful to members of my family, especially, my parents and
parents-in-law for their continued support, patience, and love. Without them this
thesis would never have been completed. Finally, I wish to thank my wife,
Soyoun Jung. Her support and encouragement were greatly instrumental to the
completion of my graduate work and this thesis.
To my family, I dedicate this dissertation.
Chapter 1
INTRODUCTION
1.1 Purpose of Work
Demand for broadband wireless communication services has been increasing
explosively, driving the surge of research and development activities for future wireless
communication systems with higher data rates and increased functionality. It is expected
that this demand will be fulfilled by realizing 4G mobile systems which could consist of a
layered combination of different access technologies such as wireless local area networks
(LANs), intelligent transport systems (ITSs), and high altitude stratospheric platform
station systems (HAPS), as well as cellular phones [1]. However, these systems will
require the aid of advanced array antenna technologies to operate efficiently, since an
array antennas have proven to play a key role in improving system performance by
increasing channel capacity, steering multiple beams, and compensating for aperture
distortion electronically [2].
During the past few years, smart (or adaptive) antenna systems adopting these
array systems have been developed for commercial as well as military use to suppress
multipath fading, delay spread and cochannel interferences, resulting in better quality of
services [3]. The array system offers the unique capability of electronic scanning of the
main beam. By changing the phase of the exciting currents in each element antenna of
the array, the radiation pattern can be scanned through space. By this means, the beam
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can be very quickly steered electronically and becomes capable of tracking fast-moving
and multiple targets in a fashion which is impossible with a traditional rotating-dish
antenna.
Of the various types of antennas, microstrip antennas are considered to provide
good common elements in array antenna construction due to their low-cost, low-weight,
conformability, and easy integration into arrays or capability with microwave integrated
circuits [4]. A typical microstrip array antenna is composed of radiating patches and feed
networks. The radiating patches may be square, rectangular, dipole, circular, elliptical,
triangular, or other configuration depending upon required characteristics for specific
applications. The feed networks may include power dividers, phase shifters, and DC
blocks along with transmission lines. Each element should be carefully designed for the
aimed frequency to accomplish optimal performance.
The main purpose of this thesis is the design and fabrication of a four element
phased array antenna operating at 15GHz on a 400µm thick high resistivity silicon (HRS)
substrate using monolithic microwave integrated circuits (MMICs) technology. The
target frequency was chosen taking the actual size of silicon wafers (3 inch) as well as the
upper limitation of our measurement equipment (18GHz) into consideration. Monolithic
integration of the array antenna into silicon not only makes the whole circuitry compact,
but also reduces the cost by utilizing mature CMOS technology. Figure 1-1 shows a
schematic diagram of the phased array antenna systems fabricated herein. It can be seen
that the antenna consists of four rectangular patches, three Wilkinson power dividers,
four phase shifters, four CPW (coplanar waveguide)-to-MS (microstrip) transitions, eight
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MS DC block
Wilkinson Power Divider
Transition CPW-to-MS
CPW DC block
Transition CPW-to-CPW
Microstrip patch
DC blocks, and four RF chokes for biasing to the phase shifters, along with CPW
transmission lines.
Fig. 1-1: Schematic diagram of the four element array antenna fabricated
Phase shifter
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1.2 Background
There have been many notable attempts to develop phased array antenna systems
employing phase shifters for beam steering [5-7]. Romanofsky et al. reported a prototype
K-band linear 16-element scanning phased array antenna based on thin ferroelectric film
coupled microstripline phase shifters and microstrip patch radiators as shown in
Figure 1-2 [5].
How et al. also presented a steerable phased array antenna using single-crystal
yttrium-iron-garnet (YIG) phase shifters (see Figure 1-3). This array antenna tuned the
input phases to the antenna elements by varying the bias magnetic field, resulting in
steering of the radiation beam in one dimensions [6].
Figure 1-2: K-band 16-element linear phased array antenna using Ba0.6Sr0.4TiO3 on 0.3mm MgO phase shifters and microstrip rectangular patch radiators [5]
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Furthermore, Yun et al. demonstrated a multi-frequency phased array antenna
system that consists of a wideband power divider, piezoelectric transducer (PET) phase
shifters, a four-channel multiplexer, MMIC amplifiers, and a stripline-fed Vivaldi
antenna array [7]. Using the PET phase shifters, this array antenna could achieve scan
angles of 38.6o, 37.6o, 43o, and 40o for four channels at 10, 12, 19, and 21 GHz,
respectively.
However, these hybrid array antennas may be not appropriate for constructing a
large phased array antenna since it generally requires several thousand elements fed by a
phase shifter as well as a switch for every antenna element, which is complex in nature.
In this research, emphasis was placed on to implement a four element phased array
antenna system on silicon utilizing the MMIC technology, which would be the first step
to provide a basic view for realizing smart antenna systems with an excellent
performance.
Figure 1-3: Layout of the phased array antenna using single-crystal YIG phase shifters reported by How et al. [6]
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1.2.1 Si MMICs
A monolithic microwave integrated circuit (MMIC) can be defined as a
microwave circuit in which the active and passive components are fabricated on the same
semiconductor substrate. Operation frequency can range from 1GHz to well over
100GHz. While military and space applications continue to drive development, MMIC
technology can also be adapted for numerous civil applications such as mobile phones.
The major applications of MMICs are listed in Table 1.1 [8].
The smart antenna constitutes one of the most important applications for MMICs
because of the impracticality of fabricating a large smart antenna system with hybrid
microwave integrated circuits (MICs) technology due to the size and mass of hundreds of
individual transmitter-receiver modules required in the antenna system. MMICs also
show good reliability, excellent reproducibility, and low fabrication cost when compared
with hybrid MICs.
To date, gallium arsenide (GaAs) has been used predominantly in the
development of MMICs since its semi-insulating properties and high electron mobility
Table 1.1: Applications of MMICs
Military and Space Civil
Steerable phased array antenna Mobile phones
Remote sensing Wireless LANs
Low earth orbit satellites Global positioning (GPS)
Communication satellites Medical systems
Radiometers Anti-collision radar
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make it suitable for microwave applications. However, absence of natural oxide, small
wafer size of less than four inches in diameter with resultant high fabrication cost, and
low thermal conductivity of GaAs are still problematic in MMIC development.
If silicon can be used as a substrate material, many of these drawbacks with GaAs
would be overcome. In addition, by using silicon as substrate materials, standard CMOS
fabrication processes can be employed. However, in spite of its low-cost and high
thermal conductivity, critical characteristics for high power device operation, the use of
standard CMOS grade silicon with low resistivity typically on the order of 0.5 to 20Ωcm
for MMIC applications has been limited by its high loss, especially at an RF frequency
range.
To overcome this problem, all MMIC components constructing the array antenna
in this work have been realized on high resistiviy silicon (HRS) surface-stabilized by
polycrystalline silicon and silicon oxide. This configuration has shown significantly
reduced losses, and will be described in Chapter 2 in detail.
1.2.2 Phase Shifters
A phase shifter is a key element in the phased array antenna, providing a means of
changing the effective path length on a transmission line resulting in phase shifts at the
device terminals, as shown in Figure 1-4. Characteristics of phase shifters required to
construct phase array antennas for telecommunication include a good impedance match,
proper power handling capability, low drive power and fast response speed.
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VVinin=V=V11ee--jjφφ11 VVoutout=V=V11ee--j(j(φφ1+1+ΔφΔφ))ΔφΔφVVinin=V=V11ee--jjφφ11 VVoutout=V=V11ee--j(j(φφ1+1+ΔφΔφ))ΔφΔφ
By manipulating the relative phase relationships between the individual antenna
elements with phase shifters, an inertialess beam can be formed and steered electronically
without mechanical motions, as depicted in Figure 1-5. A typical phased array may have
several thousand elements fed by a phase shifter, as well as a switch for every antenna
element. Therefore, it is also important to take low loss, low cost, and lightweight phase
shifters into consideration when designing and fabricating the array elements.
Of a wide variety of phase shifters that have been shown to meet these
requirements until recently, the electronically variable phase shifters using ferrite
materials developed in 1957 by Reggia and Spencer proved to be a significant milestone,
providing inertialess phase changes in a short time, a capability previously impossible
using the older mechanical phase shifters [9]. In addition to the ferrite phase shifter,
another important type of electronic phase shifter categorized as a semiconductor phase
shifter emerged in the mid-1960s. This semiconductor phase shifter adopted p-i-n diodes
as electronic switches for phase control [10]. Since the appearance of the semiconductor
phase shifter, there have been significant advances in electronic phase shifters, and a new
active type of semiconductor phase shifter using the GaAs FET (Field Effect Transistor)
has emerged with the aid of mature semiconductor technologies, which have been
Fig. 1-4: Schematic diagram of a phase shifter resulting in phase shifts at the device terminal
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Ref=0Ref=0oo Ref=0Ref=0oo Ref=0Ref=0ooPhase=Ref+Phase=Ref+φφooPhase=Ref=0Phase=Ref=0oo Phase=RefPhase=Ref--φφooRef=0Ref=0oo Ref=0Ref=0oo Ref=0Ref=0ooPhase=Ref+Phase=Ref+φφooPhase=Ref=0Phase=Ref=0oo Phase=RefPhase=Ref--φφoo
integrated into a monolithic form [11-12]. This GaAs FET phase shifter exhibits fast
operating speed and monolithic integration capability, in addition to small device size.
However, both types of phase shifters have inherent drawbacks that prevent their
use in a variety of applications. Ferrite phase shifters usually have a low insertion loss,
and can handle significantly higher power, but their high unit cost and complexity are
still problematic. In contrast to the ferrite phase shifter, the semiconductor phase shifter
using p-i-n diodes or FET is quite a bit cheaper and smaller than ferrites. However, these
semiconductor types suffer from drastic loss increase at RF frequency ranges [13].
In the past decade, several other types of phase shifters using RF capacitive
micro-electromechanical (MEMS) switches [14-15] and ferroelectric thin films such as
barium strontium titanate, (BaSr)TiO3, have been proposed to overcome these limitations
[16-17]. The MEMS-based phase shifters have successfully shown low loss, very little
DC power consumption, and higher linearity [18-20], yet relatively slow switching speed,
packaging and reliability problems, mainly attributed to the stiction of mechanical
Fig. 1-5: Concept of beam steering showing beam steering depending on the relative phase relationship between the individual elements of phased array antennas
Phase shifter
Radiator
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structures, remain problematic. In contrast, ferroelectric phase shifters are free of these
reliability issues although they show relatively high loss and high operation voltage.
In this research, both types of phase shifters have been developed, and
characterized to determine which device is more suitable for implementation on a silicon
substrate to realize a phased array antenna system.
1.3 Thesis Organization
The remainder of this thesis is organized into six more chapters. Chapter 2
presents an approach to reduce insertion loss related to the silicon substrate. By
comparing the loss characteristics of various substrates, the possibility for Si MMIC
realization with low insertion loss at RF frequency ranges will be investigated.
Two types of phase shifters are presented in Chapters 3 and 4. MEMS phase
shifters are first discussed in Chapter 3. The MEMS phase shifters adopt polymer
material as MEMS bridge structures to reduce operating voltages.
In Chapter 4, two kinds of designs for ferroelectric phase shifters are compared in
terms of loss and phase shift capability. Discussion to determine the phase shifter type
most suitable for implementation into the phased array antenna system is also presented.
Apart from the phase shifter, MMIC components constructing the array are
studied in Chapter 5. These include microstrip patches, CPW-to-MS transitions,
Wilkinson power dividers and DC blocking filters for CPW and MS.
11
A complete phase array antenna monolithically realized on a silicon substrate is
presented in Chapter 6. The array design shows beam steering capability based on the
results obtained in Chapters 4 and 5.
A summary of the conclusions drawn from the research towards this thesis work
is presented in Chapter 7. Some directions for future research to further improve the
performance of phased array antennas are also discussed in Chapter 7.
Metal
CMOS grade Si
Polyimide
Metal
HRS
SiO2
(a)
(b)
Chapter 2
LOSS CHARACTERISTICS OF SILICON
2.1 Introduction
Due to the high loss at RF frequency ranges, wide application of standard CMOS
grade silicon substrates for MMICs has been limited, as described in Chapter 1.
Suggestions for reduction of insertion loss attributed to silicon, have included the
insertion of a polyimide layer between the standard silicon and circuits (Figure 2-1, a)
[21], or the use of circuits implemented on HRS (ρ>2500Ωcm) with aperture regions
removed by micromachining (Figure 2-1, b) [22]. However, these approaches would not
Fig. 2-1: Configurations to reduce the insertion loss attributed to silicon by (a) inserting a polyimide layer between the CMOS grade silicon and circuits, and (b) micromachining the oxide layer on HRS
13
Metal
HRS
SiO2
Surface charges
only degrade package density of circuits, but would also make integration with active
devices such as high electron mobility transistors (HEMTs) difficult at the same wafer
level. Recently, Gamble et al. presented that the loss of circuits on HRS could be
drastically reduced by introduction of polysilcon stabilizing layer on top of the HRS.
This approach is completely compatible with CMOS technology [23].
In general, to realize metal circuits on a HRS substrate, an oxide layer (SiO2) must
be grown before metal deposition to suppress a DC leakage current. However, the
insertion of the oxide layer between the metal circuits and HRS causes the degradation of
circuit performance, resulting in high RF losses. This is known to be due to an induced
electron density at the silicon surface [24-25]. Thus, the fixed positive charges with a
density of the order of 1011cm-2 in an oxide layer, have electrons induced in the interface
region forming either an inversion layer or an accumulation layer with low resistivity,
depending on the silicon substrate type, as shown in Figure 2-2. However, the
introduction of thin undoped polysilicon layer on top of the HRS could be helpful in
alleviating the population of surface charges at the SiO2/Si interface, as shown in
Fig. 2-2: Surface charges populated in the interface between the SiO2 and HRS
14
Metal
HRS
SiO2
Polysilicon
Figure 2-3. This is due to the abundant localized states within the energy band gap of
polysilicon, typically near 1020 states/cm3 at the band edges, which act as traps to
immobilize the surface charges [26]. Therefore, it is suggested that by inserting a thin
polysilicon layer between the oxide layer and HRS, DC isolation can be accomplished
without the degradation of RF loss characteristics.
To investigate and compare of the loss characteristics due to substrates, 2.5mm-
long CPWs were prepared on three different substrates, HRS (ρ>5000Ωcm), standard
CMOS grade silicon (ρ=1~10Ωcm), and quartz. Both of the silicon substrates were
surface-stabilized by polysilicon. Design rules for the CPWs are presented in Section 2.2,
and preparation of the silicon substrates is described in Section 2.3. Section 2.4 includes
the experimental results of the loss behaviors, and the concluding remarks from this
chapter are summarized in Section 2.5.
Figure 2-3: Schematic of the HRS substrate that is surface-stabilized by undoped polysilicon and oxide buffer layers to reduce RF insertion losses
15
a-a b -b
εr h
a-a b -b
ε2
h1 ε1
h2
(a)
(b)
2.2 Design of coplanar waveguide (CPW)
Prior to determining the effective permittivity and characteristic impedance for
the unshielded CPW on a single-layered, or a double-layered dielectric substrate used in
fabrication (as shown in Figure 2-4), the general case of a double-layered CPW substrate
with upper and lower shielding (as shown in Figure 2-5) will be considered.
It will be then shown that the permittivity and impedance for the unshielded CPW
can be induced by taking the extreme value from the general case. Analysis for deriving
the CPW properties is made possible by employing the conformal mapping method,
which gives closed-form expressions for the propagation characteristics of CPW within
the limits of a quasi-TEM approximation [27].
Fig. 2-4: Unshielded CPW on (a) a single-layered, or (b) a double-layered dielectric substrate
16
h4
h2
h1 h3
S W=2a S
2b=2S+W
ε
ε2=ε0εr2
ε
ε1=ε0εr1
Fig. 2-5: Shielded CPW on a doubled-layered dielectric substrate
Fig. 2-6: Conformal mapping for a shielded CPW on a double-layered substrate
17
For the sake of simplicity, the CPW conductors with semi-infinite ground planes
and dielectric layers are assumed to be lossless. Further, the magnetic walls at which the
magnetic field terminates are considered to be present along the CPW slots [28]. The
total capacitance (Ctot) per unit length of the double layered dielectric substrate CPW can
then be calculated by summing the partial capacitance C1, C2, C3, and C4, which are
conformally mapped onto an ideal parallel plate capacitor as depicted in Figure 2-6. C3
and C4 are designated to the capacitances for the air-filled area in the absence of all the
dielectric layers. Moreover, C1 and C2 are the capacitances due to the dielectric layer
regions Ⅰand Ⅱ, respectively.
From the result of conformal transformation, one can derive the equation for each
partial capacitance [28]. The capacitance of the dielectric layers, C1 and C2 are given by:
and
respectively, where the modulus of the complete elliptic integrals of the first kind K (ki)
and K (k`i) are:
for i=1 and 2.
The ratio of the elliptical integrals can be obtained by an approximate formula [29]:
)()()1(2 '
1
1011 kK
kKC r εε −= 2.1
)()()(2 '
2
20122 kK
kKC rr εεε −= 2.2
+
=
i
ii
hWS
hW
k
4)2(sinh
4sinh
π
π
and 2' 1 ii kk −= 2.3
18
For the capacitance C3 and C4 due to the air-filled region, one can obtain:
and
where
for i=3 and 4.
Therefore, the total capacitance for the double layered dielectric substrate CPW with
shielding is given by:
According to the capacitance definition for effective permittivity (εr,eff) used in the static
analysis of quasi-TEM lines [30], εr,eff is expressed as:
−+
++=
4
4
112ln
21
)'()(
kkkk
kKkK
π, ( )
( ) ∞≤≤≤≤'
112
1kKkKandkfor 2.4
−+
++=
''1''12ln
2)'()(
4
4
kkkkkK
kK π , ( )( ) 1
'0
210 ≤≤≤≤
kKkKandkfor
2.5
)()(
2 '3
303 kK
kKC ε= 2.6
)()(2 '
4
404 kK
kKC ε= 2.7
+
=
i
ii
hWS
hW
k
4)2(
tanh
4tanh
π
π
, and 2' 1 ii kk −= 2.8
++−+−=+++=
)()(
)()(
)()()(
)()()1(2 '
4
4'3
3'21
212'
1
1104321 kK
kKkKkK
kKkK
kKkKCCCCC rrrCPW εεεε
+−
+=
−1
'4
4'3
3'1
11'
4
4'3
30 )(
)()()(
)()()1(
)()(
)()(
2kKkK
kKkK
kKkK
kKkK
kKkK
rεε
+
+−+−
1)()(
)()(
)()()(
1
'4
4'3
3'21
212 kK
kKkKkK
kKkK
rr εε
2.9
19
From Equations 2.9 and 2.10, the effective permittivity can be written as:
where q1 and q2 called the partial filling factors are:
Then, the total capacitance and the characteristic impedance of the CPW can be given by:
with the definitions of the characteristic impedance Z0, and the phase velocity vph [30]:
where c is the velocity of light in free space.
Furthermore, applying some infinite limitations to this general case enables us to
obtain the expressions for other CPW structures. For the double layered CPW without
the shields, setting h3=h4=∞ leads to k3=k4=k0 in Equation 2.8, which can be defined as:
with )()(
)()(
21
0
'0
' kKkK
kKkKqi
ii = for i=1, 2.
air
CPWeffr C
C=,ε 2.10
)()1(1 12211, εεεε −+−+= qqeffr 2.11
1
'4
4'3
3'1
11 )(
)()()(
)()(
−
+=
kKkK
kKkK
kKkKq , and
1
'4
4'3
3'2
22 )(
)()()(
)()(
−
+=
kKkK
kKkK
kKkKq 2.12
+=
)()(
)()(
2 '4
4'3
3,0 kK
kKkKkKC effrCPW εε 2.13
1
'4
4'3
3
,0 )(
)()()(60
−
+=
kKkK
kKkKZ
effrεπ 2.14
phCPW vCZ 1
0 =
effrph
cv,ε
= 2.15
WSW
k+
=20 2.16
20
Then, Equations 2.13 and 2.14 for the total line capacitance and characteristic impedance
reduce to
respectively. The effective permittivity in Equation. 2.11 should be then modified with
the new defined filling factors in Equation 2.16. The analytical expressions for
propagation characteristics derived above could be applied to the CPW fabricated on a
double layer, such as ferroelectric film deposited on any substrates and/or SiO2 layer
oxidized on a silicon substrate. In the case of a single layered CPW (h2=0), the
permittivity can be simplified further as:
setting k2=0, and 0)()(
'2
2 =kKkK
2.3 Fabrication of the CPWs
For the silicon substrates, cleaning was first done by standard SC1 and SC2
process to remove surface contamination. After the initial cleaning process, an
amorphous silicon thin film layer with 1µm thickness was deposited using low pressure
chemical vapor deposition (LPCVD) technique. The deposition temperature and ratio
were 560oC and 24Å/min, respectively. Dry oxidation was then carried out to grow a
thin oxide film of 400Å on the amorphous silicon layer at 950oC. During the dry
)()(
4 '0
0,0 kK
kKC effrCPW εε= 2.17
)()(30
0
'0
,0 kK
kKZeffrεπ
= 2.18
)()(
)()(
211
0
'0
'1
11, kK
kKkKkK
effr−
+=ε
ε 2.19
21
oxidation step, the amorphous silicon layer became poly-crystallized. In contrast, the
quartz substrate was only cleaned and rinsed with acetone and isopropyl alcohol (IPA).
After completing the cleaning process, a thin metal film of Cr/Au (50/300Å) was
evaporated on the HRS, CMOS grade silicon, and quartz substrates. This metal film
would be a seed layer for electroplating carried out during the following process step. To
pattern CPWs on the substrates, standard lithography processes were adopted. First,
Fig. 2-7: Process flow to fabricate CPWs on a silicon substrate
LPCVD amorphous silicon deposition on a silicon substrate
Poly-crystallization of amorphous silicon during the deposition of silicon oxide
Evaporate a seed metal layer (Cr/Au)
Photolithography to form electroplating molds.
Electroplating to increase the metal thickness
Remove the molds and the seed layer
silicon metal poly-Si SiO2
22
Shipley 1827 photoresist was spun on with a 4000 rpm speed, resulting in a thickness of
3µm, followed by a soft-bake process at 100 oC for 1.5min. After UV-exposure of the
photoresist using a Karl Suss MJB3 contact aligner, it was developed in CD26 developer.
The metal pattern defined by the photoresist mold was then electroplated up to a 2µm
thickness to reduce the conductive loss of the device. In the final step, the photoresist
mold and the seed layer were completely removed. The CPWs are designed to have a
220µm width (W+2S) with a 100µm-wide central electrode (W), and 60µm-wide spacing
(S) between the center electrode and the ground lines. The total length of the device is
2.5mm. It is expected that these design values give a characteristic impedance of 50Ω,
and 80Ω for silicon and quartz, respectively, assuming no conduction loss from the
substrate. Figure 2-7 shows the process flow to fabricate the CPWs on a silicon
substrate starting with the deposition of amorphous silicon.
2.4 Loss characteristics
The RF characteristics of the CPWs fabricated on three different substrates were
investigated using a HP8510C vector network analyzer, and a microprobe station. In
order to suppress the parasitic impedance due to the discontinuity in input and output
ports of the devices, cascade microprobes (HPC40-GSG) with a 150µm pitch size were
used. SOLT (short-open-load-thru) calibration was performed prior to S parameter
measurements to set the reference plane to the input and output probe tip ends.
The measured and simulated insertion losses for the CPWs fabricated on HRS,
standard Si, and quartz substrates are shown in Figure 2-8 . It can be seen that the
23
measured results are in good agreement with simulations using IE3D [31]. The measured
insertion loss for HRS surface-stabilized by polysilicon at 15GHZ is 0.16dB,
corresponding to 0.64dB/cm. This value is even lower than the insertion loss of the CPW
fabricated on quartz (0.75 dB), which has only a small conduction loss from the substrate.
Most of the loss from the CPW on quartz could be attributed to the impedance mismatch
due to the high characteristic impedance (80Ω) of the line. It is also interesting to note
that the CPW line on standard Si shows a high insertion loss of 8.3dB at 15GHz, although
the surface is stabilized by polysilicon as well. This would be because of its high bulk
conductivity, ranging from 0.1S/cm to 1S/cm.
Fig. 2-8: Insertion loss characteristics of CPWs fabricated on HRS, standard CMOSgrade Si, and quartz
24
It is well known that there exist different fundamental modes when
electromagnetic waves propagate in transmission lines, depending on the loss tangent
values of the substrate (tanδc), which is defined as [32]:
where, ω is the angular frequency, and σs and εs are the conductivity and permittivity of
the substrate, respectively. When signal frequency is low compared with the dielectric
relaxation frequency, fdr, given by
This propagation mode is identified as “slow-wave mode” and causes large losses. In
contrast, “quasi-TEM mode” produces fewer losses and occurs when the operating
frequency exceeds the relaxation frequency [33-34]. The calculated relaxation frequency
for CMOS grade silicon with conductivity values of 0.1S/cm to 1S/cm ranges from
15GHz to 150GHz, whereas HRS, with a conductivity of 0.0002S/cm, shows only
30MHz. Thus, it can be concluded that the excessively large losses of the CMOS grade
silicon are due to its high relaxation frequency, which is in the vicinity of, or beyond the
ranges of operating frequencies propagating the waves in the “slow-wave mode.”
Hence, it can be concluded that use of HRS as substrate material is a good
approach to realize low loss MMICs, as it shows a very low dielectric relaxation
frequency compared with the operating frequencies resulting in the “quasi-TEM
propagation mode.” In addition, by passivating the surface of HRS by polysilicon, the
surface charges populated in the interface between the HRS and the SiO2 layer can be
s
sc ωε
σδ =tan 2.20
s
sdrf πε
σ2
= 2.21
25
trapped in order not to increase the effective relaxation frequency due to the mobile
charges.
2.5 Summary
To investigate and compare the loss characteristics due to substrates, 2.5mm-long
CPW lines were fabricated on three different substrates (HRS, CMOS grade silicon and
Quartz). Succeeding depositions of a polysilicon stabilizing layer, and a silicon oxide
layer were carried out on both of the silicon substrates. It is shown that the loss
characteristics for a 50Ω CPW patterned on the surface-stabilized HRS is only 0.16 dB at
15GHz, while the insertion loss for CPW lines on CMOS grade Silicon and quartz are 8.3
dB and 0.75 dB, respectively, at 15 GHz. The low insertion loss from the HRS substrate
was proven to be attributed to the existence of the polysilicon stabilizing layer, which can
immobilized the surface charges populated at the interface of SiO2 and Si, reducing RF
losses. This poly-Si/SiO2/HRS configuration will be applied to all substrates where
MMIC components to construct a phased array antenna are built.
Chapter 3
MEMS PHASE SHIFTER
3.1 Introduction
Recently, microelectromechanical system (MEMS) technology has been
extensively adopted for use in radio frequency (RF) devices. Of the various RF MEMS
applications, the RF switch using MEMS bridges have shown some advantages over
other conventional semiconductor switching devices, namely low loss, very little DC
power consumption, and high linearity [35-37, 20]. Moreover, a distributed phase shifter
employing MEMS switches has shown reduced insertion loss, heat dissipation, cost,
weight and volume [38]. These desirable characteristics have led to the potential use of
MEMS phase shifters in combination with conventional semiconductor devices for
applications in satellite and wireless communication systems.
In spite of these advantages, when compared to semiconductor devices, the
MEMS switch and phase shifter has some features that require improvement, such as low
switching speed, high actuation voltage and unresolved packaging issues. Lowering the
actuation voltage is one of the primary issues for enhanced lifetime of the devices.
Chapter 3 presents an idea of how to reduce actuation voltage using polymer bridges, as
well as a description of the design, fabrication, and characterization of the distributed
phase shifter using MEMS bridges.
27
g td
G W G
go
3.2 MEMS bridge switches
The capacitive shunt switch constructing the MEMS phase shifter typically
consists of a thin metal bridge suspended over the center electrode of a CPW, as shown in
Figure 3-1, which moves with a biased DC voltage. When a dielectric film such as
silicon nitride (SixNy) is deposited on a center electrode to prevent a DC short and stiction,
the bridge capacitance, Cb comprises the air capacitance, Cba, and the dielectric
capacitance, Cbd, in series. Therefore, the total capacitance of the bridge can be written
as:
where εo and εr are the dielectric permittivity of free space and the relative
permittivity of the dielectric film, respectively. g is the gap height between the bridge
and the bottom electrode, td the thickness of dielectric film, and A denotes the overlapped
area between the bridge and dielectric layer.
Fig. 3-1: Cross section view of a shunt MEMS switch
+
=+
=
rεdtg
Aoε
bdCbaCbdCbaC
bC 3.1
28
From this expression for the bridge capacitance, the electrostatic force on the
bridge can be induced by taking the derivative of Cb with respect to the bridge height [38].
Thus,
where Vt is the voltage applied between the bridges and the electrode
Equating the applied electrostatic force with the mechanical restoring force due to
the stiffness of the bridge (F=kx), one finds:
where go is the zero-bias bridge height, and k is the effective spring constant of fixed-
fixed beams, which can be approximated by [39]:
where E is Young’s modulus of the bridge material, t the bridge thickness, L the bridge
length, w the bridge width, σ the residual tensile stress in the bridge, and ν Poisson’s ratio
for the bridge material.
Solving Equation 3.3 for the voltage results in:
2
rεdtg
Aoε
2
2tV
dgbdC2
tV21
eF
+
== 3.2
)( ggk2
rεdtg
Aoε
2
2tV
eF o −=
+
= 3.3
Lν)tw(1 8
3L
w332Etk −+=
σ 3.4
2
Cooo
3o
t Rgg
gg1
Aε2kg
V
+
−= 3.5
29
where, RC=Cbo/Cbd, Cbo is the air capacitance at the initial position. When the voltage is
increased, the electrostatic force is increased due to an increase in the charge on the
bridge and bottom electrode. At a certain point, the increase in the force is greater than
the increase in the restoring force, resulting in the beam position becoming unstable and
collapse of the beam to the down-state position as shown in Figure 3-2.
To calculate the position of the instability, one can take the derivative of Equation
3.5 with respect to g and set it to zero, resulting in:
It is seen that for RC=0 ( no dielectric films on the electrode) the instability occurs at one
third of the gap height (2go/3). The voltage at the point of the instability called pull down
voltage can then be found by substituting Equation 3.6 into 3.5:
Fig. 3-2: Schematic of cross section of the bridge switch at the up and down state
)2(3 Co
p Rg
g −= 3.6
( )3C1Ao27ε
3o8kg
Vp R+= 3.7
Switch up state Switch down state
Dielectric layer
30
Figure 3-3 shows the change in bridge height versus applied voltage as RC is
varied from 0 to 2, assuming E=70GPa (for aluminum), σ=0, go=2.8µm, w=60µm,
L=300µm, t=2µm, and A=6000µm2. It is interesting to note that the instability can be
completely removed by setting RC=2. Since the MEMS bridge phase shifters should be
operating within the stable region so as not to cause an RF short, this removal of the
instability would help to improve the capacitance ratio between the up-state and down-
state, resulting in higher phase shift. However, the increase in the stable region also
requires the increase of pull down voltage. For example, the pull-down voltage is
increased by a factor of 5.2 with RC=2, as shown in Figure 3-3. Thus, there should be a
compromise in determining the RC.
Fig. 3-3: Plot of change in bridge height versus applied voltage versus applied voltage asRC is varied from 0 to 2
31
(a) (b)
One of the bottlenecks in the integration of MEMS phase shifters with
conventional semiconductor circuitry is their large operational voltage. It is well known
that high actuation voltages decrease the lifetime of switches, causing the dielectric to
acquire and hold charges, and making bridge switches unable to release [40]. The pull
down voltage of a MEMS bridge is dependent upon its material properties as well as
geometry.
The easiest method to decrease pull-down voltage is to reduce the bridge gap.
However, in addition to fabrication difficulties, this may cause an increase in the return
loss, resulting in degradation of device performance. Another method is to lower the
spring constant, which can be done by either changing the geometry of bridges or
employing materials of low Young’s modulus. Meander or hinge structures have been
proposed for the reduction in operating voltages, as shown in Figure 3-4 [41-42], but
these increase design as well as fabrication complexity. Thus, materials such as polymers,
whose Young’s modulus is typically around 5GPa, much less than that of metal
Fig. 3-4: Photographs of shunt switches using (a) meander or (b) hinge structures to lower the spring constant [41-42]
32
(50~100GPa), should be explored for fabricating these bridges [43-44]. Figure 3-5 is a
material selection chart with the Young’s modulus plotted against the electrical resistivity,
including polymers [45]. It is seen that conductive polymers would be very attractive to
realize RF MEMS applications such as switches that require low actuation voltages and
low resistivity.
Figure 3-6 depicts the calculated actuation voltages of both aluminum (Al) and
polymer bridges with different thicknesses, as a function of bridge height, assuming the
same design parameters used for Figure 3-3. It can be easily seen that the polymer
bridges have much lower actuation voltages compared to the Al bridges, especially with
gap heights and bridge thicknesses larger than 3µm and 4µm, respectively.
Fig. 3-5: Plot of Young’s modulus against electrical resistivity for various materials [45]
33
However, the polymer bridge should be metal-coated in order to work as an
electrostatic actuator because UV curable conductive polymers required to define the
bridge patterns by photolithography are not yet commercially available. The equivalent
Young’s modulus (Ee) for such fixed-fixed bridges composed of multi-layers can be
calculated from the weighted volumetric average of the different layers.
where En and tn is the Young’s modulus and the thickness of each layer, respectively.
Fig. 3-6: Calculated actuation voltages for metal and polymer bridges
∑∑=
n
nn
ttE
eE 3.8
34
MEMS bridgeDielectric film Probe pad
s
3.3 Distributed MEMS transmission line (DMTL)
Distributed MEMS phase shifters are usually fabricated on a coplanar waveguide
(CPW) transmission line owing to the ease of fabrication and low loss. In order to
fabricate the distributed MEMS phase shifter, a high impedance (Zo) CPW transmission
line periodically loaded with MEMS bridge switches with spacing s is required, as shown
in Figure 3-7. The high impedance is indispensable for the unloaded line so that the
loaded line including the MEMS bridges can be matched with 50Ω. The per unit-length
capacitance Ct, and inductance Lt of the unloaded CPW transmission line are given by
[46]:
where εr,eff is the effective dielectric constant of the unloaded CPW transmission line, and
c is the free-space velocity.
Fig. 3-7: Schematic of a DMTL phase shifter with MEMS bridges
o
effrt cZ
C ,ε=
3.9
2Ott ZCL = 3.10
35
sLt
sCt
Cba
Cbd
s
sLt
sCt
Cba
Cbd
The CPW line periodically loaded with MEMS capacitors can be modeled as a
lumped inductance (Lt) and capacitance (Ct) with a parallel variable capacitor (Cba) and
fixed capacitor (Cbd), as shown in Figure 3-8. The phase velocity vl, and the
characteristic impedance Zl of the loaded CPW transmission line are then given by [47]:
where the total capacitance of the bridge, Cb, and the Bragg frequency, ωB, are
respectively defined as:
Fig. 3-8: Lumped-element transmission line model with variable and fixed capacitorswith periodic spacing, s
⋅⋅⋅+++
=
2
2
61)(
Bbtt
l
CsCsL
sv
ωω
3.11
221)(
41
−
+=+−
+=
Bbt
tbtt
bt
tl CsC
sLCsCsL
CsCsL
Zωωω 3.12
bdba
bdbab CC
CCC
+= 3.13
)(2
bttB
CsCsL +=ω 3.14
36
At the Bragg frequency, the guided wavelength approaches the periodic spacing of the
discrete components, which bring the characteristic impedance of the line zero, indicating
no power transfer.
The phase shift resulting from the change of the DMTL characteristic impedance
arising from the MEMS bridges capacitance variation by applying a bias voltage can be
given as:
where Zlu and Zld are the DMTL characteristic impedance for the low and the high bridge
capacitance state, respectively, and l is the total length of the transmission line.
From the above expression, it is apparent that the impedance and propagation
velocity through the transmission line can be varied according to the dimension of the
MEMS bridges and their periodic spacing. By applying a bias voltage between the
MEMS bridges and the bottom electrodes, the height of the MEMS bridges can be
changed. This variation changes the distributed MEMS capacitance, resulting in a
change in the loaded transmission line impedance and phase velocity, which in turn
causes phase shifting.
Several critical parameters, such as the physical dimensions of the device, should
be considered in designing the MEMS bridges as well as the DMTLs, as these are
essential to acquire good performance for phase shifting. These parameters should be
determined keeping in mind not only the circuit performance, but also the process
tolerance for fabrication.
lZZc
Zl
vv ldlu
effro
du)11(11 ,
−=
−=∆
εωωφ 3.15
37
3.4 Previous MEMS phase shifter research
Since incorporation of MEMS switches into distributed CPW transmission line
designs, as demonstrated by Barker and Rebeiz [46], a variety of distributed MEMS
phase shifters have been developed for wide-band applications. Borgioli et al. developed
one-bit K/Ka- band phase shifters with RF MEMS capacitive switches, giving a 270o
phase shift and 1.69dB loss at 35GH [48]. In addition to these single-bit phase shifters,
multi-bit MEMS phase shifters have also been reported by several groups. A three-bit K-
band distributed phase shifter, as shown in Figure 3-9, demonstrated a 1.7dB loss at
26GHz resulting in a phase shift from 0o to 315o with a 45o phase step [49].
Hyden et al. presented a two-bit distributed CPW phase shifter for X-band
developed using a series of combinations of MEMS bridges and MIM capacitors, as
shown in Figure 3-10. This two-bit phase shifter was designed to have a 90o, 8 MEMS
bridge section cascaded with a 180o, 16 MEMS bridge section with an expected phase
shift of 0/90/180/270o (Figure 3-11) [50]. This configuration enables selection of either
the MEMS bridge capacitance (Cb) or the total lumped capacitance (Cs) by applying
voltages on the line composed of MIM capacitors and MEMS bridges.
Fig. 3-9: Three-bit distributed MEMS phase shifter [49]
38
Furthermore, Pillions et al. demonstrated three and four bit phase shifters for Ka-
band built on silicon [51]. These phase shifters showed a 0o to 315o phase shift with a
step of 45o for the three-bit phase shifter (Figure 3-12, a) and a 0o to 337.5o phase shift
with a step of 22.5o for the four-bit phase shifter (Figure 3-12, b).
Fig. 3-10: (a) Schematic of a phase shifter with MEMS bridges and MIM capacitors, and(b) a cross sectional view of the phase shifter [50]
Fig. 3-11: Phase shifts of the 2 bit phase shifter showing 0/87/183/270o at 20GHz [50]
(a) (b)
39
(a) (b)
The MEMS phase shifter presented in this research has been developed to
improve performance, placing special emphasis upon reduction of the operating voltage.
This work was accomplished by replacing the bridge materials with polymer, a technique
not previously attempted. Fabrication and performance for this device will be presented
in the following sections.
3.5 Fabrication
The phase shifters employing polymer MEMS bridges were fabricated by
conventional surface micromachining methods. Fabrication begins with the preparation
of silicon wafers that are surface-stabilized by polysilicon and silicon oxide, as described
in Chapter 2.
Fig. 3-12: Photographs of (a) the three-bit MEMS phase shifter. (b) the four-bit MEMS phase shifter fabricated by Pillans et al. [51]
40
mask1
(a) Patten the CPW and electroplating to increase the thickness
mask2
(b) Deposit and pattern the silicon nitride film
(c) Photoresist sacrificial layer
mask3
(d) 3rd photolithography for bridge posts
(e) Seed metal deposition for MEMSbridges
mask4
(f) Spin-coat SU8 and cure it to make the polymer bridges
(h) Removal of the sacrificial layer
metalmask PR substrate SU8 Silicon nitride
(f) Spin-coat and cure SU8 to make the polymer bridges
3.5.1 Process flow
Fig. 3-13: Process flow for the MEMS phase shifter with polymer bridges
41
Figure 3-13 depicts the process flow for fabricating the MEMS phase shifter
consisting of polymer MEMS bridges and CPW line. The CPW transmission line was
defined by evaporating chromium and gold metals (Figure 3-13, a), followed by an
electroplating step to increase the electrode thickness beyond the skin depth (~2µm), as
presented in Chapter 2. A 3000Å thick silicon nitride film was then deposited on the
center electrode using plasma enhanced chemical vapor deposition (PECVD) technique
(Figure 3-13, b), which acts as insulator to prevent a DC short between the top and
bottom electrode. Photoresist (Shipley 1827) was then spun on as sacrificial layer and
patterned (Figure 3-13, c, d), which determines the height of the MEMS bridge. It is
advantageous to use photoresist as the sacrificial layer because it can be reflowed during
the post baking process for 20~30minutes at 90~110oC to smooth the edges of the
patterned photoresist, especially at the edges of the center conductor. Again, a thin metal
layer of around 1000Å thickness was deposited using an evaporator or sputtering system
on the sacrificial layer (Figure 3-13, e), which is used as metal electrodes for the polymer
bridges.
A negative photoresist of SU8 was then spin-coated at a speed of 1000rpm for
20sec on the thin metal layer to form the structural layer of the bridges. The obtained
thickness was around 4µm. SU8 is chosen as the structural polymer since it shows a
strong adhesion to metal, as well as resistance to acetone used for etchant to remove the
photoresist sacrificial layer. After the UV exposure, the SU8 layer was post-baked to
induce cross-linking for polymerization, an imperative step for negative photoresists
(Figure 3-13, f). The thin metal layer was etched away to define the bridges except
42
where the cured polymer bridges lay. The sacrificial layer was then removed in acetone
and rinsed with IPA several times until no residue could be found on the substrate. After
being rinsed, the device was put into a supercritical drying chamber to release the metal-
coated polymer bridges (Figure 3-13, g). It is worthy to note that the releasing process in
MEMS fabrication is quite important because it chiefly determines the entire fabrication
yield. The releasing method will be presented in the following section in detail.
3.5.2 Supercritical point dry
The biggest issue in the fabrication process of the MEMS bridge relates to the
stiction problem at the final step. After etching off the sacrificial layer, the etchant is
normally rinsed with DI water or IPA, and then dried through evaporation to release the
MEMS structures from neighboring surfaces, typically bottom substrates. However, this
drying technique has the inherent drawback of causing capillary forces during drying and
causes the structures to remain stuck to the substrate. Once the MEMS structures adhere
to the substrate, it is very difficult to restore the deformed structure, even after being
completely dried. Accordingly, efforts should be exerted to reduce the capillary forces
and to find a better fabrication yield.
Of the various methods used to eliminate the undesirable forces, one well-known
technique using the critical phenomenon of Carbon Dioxide (CO2) would be most
effective; this is called CO2 critical point drying (CPD). After replacing the final rinse
with liquid CO2 (LCO), the LCO can be dried without crossing a phase boundary or
43
Supercritical Drying
Evaporation
Critical point
Pressur
Temperature
Solid Liquid Vapor
causing any abrupt change in state by increasing the pressure and temperature of the
specimens, as shown in Figure 3-14.
This is possible because when the critical point is reached, the density of the
liquid and the density of the gas are identical. The CO2 CPD can be applied for most
specimens, including biological ones, since it has a quite low critical point (31oC and
1072psi) while water has a critical point of 347oC and 3212psi, which would cause heat
damage to the specimen. Figure 3-15 is a photograph of the CO2 critical point dryer
being used to release the MEMS bridges herein.
Fig. 3-14: Phase diagram for drying procedures
44
Dryer chamber
Sample immersed in IPA
3.6 Results and Analysis
The MEMS phase shifter fabricated on silicon substrates consists of a high
impedance CPW line of 73Ω, loaded periodically with eleven polymer MEMS capacitors
at a spacing of 640µm, as shown Figure 3-16. The critical dimensions of the device are
summarized in Table 3.1. This configuration theoretically gives a minimum distributed
capacitance of 37 fF/mm at 0V and a maximum capacitance of 55.5fF/mm at the pull-
down voltage when fringe capacitances neglected, resulting in a Bragg frequency of
around 54GHz.
Fig. 3-15: Photograph of the CO2 critical point dryer
45
WS
S
s
w
Figure 3-17 shows the empirical phase shifts as a function of frequency for
different bias values. The device shows a continuous phase shift of up to approximately
90o, with a maximum operating voltage of 40V over the frequency ranges from 1 to 15
GHz. From Figure 3-6, it can be seen that the pull-down voltage for a polymer bridge
with a 2.8µm gap height and a 4µm thickness would be around 50V, slightly higher than
Fig. 3-16: Photograph of the MEMS phase shifter consisting of a high impedance CPW, loaded periodically with eleven polymer MEMS capacitors
Table 3.1: Critical dimensions of the polymer MEMS phase shifter fabricated herein
Center electrode width, W 125µm CPW
Gap between the center electrode and the grounds, S 50µm
Width, w 60µm
Thickness, t 4µm
Gap height, g 2.8µm Polymer bridges
Spacing between the bridges, s 640µm
46
the measured (40V). This disagreement in the pull-down voltage would prove that an
already existing bridge bending problem makes the gap height narrower, resulting in
decreased pull down voltage. The buckling generally results from the presence of a stress
gradient in the normal direction of the bridge, which is unavoidable in the structure of
multiple layers.
Because of the conductivity of silicon, there should be DC current leakage when
the devices are DC-biased. The level of DC leakage current measured is as shown in
Figure 3-18. Up to the pull down voltage of 40V, it shows leakage current levels of less
that 1µA, which would be acceptable for the device operation. Reduction in the polymer
bridge thickness can decrease the pull down voltage and leakage current further, but this
may exacerbate the bridge buckling. Thus, there must be a compromise.
Fig. 3-17: Measured phase shifts of the MEMS phase shifters, depending on differentactuation voltages
47
Fig. 3-18: Plot of leakage currents versus DC bias voltage for the MEMS phase shifter
-20-18-16-14-12-10-8-6-4-20
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Frequency (GHz)
Inse
rtio
n lo
ss (d
B)
measuredsimulated
Fig. 3-19: Comparison of insertion loss between the simulated and the measured results
48
Figure 3-19 compares simulated and measured insertion loss (S21) for the
MEMS bridge-loaded phase shifter. It is noted that the measured insertion loss indicates
around 5dB at 15GHz, while the simulated results stay less than 1dB from 1 to 15GHz..
This difference is also attributed to the nonuniformity in bridge heights due to bridge
bucking, which may cause excessive power reflections between the periodic unit cells.
Therefore, it can be concluded that overcoming the bridge bending problem is a
key issue to further reduction of pull down voltage as well as RF losses. Bending can be
reduced by using a single polymer layer as the bridge material. Thus, further research on
the development of UV curable conductive polymers will be required.
It should be mentioned that even though the MEMS bridges are released
successfully at the final step in fabrication using the CPD, they are easily stuck to the
bottom plate when exposed to the environment because of sensitivity to vibration,
humidity, and/or particles in air. Therefore, they must be packaged in hermetic or near-
hermetic seals in nitrogen environments for use in phased array antennas with reasonable
reliability.
3.7 Summary
RF phase shifters using polymer MEMS bridges developed here showed a phase
shift of 90o at 15GHz with a pull down voltage of 40V. The DC leakage currents were
less than 1µA with biased voltages of up to the pull down voltage, which would be
acceptable for device operation. The lower pull down voltage than expected identifies
existing bridge bending problems attributed to the internal stress due to the bilayer
49
structure of the bridge, resulting in excessive RF losses and difficulty in further reduction
of the pull down voltage. This buckling issue will, however, be lessened by using a
single conductive polymer layer as the bridge material. In addition, hermetic packaging
would be required for the MEMS devices to prevent the stiction problem, improving the
reliability in device operation.
Chapter 4
FERROELECTRIC PHASE SHIFTER
4.1 Introduction
Ferroelectrics such as BaTiO3, (Ba,Sr)TiO3, and (Ba,Pb)TiO3 are a class of
dielectric materials that possess high permittivity and a polar axis which can be realigned
by application of an external field. These characteristics of high permittivity and polarity
enable the ferroelectric materials to be extensively used in a variety of electronic
applications such as dielectric capacitors for dynamic random access memories (DRAMs),
resonators [52], filters [53], and phase shifters [54-55].
Fig. 4-1: Schematics of (Ba,Sr)TiO3 perovskite unit cell (a) before, and (b) after polarization under external electric fields
Ba2+, Sr2+ O2- Ti4+
(a) (b)
51
Of the various ferroelectric materials, barium strontium titanate, (Ba,Sr)TiO3, is
currently a leading candidate for use in microwave and millimeter wave applications
because of its high dielectric tunability, high breakdown field, and relatively low
dielectric loss. (Ba,Sr)TiO3 is a mixed cation perovskite where both Ba and Sr occupy
the metallic cation site with a positive charge, as shown Figure 4-1. The unit cell of
(Ba,Sr)TiO3 is either tetragonal or cubic, depending on whether the material is in the
ferroelectric region (below the Curie temperature, TC) or paraelectric region (above TC),
respectively. The Ti+4 ion surrounded by six nearest neighbor oxygen ions will be off
center under external electric fields giving rise to an electric dipole (see Figure 4-1, b).
In the ferroelectric region, the material retains some remnant polarization, when
the applied field is removed. This hysteresis effect is not highly desirable for phase
shifting devices because it couples with the tunability of the dielectric constant reliability
for repeatable uses. Fortunately, tunability is also present in the paraelectric region in
which the nearly linear variation in dielectric constant with applied bias fields occurs.
For this reason, BST thin films are suitable for phase shifting devices because their Curie
value is in the vicinity of room temperature, resulting in a significant variation of the
dielectric constant with applied electric fields at microwave frequencies. In this chapter,
the phase shifter utilizing the tunability of BST films is presented. This includes the
characterization of the BST film itself, the fabrication and the planar design of the phase
shifter.
52
4.2 Previous works for BST thin film phase shifters
A couple of designs for phase shifter with BST films were recently reported [51-
52]. Figure 4-2 is a photograph of the coupled microstrip phase shifter using BST thin
films as interdigital capacitors developed by Van Keuls et al. [56]. The phase delay of
transmitted waves in the microstrip line occurs by biasing DC voltages between the
coupled lines, producing a change in the capacitance of the coupled lines.
Erker et al. recently proposed a monolithic Ka-band phase shifter that employs
the parallel plate capacitors of BST film as varactors periodically loaded on a distributed
CPW transmission line as shown in Figure 4-3 [57]. It is generally known that the
parallel plate structures have an advantage in tunability at low voltages over the
interdigital geometry because electric fields are better confined in the film. In this case,
the phase delay of the transmission can be controlled by applying voltage to the loaded
BST capacitors. They reported a phase shift of 0o~157o at 30GHz with an insertion loss
Fig. 4-2: Four-element phase shifter using interdigital capacitors [56]
53
of 5.8dB and a bias voltage of 20V. This parallel structure, however, is vulnerable to
hillock formation, and/or metal diffusion into the BST film because high temperature
(≥500oC) BST growing process follows the metal deposition step. In this research,
interdigital planar structures have been tried for the phase shifter, where the metal circuit
is defined after the BST deposition resulting in fewer defects from the high temperature
process.
4.3 Synthesis and properties of BST films sputter-deposited on silicon
BST films were RF-sputtered from a stoichiometric (Ba,Sr)TiO3 3-inch target
onto high resistivity silicon substrates under the conditions listed in Table 4.1. Prior to
the direct deposition of BST, a surface-stabilizing layer of polysilicon as well as a buffer
layer of SiO2 were first grown on the silicon wafer to decrease RF losses and DC leakage
currents, as described in Chapter 2 (see Figure 4-4).
Fig. 4-3: Phase shifters employing BST film varactors periodically loaded on a CPW line [57]
54
Ground
HRS
Poly-Si
Tunable (Ba,Sr)TiO3
SiO2 buffer layer
Ground Signal
Figure 4-5 is a photograph of the RF reactive sputtering system used for BST
deposition, comprised mainly of a process chamber, a load lock chamber, and a load arm.
Substrates are first loaded in the load lock chamber, and then introduced into the process
Table 4.1: Sputtering conditions for BST deposition
Target Ba0.5Sr0.5TiO3
Target diameter 3 inch
Source to substrate distance 6 inch
RF power 120W
Sputtering gas Ar/O2=10/1
Substrate temperature 750oC
Gas pressure 20mTorr
Deposition rate ~4Å/min
Fig. 4-4: Configuration of the substrate on which the phase shifter circuit is defined. BST films are deposited on HRS that is surface-stabilized by poly-silicon and oxide buffer layers in advance.
55
Load lock chamber
Process chamber
Load arm
chamber using the load arm, a very effective way to protect the process chamber from
contamination.
The base pressure of the process chamber can rise to 3.0×10-7torr by turbo
molecular pumps. In this work, the constant deposition pressure of 20mTorr was
maintained by a mixture of oxygen and argon with a ratio of 1 to 10. The oxygen gas
was supplied through a gas ring surrounding a sample holder for reactive sputtering (see
Figure 4-6).
During deposition, the substrates mounted on a substrate holder were held at
750oC using a quartz lamp heater rotating at 10rpm to achieve uniform BST films. In
addition, to avoid cracks on the target, ramping speed of heater and RF power were
carefully adjusted as low as possible. At an RF power of 120W, the BST film was
deposited for about 14hours with a deposition rate of 4Å/min.
Fig. 4-5: Photograph of the RF reactive sputtering system used for BST deposition
56
Fig. 4-6: Schematic of the process chamber of the RF reactive sputtering system
O2 gas ring
Substrate rotator
Quartz heater
Ion gauge
Turbo pump
Target
O2 Ar
Substrate holder
57
(a)
(b)
BST
Poly- Si SiO2
Grown BST films were characterized by x-ray diffraction (XRD), and scanning
electron microscope (SEM). Figure 4-7 (a) shows the XRD result for the BST film
grown on HRS, indicating the film is well-crystallized. The main peaks observed are
Fig. 4-7: (a) X-ray diffraction pattern, and (b) cross-sectional SEM image of BST film deposited on SiO2/poly-Si/Si substrate
58
ascribed to the peaks of (100), (110), (111), and (200), respectively. The cross section
view of BST film grown on a SiO2/poly-Si/Si substrate can be seen in the SEM image as
shown in Figure 4-7 (b).
The phase shifting devices were completed by defining metal patterns on this BST
film using conventional photolithography and electroplating methods. The analytic
formulations to design the BST phase shifters are presented in the following sections.
4.4 Analytic formulations for the BST film based phase shifters
The BST phase shifters developed herein have adopted a bilateral coplanar
waveguide structure for ease of monolithic integration with control circuits as well as
fabrication, as described in Section 4-2. Since the bilateral CPW phase shifter consists of
periodic capacitive loads on a CPW identical to the MEMS phase shifter presented in
Chapter 3, it can be analyzed employing the periodic shunt circuit model [58].
For the purpose of comparison, two kinds of the bilateral CPW structures,
interdigital (BI) and coplanar stripline (BCS) structures, were prepared. The schematic
diagrams of both structures are shown in Figure 4-8. It is seen that the periodic
capacitive loads in a unit cell consist of either interdigital fingers (BI-CPW) or coupled
coplanar striplines (BCS-CPW). Formalism to design both the structures will be
introduced using conformal mapping in the following sections. In addition, comparison
to real device performances will be presented to assist in determining which structure
would be more suitable for integration into the antenna array.
59
d Unit cell Unit cell
d
(a) (b)
4.4.1 Bilateral interdigital CPW (BI-CPW) phase shifter
The analytic model for BI-CPW phase shifters fabricated on a two-layered
dielectric substrate was proposed by H. Yoon, where it is assumed that the total
capacitance in a unit cell consists of two different sections, Ccps and Cend, as shown in
Figure 4-9 [59].
First, conformal mapping is used to find the capacitance of the periodic
symmetric section, Ccps, on a two-layered dielectric substrate corresponding to a coplanar
strip (CPS) structure. That is [60]:
Fig. 4-8: Schematic diagrams of (a) the bilateral interdigital, and (b) the bilateralcoplanar stripline CPW structures to construct BST phase shifters
60
Cend
Ccps
Cend
Ccps Ccps Ccps
Cend
l
2g 2s
εr1
εr2
h1
h2
2s 2g
W
gend
where K(ki) is the complete elliptic integral of the first kind, ki the modulus of the elliptic
integral, qi the filling factors, l the length of a coplanar strip section, 2s the width of a
finger, and 2g the gap between two fingers.
lkKkK
Cc
cecocps )'(
)(
0
0εε= 4.1
2
0 1
+
−=sg
gk c , 20
'0 1 cc kk −= 4.2
( )[ ]i
iic hgs
hgk2/)(sinh
2/sinh1 2
2
+−=
ππ , 2' 1 icic kk −= , i=1, 2 4.3
)()'(
)'()(
21
0
0
c
c
ic
icic kK
kKkKkK
q = 4.4
)()1(1 12211 rrcrcec qq εεεε −+−+= 4.5
Fig. 4-9: Schematic view of the unit cell for the BI-CPW phase shifter fabricated on a two-dielectric substrate. The total capacitance in a unit cell consists of two sections, Ccpsand Cend [59].
61
The approximate formula for the capacitance of the finger end section could be
induced by adopting the CPW open-end extension model [59-61] because the geometry
of the finger end section is very similar to the CPW open circuit. The open circuit
capacitance Cend is expressed by the length extension of the CPW as a function of the
finger-to-finger spacing (2g), the finger width (2s), and the gap of the finger end (gend).
That is:
Therefore, the total capacitance of the bilateral interdigital capacitors can be calculated
by taking the sum of Ccps and Cend considering the number of fingers n.
exte
eeeoend l
kKkK
C)'()(
40
0εε= 4.6
+
+
×+
×+
×−
×= −−−
−
366
26
6 1108109104105.12 Ag
AAs
AsAl
endext 4.7
22gsA +
= 4.8
sgsk e +
=20 , 2
0'0 1 ee kk −= 4.9
+
=
i
iie
hsg
hs
k
2)2(sinh
2sinh
π
π
, 2' 1 ieie kk −= , for i=1, 2 4.10
)()'(
)'()(
21
0
0
e
e
ie
ieie kK
kKkKkK
q = 4.11
)()1(1 12211 rrereee qq εεεε −+−+= 4.12
endcpstot nCCnC +−= )1( 4.13
62
d
2s
2g
Ccpw
Coms
lo S
WS
4.4.2 Bilateral coplanar stripline CPW (BCS-CPW) phase shifter
For the BCS-CPW structure, it would be reasonable to consider that the
capacitance is a parallel combination of the partial capacitance due to the CPW itself,
Ccpw, and the overlapped microstrip line region, Coms (see Figure 4-10). Because the
stripline width is very small compared to the line length, the capacitance due to the
stripline end section is negligible.
The partial capacitance due to the overlapped microstrip line region, Coms in a unit
cell can also be obtained by using Equation 4.1 through 4.6 replacing l with lo, where lo is
the length of the overlapped microstrip region. That is:
In addition, the partial capacitance attributed to the CPW line, Ccpw, in a unit cell could be
induced by taking the half value of Equation 4.6, and replacing lext with the unit cell
length d, which is expressed by:
Fig. 4-10: Schematic view of the unit cell for the BCS-CPW structure. The total capacitance in a unit cell consists of two sections, Coms and Ccpw
oo
oeoooms l
kKkK
C)'()(
0
0εε= 4.14
63
(a)
(b)
Thus, with m unit cells, the total capacitance of the bilateral coplanar stripline
CPW structure can be expressed as the linear sum of the Coms, and the Ccpw:
4.5 Design parameters of BI- and BCS-CPW phase shifters
Fabrication of BST phase shifters employing BI- and BCS-CPW structures has
been completed by defining the metal patterns on BST-grown silicon substrates using
conventional photolithography and electroplating techniques. The BST thin film was
dkKkK
Cc
cecocpw )'(
)(2
0
0εε= 4.15
)( cpwomstot CCmC += 4.16
Fig. 4-11: (a) Schematic diagram, and (b) photograph of the BI-CPW phase shifter fabricated on BST film
64
(a)
(b)
grown on SiO2/Poly-Si/HRS substrates, as presented in Section 4-3. Both bilateral CPW
lines loaded with periodic capacitors are connected to simple 50Ω CPW pads for on-
wafer measurements of device performance, as shown in Figure 4-11 and Figure 4-12.
The critical dimensions for both bilateral BST phase shifters fabricated herein are
listed in Table 4.2, referring to Figure 4-9 and Figure 4-10.
Fig. 4-12: (a) Schematic diagram and (b) photograph of the BCS-CPW phase shifter fabricated on BST film
65
4.6 Performances of the BST phase shifters
Prior to phase shift measurements, S parameters for both BI- and BCS-CPW
phase shifters were characterized using a network analyzer as shown in Figure 4-13. It
can be easily noted that the BCS phase shifter shows much better RF performance than
the BI type. Thus, from 5 to 25GHz, an insertion (S21) and a return loss (S11) of better
Table 4.2: Design parameters of the BI- and BCS-CPW phase shifters using BST films
BI-CPW BCS-CPW
Thickness 400µm HRS
Dielectric constant 11.7
Thickness 1µm Polysilicon
Dielectric constant 11.7
SiO2 Neglected due to the low thickness (35nm)
Thickness 3500Å BST
Dielectric constant variable
2g 10µm (gend=10µm) 4µm
2s 10µm 2µm
W 20µm 60µm
S - 140µm
d 40µm 84µm
l 20µm -
lo - 20µm
n 894 -
Metal circuits
m - 222
66
than 5dB and 20dB, respectively, were obtained by the BCS phase shifter, whereas the BI
shows S21 of 8dB, and S22 of 16dB at the same frequency ranges.
Since all process conditions for fabrication were identical except metal circuit
structure, this difference originates from the circuit design itself. This explanation can be
validated well by plotting the input impedances of each device on a Smith chart, as
depicted in Figure 4-14, where the data points of the BCS phase shifter are much more
concentrated in the vicinity of the 50Ω impedance point than observed for the BI phase
shifter. Accordingly, it can be concluded that the BCS-CPW structure is well-matched
with a characteristic impedance of 50 Ω compared to the BI-CPW design.
Fig. 4-13: Loss characteristics of the BI-CPW and the BCS-CPW phase shifter
67
The measured differential phase shifts for BI and BCS phase shifters are
compared in Figure 4-15 and Figure 4-16, respectively. DC bias voltages were applied
up to 300 V between the ground and signal line through bias-tee and DC blocks.
The BCS phase shifter exhibits continuous phase shifts of 0o~90o at 15GHz,
higher than the BI a phase shift capability reaching only 75o at the same frequency. This
difference could be explained by considering the finger design of each structure. Thus,
because of its narrow finger gap (4µm) as compared to the BI structure gap (10µm), the
BCS structure could confine the high external electric field more efficiently between the
fingers, making the contribution of BST film to dielectric tunability much greater. Thus,
it can be understood that by increasing the filling factor from the BST, larger phase shifts
are achieved.
Fig. 4-14: Input impedance plotted on a Smith chart of (a) the BI-CPW, and (b) the BCS-CPW phase shifter
(a) (b)
68
Leakage current characteristics were also investigated for both types of the
devices with bias voltages up to 100V. From Figure 4-17, it is noted that a 50nA of
leakage current at an applied voltage of 100V is obtained with the BCS structure. This
Fig. 4-15: Measured differential phase shifts of the BI-CPW phase shifter with bias voltages up to 300V
Fig. 4-16: Measured differential phase shifts of the BI-CPW phase shifter with bias voltages up to 300V
69
current level is much less than the BI structure that shows a leakage current level of
300nA, indicating an exponential increase beyond 65V. This would be attributed to its
large number of fingers (894), which may widen a current leakage path.
Therefore, it is concluded that from the viewpoints of insertion loss, phase shift
capability, and leakage current characteristic, the BCS-CPW type of BST phase shifter
exhibits better device performance.
4.7 Comparison of MEMS and BST phase shifter
In this section, two types of phase shifters, MEMS and ferroelectric phase shifter
presented in Chapter 3 and Chapter 4, respectively, are compared to determine a suitable
device design for constructing the phase array antenna system discussed in Chapter 1.
Important properties of both types of phase shifters are summarized in Table 4-3 .
Fig. 4-17: Measured leakage currents of the BST phase shifters
70
It is seen that even though the MEMS phase shifter with polymer bridges shows a
high value of phase shift per operating voltage (2.25o/V), mainly due to its low operating
voltage (40V), its other properties such as phase shift per insertion loss and leakage
currents level are poorer than the ferroelectric phase shifters. The most significant
concern of the MEMS phase shifter is related to reliability.
As discussed in Chapter 3, MEMS structures should be hermetically packaged for
stable operation because of their inherent environmental vulnerability including humidity,
shock, and vibration. In addition, fabrication is generally much more difficult compared
to the construction of planar structures. In contrast, in spite of its high operating voltage,
the ferroelectric phase shifter shows many advantages over the MEMS structure,
primarily in terms of reliability. Based on this comparison, it is determined that the BCS-
CPW ferroelectric phase shifter is employed as the phase shifting device for integration
into the array antenna system.
Table 4-3: Comparison of properties between the MEMS and the BST phase shifter
Ferroelectric MEMS
BI BCS Phase shift per insertion loss at 15GHz 18o/dB 14o/dB 30o/dB
Phase shift per operating voltage at 15GHz 2.25o/V 0.25o/V 0.3o/V
Leakage current at 100V ~20µA ~50nA ~300nA
Reliability Poor Good
Fabrication yield Poor Good
71
4.8 Summary
Two kinds of ferroelectric shifters utilizing the permittivity tunability of BST, one
with BCS-CPW structure and the other with BI-CPW structure, have been designed and
tested. It was confirmed by XRD and SEM measurements that the BST films deposited
on silicon substrates using a RF reactive sputtering system were well-crystallized. The
BCS phase shifter shows a phase shift capability of 30o/dB, two times higher than the BI
phase shifter (14o/dB). In addition, despite its high operating voltage, it has been proven
that the ferroelectric phase shifter is more suitable for phased array antenna applications
than the MEMS phase shifter because of its high operational reliability.
Chapter 5
MMIC COMPONENTS FOR THE ARRAY ANTENNA
Aside from phase shifters, each MMIC component of the array antenna has been
also fabricated and tested prior to implementing the whole array system on a silicon
substrate. These components include a single microstrip patch, a transition from CPW to
MS, a Wilkinson power divider, and a DC block. The silicon substrates were also
surface-treated by polysilicon and silicon oxide, as presented in Chapter 2. In this
chapter, a fundamental understanding of the each MMIC component is introduced, and
discussion about the RF performances of these fabricated devices is provided.
5.1 Microstrip patch
Microstrip antennas have found a broad range of applications in both the military
and the civil sectors that include radars, telemetry, and navigation, primarily due to their
conformability, simplicity, low manufacturing cost, and compatibility with MMIC
designs. In contrast, narrow bandwidth, and spurious feed radiations are some of
disadvantages of the original microstrip antenna configurations. However, improvements
have been achieved by introducing micromachined patches [62], aperture-coupled
feeding methods [63-64], and stacked radiating patches [64].
The microstrip patch antenna designed and fabricated herein consists mainly of a
rectangular radiator fed by a stripline, and a transition of CPW-to-MS. While study of
73
L
W
yo
CPW-to-MS transition
the microstrip antenna is, in this section, concentrated on the design as well as the
performance of the rectangular radiator itself, and the CPW-to-MS transition will be
discussed in the subsequent section in detail.
5.1.1 Design parameters for the patch radiator
A rectangular patch radiator can be completely characterized in terms of its
radiation pattern, input impedance, resonant frequency, bandwidth, beamwidth,
efficiency, gain, Q factors, and losses. There are several analytical models to predict
these parameters, which include the vector potential approach, the Diatic Green’s
function technique, the wire grid model, the radiation aperture model, the cavity model,
the modal expansion model, and the transmission model [65]. These analysis methods
will be instrumental for antenna designers to determine the critical parameters in a
microstrip antenna design.
Fig. 5-1: Schematic of the single microstrip antenna with a transition from CPW to MS
74
Figure 5-1 shows a schematic diagram of the rectangular patch used for the array
antenna. It is noted that the patch antenna has a transition from CPW to MS necessary
for combining the microstrip patch with the feed networks based on the CPW
configuration. The dimensions of the patches were determined so as to resonate at
15GHz using the following equations derived by the analytical models mentioned above
[66].
where L is the patch length, W the patch width, h the substrate thickness, and εr the
relative dielectric constant of substrate. Optimal values for the position of the inset feed-
point where the input impedance is 50Ω, as well as the patch dimensions, were validated
using IE3D software. The chosen values for W, L, and yo were finally 4000μm, 2800μm,
and 1060μm, respectively, expecting a resonance frequency of 15GHz.
5.1.2 Return loss, and radiation pattern
Figure 5-2 shows simulated as well as measured return loss, and the measured
input impedance of the patch antenna fabricated on a silicon substrate. The dot loop
lfcLreffr
∆−= 22 ε
5.1
reffr lL
cfε)2(2 ∆+
= 5.2
2/11212
12
1 −
+
−+
+=
Whrr
reffεε
ε 5.3
)8.0/)(258.0()264.0/)(3.0(
412.0+−
++=∆
hWhW
hlreff
reff
εε
5.4
75
around the center of the Smith chart indicates a 2:1 standing wave ratio (SWR)
bandwidth.
Fig. 5-2: (a) Return loss, and (b) Input impedance of the single microstrip antenna. Thedot loop around the center of the Smith chart indicates a 2:1 SWR bandwidth
(a)
(b)
76
A slight discrepancy exists in the resonance frequency between the simulated and
measured results. This could be attributed to either fabrication error or small deviation of
silicon dielectric constant from 11.7. It is seen that the single patch antenna resonates at
14.8GHz with a good return loss (S11) of 21dB, but a very narrow 2:1 SWR bandwidth
of 1.7%. The high dielectric constant of silicon (11.7) would make the bandwidth even
worse. Efforts have recently been made to improve the bandwidth by employing
micromachining techniques that artificially remove the substrate below the antenna and,
therefore, locally synthesize a low-dielectric constant region around the antenna. This
technique has been successfully applied by drilling closely spaced holes [67], or a cavity
around and beneath the microstrip antenna [62]. Wide bandwidth is especially important
in designing an array system, since it would be very difficult to overlap the resonance
frequencies of the radiating patches in the array with a narrow bandwidth if a large
discrepancy exists between each patch. Thus, this particular array may not radiate at the
resonance frequency due to small overlapped resonance frequency region between
patches. To improve array performance, more studies involving tolerance of narrow
bandwidth as well as discrepancy in the resonance frequency will be required.
Simulated radiation patterns show a typical shape of a single patch antenna, but
the patterns have an asymmetric shape along the X axis as expected, due to the feed line
connected to the patch (see Figure 5-3).
77
5.2 CPW-to-MS transition
5.2.1 Transition description
In order to integrate the microstrip antenna in an array with feed network based on
CPW lines, a compact low-loss CPW-to-MS transition should be designed. Some types
of via-less transitions based on radial stubs and sections of coupled lines have been
reported [68-69]. These transitions, however, do not give a compact design for
frequencies below 30GHz because they typically require a λg/4-long coupling region. In
this work, a new design approach has been tried employing an intermediate transition
region where the CPW line is gradually matched with the MS line, as was suggested by
Zheng et al. [70].
Fig. 5-3: Simulated radiation pattern of the single microstrip antenna
78
MS section
CPW-to-MS transition section
CPW section
The complete structure of the CPW-to-MS transition consists mainly of a CPW
section, a CPW-to-MS transition section, and a MS section. As seen in Figure 5-4, in the
intermediate region, both the signal line and the gaps between the ground lines in the
CPW section are gradually changed to adhere to a 50Ω characteristic impedance, until the
width of the signal line exactly finally matches the width of the MS line. It is expected
that this configuration will be helpful in minimizing reflections by suppressing the abrupt
introduction of discontinuity in circuitry.
The transition length numerically optimized using IE3D for the center frequency
of 15GHz, is 500µm, which corresponds to 0.076λg when calculated with the design
parameters of the CPW section at 15GHz. Apart from the transition section, the design
parameters for the CPW and the MS section are summarized in Table 5.1.
Fig. 5-4: Photograph of the CPW-to-MS transition fabricated on a silicon substrate
79
(a)
(b)
5.2.2 Transition characteristics
To facilitate coplanar on-wafer measurements, the transition was fabricated as
back-to-back configuration where two transitions are separated by a 2mm long microstrip
line, as shown in Figure 5-5 (a). In addition to the back-to-back transition, a simple
Table 5.1: Design parameters of the CPW and the MS section constructing the CPW-to-MS transition
CPW MS
Signal line width 100µm Gap between the ground lines and the signal line 60µm
Ground line width 500µm
Strip line width 300µm
Characteristic impedance 50Ω
Target frequency 15GHz
Fig. 5-5: Layout of (a) the back-to-back transition, and (b) the CPW circuit used for thru calibration standard
80
CPW circuit was also prepared with the same total length as the transition (see Figure 5-
5 (b)), and this was used as thru calibration standard to de-embed the loss characteristic
of the transition itself.
The measured and simulated S parameter results from 0 to 30GHz are shown in
Figure 5-6. Good agreement is seen between the simulations and measurements of the
back-to-back CPW-to-MS transition. The measured insertion loss (S21) at 15GHz
indicates 1dB. Since this value corresponds to the insertion loss for two transitions in the
back-to-back configuration, the insertion loss attributed to one transition could be
deducted by taking half of the measured insertion loss. The deduced insertion loss for a
single transition including CPW and MS lines at 15GHz is, thus, 0.5dB, and 3dB
Fig. 5-6: Simulated and measured S parameters of the CPW-to-MS transition
81
bandwidth is 168%. It is also seen that the return loss is better than 12dB from 7 to
22GHz, indicating that this transition can be used for wideband applications.
5.3 Wilkinson power divider
5.3.1 Design for ACPS power dividers
A Wilkinson power divider is a fundamental component extensively used in
various MMICs, such as power amplifiers and antenna distribution networks. One of the
most significant characteristics of the Wilkinson power divider is that all of its ports can
be finely matched and hence a good isolation between the output ports can be achieved
[71]. Because of this advantage over the other types of power dividers such as T-junction
dividers and resistive dividers, there have been many efforts to realize the Wilkinson
structure on silicon using MMIC technology [72, 21-22]. The typical Wilkinson power
divider consists of a three port passive reciprocal network, as shown in Figure 5-7.
The input signal at port 1 can be unequally divided between the two output ports
comprised of quarter-wave (λg/4) transmission lines. If the divided power between ports
2 and 3 is defined with a ratio of K2=P3/P2, then the divider design can be accomplished
by using the following equations:
+=
+==
+=
KKZR
KKZZKZ
KKZZ
O
O
O
1
)1(
,1
203
202
3
2
03
5.5
82
Port 1
Z0
Z02
Z03
R R2=Z0K
R3=Z0/K
Port 2
Port 3
where Zo, Z02, and Z03 are the characteristic impedances of port 1, 2, and 3, respectively,
and R is the shunt resistor for isolation between port 2 and 3. It is noted that the above
equations can be reduced to the equal-split case for K=1. Therefore, for the equal-split
power divider with a 50Ω-impedance input line, Z02, Z03 and R should be 71Ω, 71Ω, and
100Ω, respectively.
As a planar structure, ACPS configuration is more likely adopted for the
Wilkinson power divider since, with the ACPS, higher impedances can be easily
achieved, and fewer air bridges or bond wires to suppress slot propagation modes are
required compared to CPW [73]. The characteristic impedance, ZoACPS and the effective
permittivity, εeffACPS, of the ACPS on substrates can be derived from conformal mapping,
and expressed as [74]:
Fig. 5-7: Schematic diagram of a typical Wilkinson power divider
)'()(60kKkKZ
ACPSeff
ACPSo
ε
π= 5.6
)()'(
)'()(
211
1
1
kKkK
kKkKrACPS
eff−
+=ε
ε 5.7
83
b1 b2
W1 W2Sa a
h
where εr is the relative permittivity of the substrate, K(ki) is the complete elliptic integral
of the first kind, and ki depends on the geometrical parameters of the ACPS, as shown in
Figure 5-8.
Using the above equations, 500µm, 200µm, and 60µm are chosen as the values for
W1, W2, and S referring to Figure 5-8, respectively, in order to realize a 71Ω ACPS line
on Si (εr=11.7) whose line length is λg/4. The shunt resistor (Thin film resistor, TFR)
was defined by sputtering a 500Å thick Ti to achieve a resistance value of 100Ω with a
ratio of width to length=1. The ACPS divider was then connected to a 50Ω CPW line to
))(())((1'
))(())(2(
21
212
21
21
babaababkk
bababbak
++−−
=−=
+++
=
5.8
( )[ ] ( )[ ] ( )[ ] ( )[ ] ( )[ ] ( )[ ]
211
1121
21111
1'
1/2exp/2exp/2exp1/2exp/2exp/2exp
kk
habhabhbbhbbhabhabk
−=
−+−−+−+−−+
=ππππππ
5.9
Fig. 5-8: Dimension parameters for ACPS design
84
TFR
ACPS
CPW
facilitate on-wafer probing. Figure 5-9 shows a photograph of the ACPS Wilkinson
power divider fabricated on HRS.
5.3.2 Insertion loss, return loss and isolation of the power divider
At the final fabrication step for the power divider, Au bond wires were
implemented to connect the ground planes at discontinuities such as 90o bends, and Y-
junctions (see Figure 5-10), which equalizes the ground plane potentials as well as
prevents the higher order mode from propagating on the CPW lines.
Since the network analyzer is a two port system, two kinds of Wilkinson power
divider layouts were prepared, where one port is terminated with a 50Ω TFR. The first
layout (Figure 5-10 (a), PD1) was for measuring the insertion loss and return loss, and
the second layout (Figure 5-10 (b), PD2) was used for isolation measurements.
Fig. 5-9: Photograph of the Wilkinson power divider fabricated on HRS
85
Bonding wires
TFR
(a) PD1 (b) PD2
Figure 5-11 shows the measured S parameters for the ACPS divider. The
insertion loss (S21) measured from PD1 is around 3.5dB at 15GHz and shows insertion
losses better than 5dB at nearly all over frequency ranges up to 30GHz except from 5 to
8GHz, and again from 17 to 20GHz. Even though both return loss (S11) and isolation
between port 2 and 3 measured from PD2 are approximately 12dB at 15GHz, the
minimum values for the S11 and S23 of better than 30dB can be found at around
12.5GHz. Overall, it may be concluded that the Wilkinson power divider fabricated here
on HRS demonstrates high quality of RF performance making it applicable for an array
antenna system as a power distributor.
Fig. 5-10: Layout for the ACPS power dividers used to characterize the propagationperformances. PD1, and PD2 were used to measure the insertion loss, return loss, and isolation, respectively.
86
5.4 DC blocking filters
Fig. 5-11: Measured S parameters for the Wilkinson power divider fabricated on a surface-stabilized HRS substrate
Table 5.2: Design parameters of the DC blocks for CPW and MS
CPW MS
Gap between fingers 10µm 10µm
Line 1 width, S1 30µm 120µm
Line 2 width, S2 20µm 40µm
Total length ~λg/4
Target frequency 15GHz
87
(a)
(b)
line 2 (width, S2)
line 1 (width, S1)
line 2 (width, S2)
line 1 (width, S1)
Fig. 5-12: Photographs and schematic diagram of the DC blocking filters for (a) CPW, and (b) MS, both of which are built on silicon substrates
88
(a) (b)
A DC blocking filter is one important element extensively used in microwave
circuits. For wide-band applications, a large bandwidth as well as a low return loss in the
passband is indispensable for the device. In our array system, it is desirable that the DC
blocks completely insulate the high DC powers applied to the phase shifters from the
patch, as well as the other feed networks, while passing a wide range of RF signals.
Two kinds of DC blocking filters that consist of an open-end series (OES) stub
[75] were prepared for testing, one for CPW block, and the other for MS block. For both
DC blocks, the gap between the fingers is 10µm, and the total length corresponds to
about λg/4. Design parameters for both DC blocks, which were numerically optimized by
using IE3D, are listed in Table 5.2, and Figure 5-12 shows photographs and schematic
diagrams as built on silicon.
Fig. 5-13: Layout of the back-to-back DC blocks as well as the thru calibration standardcircuit for (a) MS, and (b) CPW
89
The test pattern for MS DC block is also fabricated as back-to-back configuration
where the DC blocks are connected to CPWs via CPW-to-MS transitions for coplanar on-
wafer measurements, as shown Figure 5-13 (a). To de-embed the loss characteristics of
the DC blocks, two thru calibration standard circuits having the same total length as the
DC block circuits were prepared. The thru calibration standard circuit for MS DC block
consists of two CPW-to-MS transitions separated by a 2mm long microstrip line, while
that for CPW DC block has a simple CPW structure (see Figure 5-13).
From Figure 5-14 and Figure 5-15, it is noted that the measured and simulated S
parameters of both the OES DC blocking filters agree well. The CPW DC blocks shows
an insertion loss of 0.4dB at 15GHz, and a wide 3dB-bandwidth of 130% with a return
loss of better than -12dB over frequencies from 11 to 21GHz.
Fig. 5-14: Simulated and measured S parameter results for the CPW DC blocking filter
90
The measured results for the OES DC blocking MS filter also indicate that this
filter can be used for wideband applications since it shows a wide 3dB bandwidth of
123% with an insertion loss of 0.2dB at 15GHz, and a return loss of better than 12dB
from 11 to 21GHz. Therefore, it can be concluded that both DC blocking filter designs
are also suitable for wideband applications.
5.5 Summary
Prior to implementing the entire array system on a silicon substrate, each MMIC
component comprising the array antenna was been fabricated on silicon and tested.
These components include a single microstrip patch, a transition from CPW to MS, a
Fig. 5-15: Simulated and measured S parameter results for the MS DC blocking filter
91
Wilkinson power divider, and a DC block. The design for each component was validated
and optimized using a commercial simulation tool before fabrication.
The single microstrip patch antenna shows a resonance frequency 14.8GHz with a
good return loss (S11) of 21dB. This microstrip patch is connected to the feed networks
based on CPW lines through a CPW-to-MS transition. The newly designed transition
achieved a very low insertion loss of 0.5dB at 15GHz, and a 3dB bandwidth of 168%,
demonstrating the possibility for wideband applications. A 3.5dB power split and a 12dB
isolation at 15GHz could be obtained using the Wilkinson power divider consisting of
ACPS and CPW lines, a key element necessary to distribute RF powers to each radiating
patch. In addition, it has been proven that both of the DC blocks for CPW and MS
consisting of OES are also suitable for wideband applications because of their wide 3dB
band width of 123%, and 130%, respectively. The complete array antenna has been
monolithically implemented on silicon based on these results for each MMIC component.
Chapter 6
FOUR ELEMENT PHASED ARRAY ANTENNA
6.1 Introduction
To produce a directional radiation pattern, multiple radiating elements can be
arranged in space constructing an array antenna. The radiation from the elements adds up
to give a maximum field intensity in a particular direction, and cancels or very nearly
cancels in others. Thus, when the phase of the exciting currents in each element antenna
of the array is changed, the radiation pattern can be steered through space. The array is
then called a phased array. The radiation pattern of an array in free space is well known
to depend upon five factors. These include the geometrical configuration of the overall
array (linear, circular, rectangular, spherical, etc.), the relative displacement between the
elements, the excitation amplitude of the individual elements, the excitation phase of the
individual elements, and the relative patterns of the individual elements [66].
In this work, a prototype scanning four-element linear phased array antenna
fabricated on silicon substrates has been developed The phase array antenna consists of
BST phase shifters and other MMIC components such as Wilkinson power divider,
microstrip patches, DC blocks, and CPW-to-MS transitions, as was discussed in the
previous chapters. Beam steering is accomplished electronically by varying the biased
DC voltages to the BST phase shifters causing a change in the permittivity value of the
BST film, resulting in phase shifts of the electromagnetic waves radiated at the antenna
93
terminals. Chapter 6 presents the design, fabrication, and performance of the phased
array antenna monolithically integrated into silicon.
6.2 Array design
6.2.1 Linear array factor, side lobe level, and beamwidth
The most elementary of arrays is a linear array in which the array element centers
lie in a straight line. The pattern of each element varies with the arrival angle and
amplitude of the incoming wave, which may be controlled by phase shifters and
attenuators. The angular dependence of this resulting pattern is called the array factor,
determined solely by the element positions, with amplitudes and phases denoted by In. If
a linear array consisting of N elements is symmetrically distributed with constant
interelement spacing, the array factor of such geometry is then given by [76]:
for even number of elements. In the case of odd number of elements, the array factor
could be written as:
where ψ=kdcosθ+β, k=2π/λ, λ is the wavelength, d the interelement spacing, θ the angle
measured from the line of the array, and β the phase difference between elements. In
addition, In is the magnitude of the current for the nth element on either side of the array
midpoint, and Io denotes the current of the center element when N is odd.
∑=
−=
N/2
1nn ψ
21ncosI2AF 6.1
( )∑−
=
+=1)/2(N
1nno nψcosI2IAF 6.2
94
A typical antenna radiation pattern for steering is shown in Figure 6-1. The main
lobe contains the direction of maximum radiation. In most cases, there are also a series
of smaller lobes called minor lobes. The minor lobes immediately adjacent to the main
lobe are side lobes, which in most cases are the largest of the minor lobes, and hence of
greatest importance. The ratio of the pattern value of a side lobe peak to the pattern value
of the main lobe is referred to as side lobe level (SLL), which indicates how well the
power is concentrated into the main lobe. The larger the SLL value, the better the
antenna performance, from the point of view of favoring main lobe signals and
discriminating against signals from other directions. The SLL can be defined as:
where /F(max)/ is the maximum value of the pattern magnitude, /F(SLL)/ the pattern
value of the maximum of the highest side lobe magnitude, and R the main beam-to-side
lobe ratio. For a normalized pattern, F(max)=1.
The half-power beamwidth (HPBW) is another meaningful parameter that
describes the resolution capabilities of the antenna to distinguish between two adjacent
radiating sources or radar targets. The HPBW is defined as the angular separation of the
points where the main beam of the power pattern equals one-half. Thus:
where θHP left, and θHP right are the left and the right points of the main beam maximum for
which the power pattern has a value of one-half (See Figure 6-1). There exists a tradeoff
between the HPBW and the SLL, that is, as the beamwidth decreases, the sidelobe
RF
SLLFSLLdB log20
(max))(
log20 −== 6.3
HPBW=|θHP left - θHP right | 6.4
95
Minor lobes
Main lobe
Main lobe maximum direction
Half power beamwidth (HPBW)
0.5
1 Half power point (right)
Half power point (left)
increases, and vice versa. Hence, it is apparent that there should be a compromise
between them in designing an array antenna.
6.2.2 Array tapering by Dolph-Chebyshev distribution
Radar systems generally require that side lobes be 20 to 30 dB below the main
lobe, and in special cases even greater reduction may be desired. It has been found that
side lobes can be considerably reduced if the center element of the array radiates more
strongly than the end elements. Thus, as the current amplitude is tapered more toward
the edges of the array, the side lobes tend to decrease, but the beamwidth increases. The
Dolph-Chebyshev array, based on the use of mathematical functions called Chebyshev
Fig. 6-1: Typical power pattern polar plot in steering
96
polynomials, is one of the most effective means of distributing the current amplitude in
an array to accomplish a reduction of SLL. Chebyshev polynomials are defined by [76]:
and, the recursion formula for Chebyshev polynomials is given by:
By choosing an appropriate transformation between x in equation 6.5, and ψ in Equation
6.1 and 6.2, the array factor and Chebyshev polynomial will be identical. The
transformation:
and the correspondence:
yield a polynomial in powers of cos(ψ/2) matching that of the array factor. Since the
main beam-to-side lobe ratio, R is the value of the array factor at the main beam
maximum, the following equation can be derived from Equation 6.5.
or
( )( )( )
−
=−
−
−−
xn
xn
xn
xT
n
n1
1
1
coshcosh
coscos
coshcosh)1(
)( , 1
111
><<−
−<
xx
x 6.5
)()(2)( 11 xTxxTxT nnn −+ −= 6.6
2cos0
ψxx = 6.7
= − 2
cos01ψxTAF N 6.8
]cosh)1cosh[()( 01
01 xNxTR N−
− −== 6.9
−= − R
Nx 1
0 cosh1
1cosh 6.10
97
With the aid of Chebyshev polynomials, one can find the current distribution that results
in the minimum beamwidth for a given degree of side-lobe reduction.
Figure 6-2 (a) and (b) shows the calculated Dolph-Chebyshev array factor for a
four element linear array equally spaced at a half wavelength (d=λ/2) with side lobe
levels of 20dB and 40dB, respectively. It is noted that the better the side lobe levels, the
wider the beamwidth, as expected. Thus, the array shows a HPBW of 28o with a SLL of
20dB when a 1.735743:1 of Chebyshev current distribution is given, whereas a
2.668758:1 current distribution results in a HPBW of 37.2o, and a SLL of 40dB.
It is even possible to eliminate the side lobes completely, in principle, by means
of a binomial current distribution, written as am, which satisfies the following binomial
expansion:
However, the taper is so extreme that it would be very difficult to realize, in practice,
power dividers, which support the binomial current distributions. Moreover, the
theoretical absence of side lobes is not likely to be achieved because of unavoidable
imperfections in the antenna geometry, phasing and feed system. Calculated current
distribution magnitudes for linear, equally spaced Chebyshev and binomial arrays are
summarized in Table 6.1.
( ) ( ) ( )( ) ( )( )( )K+
−−−+
−−+−+==+ ∑
=
−− 32
1
11
!3321
!221111 xmmmxmmxmxax
m
mm
m 6.11
98
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 20 40 60 80 100 120 140 160 180
Theta
AF
dB
current magnitudei1:i2=1.735743:1
HP=28.0o
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 20 40 60 80 100 120 140 160 180
Theta
AF
dB
current magnitudei1:i2=2.668758:1
HP=37.2o
(a)
(b)
Fig. 6-2: Dolph-Chebyshev synthesized array factors for a four element, λ/2 spaced with (a) -20dB, and (b) -40dB side lobes
99
-30
-25
-20
-15
-10
-5
0
0 20 40 60 80 100 120 140 160 180
Theta
AF
dB
current magnitudei1:i2=1:1
HP=23.3o
For easy of fabrication, a four element phased array antenna with equally spaced
(d=λ/2) elements, and uniform current distribution of 1:1:1:1 has been fabricated as a
prototype. The calculated array factor for this configuration is shown in Figure 6-3,
which predicts a 12dB of SLL with a 23.3o of HPBW.
Table 6.1: Current magnitude for linear equally spaced Chebyshev and binomial arraysCurrents of edge elements are unity
Dolph-Chebyshev Array element binomial
SLL=-20dB SLL=-40dB
1 1 1 1
2 3 1.735743 2.668758
3 3 1.735743 2.668758
4 1 1 1
Fig. 6-3: Array factor for a four element, λ/2 spaced linear arrays with an uniform current distribution of 1:1:1:1. The obtained HPBW and SLL are 23.3o and 12dB, respectively.
100
(a) (b)
(c)
(e) (d)
θ=10o θ=15o
θ=15oθ=10o
6.2.3 Beam steering
Fig. 6-4: Simulated radiation patterns of the array antenna showing beam steeringaccording to the phase difference(β) between the elements (a) β=30o, (b) β=60o, (c) β=0o, (d) β=-30o, and (e) β=-60o
101
The most important advantage of a phased array is its ability to produce a beam
that can be directed at various angles by controlling the progressive phase difference (β)
along the array. Beam steering may be accomplished by mechanically turning the entire
antenna, but the scanning speed is limited by the size and weight of the antenna.
Therefore, considerable efforts have been made to develop electronic phase shifters that
can rapidly control phase shifts along an array with no mechanical motion. The BST
phase shifters discussed in Chapter 4, which have been integrated into the prototype
phased array, are good candidates for this purpose.
Figure 6-4 shows the simulated beam steering results for the array with elements
equally spaced (d=λ/2) and an uniform current distribution when ±30o and ±60o of phase
difference (β) are given between the elements. It is seen that beam steering capabilities
of ±10o and ±15o on each side are expected for the given phase difference of ±30o and
±60o, respectively, corresponding to ±20o and ±30o of total scan.
6.3 Implementation of a four element array antenna on silicon
The 15GHz array antenna system developed herein consists of a monolithic 1:4
CPW feed network and a monolithic set of microstrip patch radiators, as shown in
Figure 6-5. Inter-element spacing is 11.25mm, corresponding to half free-space
wavelengths.
Monolithic implementation of the array started with the preparation of silicon
substrates. High resistivity silicon (HRS) substrates were thoroughly cleaned through
standard clean 1 (SC1) and standard clean 2 (SC2), followed by deposition of a 1µm-
102
thick polysilicon layer and a 400Å-thick silicon oxide layer under the same conditions, as
described in Chapter 2.
(Ba,Sr)TiO3 thin film with a thickness of 3500Å was then RF-sputtered on the
substrates using the deposition conditions presented in Chapter 4 for construction of
ferroelectric phase shifters. To minimize RF loss from the BST film, the BST thin film
was etched out using hydrofluoric (HF) acid, except where the phase shifter circuits were
to be built on. Gold metal deposited using an evaporator was then patterned by standard
photholithography techniques, and electroplated up to 2µm thickness, in order to
construct the four element phased array antenna circuits. Details for the fabrication
process are summarized in Figure 6-6.
Fig. 6-5: Photograph of the four element phased array antenna fabricated on a siliconsubstrate consisting of power dividers, microstrip patch antennas, phase shifters, DC blocks and CPW-to-MS transitions
103
Fig. 6-6: Fabrication flow for the phased array antenna system
Substrate material: N-type, ρ>5000Ωcm, (100) silicon
Initial cleaning: SC1, SC2
Amorphous silicon deposition by LPCVD,
followed by dry oxidation at 950oC
BST RF sputtering at 120W, 20mTorr, 10% oxygen gas, 750oC
BST patterning for phase shifters by HF
DC sputtering Au/Cr as a seed layer for electroplating
Defining the array antenna circuit by lithography
Au electroplating
Removal of photoresist, followed by Au/Cr seed layer etching
104
6.4 Radiation pattern measurements
6.4.1 Equipment set up for measurements
To determine the radiation pattern of antennas, two antennas are needed: one
under test being rotated, and the other remaining fixed. The antenna under test (AUT) is
mounted on an electromechanical system called a positioner, with one or more degrees of
Fig. 6-7: Set up for radiation pattern measurements
Controller
Antenna under test
Computer
AmplifierNetwork Analyzer
Wideband horn antenna
Positioner
105
freedom. A network analyzer can also be used to measure the radiation pattern as well as
antenna input characteristics such as return loss, VSWR, and/or input impedance. The
experimental set up for radiation pattern measurements is shown in Figure 6-7. Since the
outgoing signal from test antennas is generally very weak, an amplifier is often used in
the receiver circuit. When a standard antenna is used as the transmitter and test antennas
as the receiver, S21 is measured using the analyzer.
Custom software is used to control the positioner, as well as to download data
from the network analyzer. This software is also capable of generating radiation pattern
plots at individual frequencies, or S21 versus frequency at different observation angles of
the test antennas. At the beginning of the measurement, first the test antenna placed on
the positioner is pointed toward the transmitter. The test antenna is carefully aligned at
the direction of its peak by controlling the positioner. S21 is then measured using the
network analyzer at 90o, where the maximum power can be obtained. The network
analyzer is normalized with the maximum value. With this calibration, one can have
relative radiation powers along with angles with respect to the maximum value.
6.4.2 Radiation pattern and beam steering
Prior to measuring the radiation patterns of the four element array antenna
fabricated on a silicon substrate, S11 was measured using a HP8510C vector network
analyzer to find the resonance frequency of the antenna. Figure 6-8 shows the measured
results for the S11 and input impedance drawn on a Smith chart. It is noted that this array
106
(a)
(b)
antenna has a resonance frequency of 14.85GHz with an excellent return loss (S11) value
of around 32dB, and a 2:1 SWR bandwidth of 8.7%.
Fig. 6-8: (a) Return loss, and (b) input impedance of the four element phased arrayantenna monolithically fabricated on a silicon substrate. The dot loop around the centerof the Smith chart indicates a 2:1 SWR bandwidth.
107
The measured and the simulated radiation pattern (at φ =90o cut) of the array
antenna at the resonance frequency (14.85GHz) without any bias to the array are shown
in Figure 6-9. Good agreement is obtained between both the patterns with the first nulls
at around 60o and 120o. The measured 3dB beamwidth (HPBW) of the main lobe and
side lobe level (SLL) are around 20o and -7dB, respectively. This high SLL value and
many minor lobes shown in the measured pattern are due to the parasitic radiations from
the feed networks in the array, as well as reflections from environment. These spurious
radiations from the feed could be significantly reduced by adopting other feeding
techniques such as the aperture coupling method, where the metal ground inserted
between the feed and the radiating patches suppresses the spurious radiation from
interfering with the antenna pattern. More details will be discussed in Chapter 7.
Fig. 6-9: Measured and simulated radiation patterns (at φ =90o cut) of the four element phased array antenna at 14.85GHz
108
10o
To realize beam steering of the array antenna, the wave phase arriving at the patch
terminal needs to be controlled. This work is possible by varying the bias voltage applied
to the phase shifters that are connected to each patch element, resulting in a change in
phase velocity. Thus, the direction of the beam can be changed by controlling the
relative phase relationships between the individual antenna elements using the BST phase
shifters in our array antenna. The external voltages are applied though the bias stub
connected directly to the BST phase shifter (see Figure 6-5) using gold bond wires.
Figure 6-10 shows the measured radiation patterns when the phase shifter circuits
are biased. The voltages applied to each phase shifter were 0V, 80V, 150V, and 300V, at
which phase shifts of 0o, 30o, 60o, 90o are expected at 15GHz, respectively, according to
Figure 4-16. It is noted from Figure 6-10 that a 5o phase tilt of the main beam on each
Fig. 6-10: Measured radiation patters showing the capability of beam steering with aphase tilt of the main beam of 5o on each side
109
side, corresponding to 10o of total scan, was obtained. Thus, results show that the
measured steering capability is smaller than the simulated (20o of total scan, see
Figure 6-4). This difference would be due to deviation of the phase shifts in the array
from expected values, or because phase calibration at the terminal of each patch element
was not taken, which may require a modification in voltage-biasing configuration for the
phase shifters. For wide applications of this array antenna, further research should be
concentrated on enhanced steering capability, which would be accomplished by
improving the performance of the phase shifters, and/or modifying the array design itself.
6.5 Summary
A four element phased array antenna has been monolithically implemented on
silicon substrates. The array antenna consists of radiation patches and feed networks
including CPW-to-MS transitions, BST phase shifters, Wilkinson power devices, and DC
blocks. The array resonates at 14.85GHz with a return loss of 32dB and a 2:1 SWR
bandwidth of 8.7%. The radiation patterns measured at the resonance frequency without
biasing show good agreement with simulated results. In addition, it is observed that the
array antenna shows a total scan of 10o with voltages applied to the BST phase shifter
circuits. Further research will be required to increase the beam steering capability.
Chapter 7
CONCLUSIONS AND FUTURE WORKS
Development of phased array antenna systems is essential to fulfill the demand
for broadband wireless communication services. However, a hybrid device would be
limited in use because of high fabrication cost and massive structure. The necessity for
phased array antennas with low cost, compact size, and good reliability initiated this
research work, which has addressed the monolithic implementation of a phased array
antenna system on silicon with a target frequency of 15GHz. The research work also
includes substrate preparation, and the design and the fabrication of radiating patches, as
well as feed networks.
First, to investigate and compare loss characteristics due to substrates, 2.5mm-
long CPW lines were fabricated on three different substrates (HRS, CMOS grade silicon
and quartz). It is generally known that direct deposition of oxide layers on silicon
populates surface charges in the interface between the oxide and the silicon substrate,
resulting in excessive RF losses. This is true even for HRS. These surface charges could
be successfully immobilized by inserting a surface stabilizing layer of polysilicon into the
interface of SiO2/Si, since the abundant localized states within the energy band gap of
polysilicon act as traps to hold the surface charges, suppressing high RF losses. This
results was validated by measuring significantly low insertion loss (0.16 dB at 15GHz)
with 50Ω CPW lines fabricated on a HRS substrate surface-stabilized by polysilicon.
111
This poly-Si/SiO2/HRS substrate configuration was applied to all substrates where MMIC
components and phased array antenna systems were built.
Phase shifters are key elements in construction of a phased array antenna, where
the phase shifters control the wave phase arriving at the radiating element, enabling the
antenna to steer the beam direction. Two types of phase shifters have been developed
herein: a MEMS phase shifter and a ferroelectric phase shifter. In order to reduce
operation voltage, the MEMS phase shifter utilized polymer as bridge materials with
Young’s modulus around 5GPa, significantly low compared to metal (50~100GPa). The
polymer bridges were metal-coated to operate as electrical actuators. When the bridges
are biased with respect to the center electrode, the bridge begins to be pulled down,
resulting a change in the bridge capacitance. This capacitance change, in turn, alters the
phase velocity traveling along the transmission line of the device, causing phase shifts at
the device terminal. The polymer MEMS phase shifter fabricated on silicon showed a
phase shift of 90o at 15GHz with a pull down voltage of 40V. Bridge bending problems
attributed to the internal stress of the bi-layered bridge resulted in excessive RF losses, as
well as difficulty in further reduction of the pull down voltage. This buckling issue could,
however, be lessened by using a single conductive polymer layer for the bridge material.
In addition, it should be noted that hermetic packaging is required for the MEMS devices
to prevent the stiction problem for improved reliability in device operation.
As for the ferroelectric phase shifters, two metal circuit designs, BI-CPW and
BCS-CPW structure, were tested, both of which utilized the permittivity tunability of
BST films to control phase delays. The BST film grown by RF reactive sputtering was
characterized by XRD and SEM measurements showing a well-crystallized structure.
112
The BCS phase shifter showed a phase shift capability of 30o/dB, two times higher than
that of the BI phase shifter (14o/dB). Based on the overall comparisons between MEMS
and ferroelectric phase shifters in terms of phase shift capability, operating voltage,
leakage current level, and reliability in operation, it is concluded that the ferroelectric
phase shifter, in spite of its high operating voltage (~300V), is more suitable for phased
array antenna applications than the MEMS phase shifter.
Aside from phase shifters, each MMIC component of the array antenna was also
fabricated and tested, including a single microstrip patch, a transition from CPW to MS, a
Wilkinson power divider, and a DC block. The design for each component was validated
and optimized using a commercial simulation tool before fabrication. A resonance
frequency of 14.8GHz with a return loss of 21dB was obtained from the single microstrip
patch antenna connected to the feed networks based on CPW lines through a CPW-to-MS
transition. This transition exhibited the possibility for wideband application by showing
a wide 3dB bandwidth of 168% and a very low insertion loss of 0.5dB at 15GHz. A
3.5dB power split and a 12dB isolation at 15GHz could be obtained using the Wilkinson
power divider consisting of ACPS and CPW lines, a key element for distribution of RF
powers to each radiating patch. It is also believed that the DC blocks for CPW and MS
consisting of OES are suitable for wideband applications due to their wide 3dB
bandwidth of 123% and 130%, respectively.
Based on the design of each MMIC component, a four element phased array
antenna was monolithically implemented on silicon substrates. The radiation patterns
measured at its resonance frequency (14.85GHz), with a return loss of 32dB without
biasing showed good agreement with the simulated patterns. In addition, it was observed
113
that the array antenna has a total scan capability of 10o with application of voltages to the
BST phase shifter circuits.
Even though this array antenna monolithically realized on silicon using MMICs
technology showed beam scanning capability, the degree of steering is not yet sufficient
for military or civil applications. In addition, the side lobe level (SLL), half power beam
width (HPBW) and bandwidth need to be improved.
To increase the beam steering capabilities, a significant advance in the
performance of phase shifters is indispensable. For ferroelectric phase shifters, it would
be important not only to improve the BST film quality, but also to enhance the filling
factor contributed from BST, by optimizing the finger design. Low operating voltages
can also be accomplished with hermetically packaged MEMS phase shifters.
To suppress spurious patterns radiated from the feed networks, one of the main
factors causing deterioration of SLL and HPBW of antennas, the feeding method and
antenna structure must be changed to aperture-coupled stacked antennas. In this
configuration, metal ground planes inserted between radiating elements and feed
networks prevent the main beam from interfering with parasitic radiations, and the feed
line is coupled through a small aperture in the ground planes, as shown in Figure 7-1.
The microstrip patch antennas can be also replaced with slot antennas for wide band
applications.
In summary, the phased array antenna presented herein will provide a basic view
and understanding of the process of monolithic integration into silicon using MMIC
technology, and could be further optimized to synthesize an antenna configuration for
specified radiation characteristics.
114
Radiating patch
Ground plane/ coupling slots
Power distribution network
Fig. 7-1: Schematic diagram of an aperture-coupled stacked antenna
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Appendix
Non-Technical Abstract
Demand for broadband wireless communication services has been increasing
explosively, driving the surge of research and development activities for future wireless
communication systems with higher data rates and increased functionality. Phased array
antenna systems have proven to play a key role in improving system performance so as to
fulfill the demand by increasing channel capacity, steering multiple beams, and
compensating for aperture distortion.
During the past few years, smart antennas adopting these array systems have been
developed for commercial as well as military use to suppress multipath fading, delay
spread and cochannel interferences, resulting in better quality of services. The array
system offers the unique capability of electronic scanning of the main beam. By
changing the phase of the exciting currents in each element antenna of the array, the
radiation pattern can be scanned through space. By this means, the beam can be very
quickly steered electronically and becomes capable of tracking fast-moving and multiple
targets in a fashion which is impossible with a traditional rotating-dish antenna.
This thesis presents the design and fabrication of a four element phased array
antenna on high resistivity silicon (HRS) substrates, especially, using monolithic
microwave integrated circuits (MMICs) technology since it is impractical to fabricate a
large smart antenna system with hybrid MICs technology due to the size and mass of
hundreds of individual transmitter-receiver modules required in the antenna system. The
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phased array antenna system presented herein would be the first step to provide a basic
view for realizing smart antenna systems with an excellent performance.
VITA
Taeksoo Ji received his bachelor and master degree in Physics from Yonsei University,
Seoul, Korea in 1995, and 1997, respectively. During 1997 to 2000, he served as a
researcher at Hyundai Electronics, Yichon, Korea, where he worked on plasma display
panel (PDP) development. He joined then the Department of Engineering Science and
Mechanics, the Pennsylvania State University in January 2001 for doctoral studies. He
has been a research assistant at the Center for the Engineering of Electronic and
Acoustic Materials and Devices ever since. His research interests include phased array
antennas, phase shifters, MMIC integration, RF-MEMS for microwave applications.
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