A distributed test system for pipelined ADCs · of test results and ADC models for devices already...
Transcript of A distributed test system for pipelined ADCs · of test results and ADC models for devices already...
A distributed test system for pipelined ADCs
E. Mancini a, S. Rapuano b, D. Dallet c,
a University of Sannio - Department of Engineering
Viale Traiano, Palazzo ex Poste, 82100 - Benevento - Italy
Phone: +39 0824 305 540, Fax : +39 0824 50552, E–mail: [email protected]
b University of Sannio - Department of Engineering
Corso Garibaldi, 107 - 82100 - Benevento - Italy
Phone: +39 0824 305 804, Fax : +39 0824 305 840, E–mail: [email protected]
c IMS Laboratory - ENSEIRB - Universite Bordeaux 1 - CNRS 5218,
351 Cours de la Libration, Batiment A31, 33405 Talence Cedex, France
Phone: +33 5 40 00 26 32, Fax : +33 5 56 37 15 45, E–mail: [email protected]
Abstract
The paper presents a distributed test system for pipelined ADCs including a model-
based characterization process. A set of modular Virtual Instruments has been de-
veloped in Java to execute the system functions in order to be remotely manageable
through a common Internet browser. The system features include (i) a module able
in modeling an ADC through the specialization of a simplified behavioral model;
(ii) a module executing the dynamic testing of the device; (iii) a scalable database
providing the data sharing among more remote users; and (iv) some interface mod-
ules to programmable instrumentation. The paper also presents the results of the
first validation of the system, carried out on two pipelined ADCs.
Key words: pipelined ADC, modeling, virtual instrumentation, Java.
Preprint submitted to Elsevier 24 January 2008
1 Introduction
Researchers consider that System-On-Chip (SoC) will be the revolution of
the new century in electronic design as ASIC (Application-Specific Integrated
Circuit) was at the end of the last one. The ADCs play a fundamental role in
interfacing the processing core with the analogue world. The wide use of mixed-
signal SoCs in electronic systems opens the problems of behavioral modeling
and testing of such a complex structure by means of behavioral languages like
SIMULINK or VHDL-AMS. The paper deals with these problems focusing on
the analog-to-digital conversion stage implemented by means of a pipelined
converter.
Pipelined ADCs are available today with resolutions up to 14 bits and sam-
pling rates over 250 MHz. They offer the resolution and the sampling rate to
cover a wide range of applications, including digital imaging, digital telecom-
munications, digital video, and fast Ethernet. A popular application for these
converters is in software-defined radios that are used in modern cellular tele-
phone base stations. ADCs most commonly range in resolution going from 8
to 16 bits and provide low power consumption as well as a small form factor.
This combination makes them ideal in a wide variety of applications, such as
portable/battery-powered instruments, pen digitizers, industrial controls, and
data/signal acquisition [1, 2].
In the following a distributed test system is proposed implementing the iden-
tification of a behavioral model of pipelined ADC by means of histogram and
FFT dynamic tests described in IEEE 1241 standard [3].
A distributed Virtual Instrument (VI) has been developed to manage: (i) the
2
test set-up, (ii) the data acquisition, (iii) the data processing, and (iv) the
result storage by means of specific sub-VIs being executed on PCs located in
different laboratories. Each laboratory can produce its own model and iden-
tification procedure and make them work on the test system implemented in
another one. In such a manner it is possible to: (i) remotely execute the test
and identification of an ADC, (ii) exchange the measurement data for making
parallel processing on the same device, and (iii) realize a common repository
of test results and ADC models for devices already on the market, setting the
bases for an efficient collaboration of different research groups on the same
topic.
Section II presents a case-study of SIMULINK behavioral model of a three
stage pipelined ADC and its components: flash ADC, Digital to Analog Con-
verter (DAC), Sample and Hold Amplifier (S/H). An Input-Output mathe-
matical relation is also proposed. Section III is dedicated to the methodology
used for the estimation of the error parameters, taking in account measurement
results obtained by adjusting the input signal amplitude. Then, in Section IV,
the architecture of the distributed VI is described and discussed, focusing on
a couple of virtual instruments (VIs) dealing with modeling and testing tasks
within the IEEE 1241 standard specifications [3] is presented. The VIs have
been developed in Java, in order to be independent from the working platform
and assure an inner networking support. Moreover, they are modular, assuring
high-grade expandability and flexibility.
An experimental evaluation of the proposed system has been carried out on a
10 bit, 20 MHz ADC by Analog Devices with three stages, each containing a
4 bit flash ADC. The overall 10 bit output is obtained by means of a digital
sum of the More Significant Bit (MSB) of the output code of each flash ADC
3
with the Least Significant Bit (LSB) of the output code of the ADC of the
preceding stage [4]. The obtained results are presented in the last Section of
the paper.
2 Pipelined ADC model
A pipelined converter is constituted of several stages, each of them composed
by an ADC, a DAC and a Sample and Hold (S/H), with the aim to convert
a sub-range of entire code [5]. The input full scale signal to be converted is
processed by the first stage that acts a conversion of the most significant bits
and sends the resulting code both to the correction logic block and to a DAC.
The DAC acts a conversion from digital to analogue and the resulting value is
subtracted from the input. The resulting error value is sent to the next stage
to be processed in a similar way. Each stage adds also a delay cycle. A logic
correction block recovers the correct digital output starting from the partial
outputs of each stage by applying opportune shifts.
Fig. 1. Simulink model of a 3-stage pipelined ADC.
In Fig. 1 a block scheme, in SIMULINK environment, for a three stage pipelined
ADC is given. Each stage is similar to that shown in Fig. 2. In order to imple-
4
Fig. 2. Simulink model of each stage of the pipelined ADC.
ment S/H, ADC and DAC, simple models have been used for each block [5,6].
The model has been developed starting from the data sheets [7]. The following
equation has been used to the model of each ADC stage:
y (k) = Q
(S
(n∑
i=0
aixi (t) + b
dx (t)
dt
))(1)
where x (t) is the analog input signal, Q (·) is the ideal quantizer function,
S (·) is the saturation function, ai are the error coefficients, bdx (t) /dt the
jitter model. Each stage of the pipelined ADC uses a DAC as shown in Fig.2.
It has been considered that this component could be described by a third
order polynomial function. The following relation has been adopted for the
modeling of each DAC [5]:
y (t) =3∑
i=0
cixi (k) (2)
where ci are the error coefficients.
Then, the last component used in each stage, the sample and hold amplifier
has been modeled by the following equation [5]:
y (t) = ftx (t) + Zh
(dix
i (t))
(3)
5
where ft is the feed-through coefficient, Zh (·) is the hold function, and di the
error coefficients.
The main target of the modeling phase is to identify the ai, bi, ci, di and ft
coefficients which minimize the error between the actual and model output.
3 Parameter estimation
In order to evaluate the error parameters, a sine wave signal is generated as
input to a real ADC (Fig.3).
Fig. 3. Method diagram, including software and hardware blocks.
The obtained samples are used to estimate the analogue input sine wave pa-
rameters from the signal DFT and a three parameter sine fitting, as in [3].
From this estimate the amplitude, offset, phase and frequency of the signal
can be used to produce an analytical signal x (t) as input to the ADC model.
The output samples coming from the model are then compared with the ac-
tual ADC samples. The comparison could be done in the frequency domain,
in the time domain or in the amplitude domain.
By using a multidimensional minimization algorithm, the model can be im-
proved, by reducing the differences between the two data sequences. The fit-
6
ting of the model outputs to the actual ADC ones depends on the chosen
minimization algorithm.
Many algorithms have been proposed in literature for such a task [8, 9]. At
this time the modified Aitken algorithm has been used. The modified Aitken
algorithm splits the parameter range in sub-ranges, and executes iteratively
the following steps:
(1) For each parameter it searches the value that minimizes the error between
the actual ADC and the model output.
(2) The step 1 is repeated from the first to the last parameter and then from
the last to the first one.
(3) The iterations stop when a previously fixed improvement is obtained
or when the improvement obtained in the last step is under a certain
percentage of the former one.
4 The distributed test and identification system
As it is shown in Fig.4, the architecture of the proposed distributed test sys-
tem is based on two VIs executing the model identification, as described in
Section II, and the ADC test, as described in Section III, [10], [11], and two
VIs that are used to acquire and manage the data. In particular, the second
one, a document manager, sorts and distributes the measures to the working
group participants. All the modules have been realized by using the Java lan-
guage and the CORBA technology in order to ensure good portability, good
expandability and the networking support. The first VI, called AdcX, imple-
ments the method described in the previous section. It takes sampled data
7
Fig. 4. Architecture of the proposed distributed measurement system.
from a file or a CORBA server and sets the parameters of a Java written
model. In order to assure an easy expandability, it is as general as possible.
Thanking to its modular structure, the VI leaves the user free to include his
own ADC model by providing a Java written model with the required soft-
ware interface to the main program. In order to speed-up the development of
new modules, a template as been realized, including a set of Java interfaces,
that only have to be specialized with the characteristics of a specific ADC.
Fig. 5 shows the main graphical user interface (GUI) for AdcX. The second
VI, called AdcT (Fig.6), implements the ADC testing. It controls a signal
generator and retrieves the output samples of an actual ADC under test, by
means of a direct communication with an instrumentation control module, or
from an ADC model, provided with the same method as to AdcX. Then, it
computes the histogram (Fig.7a) and the FFT (Fig.7b) of the input signal as
specified in [3]. In future a time-frequency analysis tool will be implemented
too. AdcT supports also the data coding (e.g. Gray coding) with the possibility
of implementing new encoding algorithms with a minimum software change.
Like AdcX, AdcT is designed to have a good modularity and expandability.
8
Fig. 5. User interface of the optimization module, with the histograms of the actual and
modeled ADC outputs. The input signal is a sine wave.
Fig. 6. User interface of the test module. By means of this interface the user can choose
the parameters of signal to send to the actual (a) or simulated (b) ADCs, he/she can set the
clock (c) and start the test (d).
It exchanges data with a local or remote CORBA server. Therefore, in order
to test ADCs by means of IEEE 488, or VXI instruments, it is necessary to
develop an instrumentation control module. At now, a software module for
9
(a)
(b)
Fig. 7. Histogram and FFT displays of the acquired signal.
controlling GPIB instrumentation has been developed.
The system architecture has been designed in order to set the modeling and
testing procedures independent from the specific data sources, managed by the
acquisition server. In such a way, the analysis subsystems such as AdcX and
AdcT VIs can work whichever is the effective data source: instrumentation,
models optimized by AdcX or data coming from former acquisitions. This
separation is obtained by using a common data repository, independent from
the particular acquisition and the required analysis.
The software module with the task of managing the data is called document
manager. The acquired samples are sent to the document manager that stores
them in opportune data structures. These contain also some information about
the source, such as the sampling frequency or the particular ADC. The imple-
10
mented database is scalable, in order to provide the maximum flexibility to
the specific needs of the user. The data storage is carried out in a hierarchical
way, in order to group data from several acquisitions with similar characteris-
tics (e. g. from the same ADC) and retrieve them by using the above quoted
characteristics instead of an arbitrary file name. An additional feature of the
designed document manager is the possibility of using pre-processing modules
such as a Fourier Transform one, that, starting from time domain data, can
calculate their amplitude spectrum.
A web-based graphical user interface could enable the members of the research
group in remotely accessing, downloading or analyzing the acquired data by
means of the proposed modules.
5 Experimental validation
Fig. 8. Test bench used to validate the system.
The proposed distributed test system has been implemented and experimen-
tally validated by setting up the test bench reported in Fig.8 and testing the
AD773 ADC from Analog Devices, a three stage pipelined converter with a 10
bit resolution. The ADC has been stimulated with sinusoidal filtered signals
at different amplitudes, in order to involve a new pipeline stage at each step.
The input signal has been generated by using an Agilent 8904A multifunction
11
synthesizer, while the output has been retrieved from an Agilent HP16500C
Logic Analysis System, equipped with a 16517A/18A and a 16554A Logic
Analyzers, connected to a PC through a GPIB interface. For the purposes of
this first experimentation, only the spectral matching approach has been used,
but a histogram matching approach could be followed as well. A multiple step
process has been adopted to set the optimal parameter values by applying the
above quoted modeling identification method to each stage of the ADC from
the first to the last one.
An improvement index QI has been defined as follows:
QI =f(p0
)− f
(p)
f(p0
) × 100 (4)
where p0 is the starting point (ideal model), p is the current point in the
parameter space and f (·) is the target function, defined as the error between
the actual ADC output spectrum and the model one, limiting the evaluation
to the higher 50 harmonics (Fig.9). By using the modified Aitken algorithm
Fig. 9. Output spectra of the second stage of the real and modelled ADC.
and the AD773 model the starting models have been improved by 21% on
the first stage setting, by 25% on the second stage setting, and by 64% on
the third stage, corresponding to an overall improvement by 20% on the ADC
12
model, from the spectral point of view. Note that the equation (4) gives a
QI value of 0% at the starting point (no match) and a QI = 100% if the
model output perfectly matches the actual device one. The first test results
highlight the fitting of the proposed tools to the research on the pipelined
ADC harmonic distortion characteristics. Further experiments will be carried
out by considering the statistical properties of the model. Moreover, as the
model identification results are strictly dependent on the chosen algorithm, a
research aiming to find the best fitting minimization algorithm will be carried
out by adding new modules to the AdcX VI.
6 Conclusion
The paper presented a distributed testing and modeling system for pipelined
ADCs composed of four modules. An identification instrument working on
the simplified behavioral model of a pipelined ADC and on the samples of
an actual device has been proposed in the paper. Moreover, a tool for the
ADC testing has been realized and described. Currently the AdcX module
applies the Aitken optimization to the ADC outputs in the frequency domain.
However, both modules have been realized with a modular structure that al-
lows an easy expandability with the addition of more optimization algorithms
or testing procedures. Additional modules are currently being developed in
that direction. An instrumentation control module has been developed too.
Its function is to realize an abstraction layer for the involved instrumentation
and to communicate with the instruments through standard interface sys-
tems like GPIB. All the data involved in the tests are stored and shared in a
common repository, controlled by a suitable document manager. The module
13
implementation in Java language with the use of CORBA architecture allows
their remote control through a common browser without requiring the use of
proprietary software or complex setup procedures. This feature enables the
collaboration of geographically distributed research groups on the themes of
ADC modeling and testing.
Acknowledgment
The authors whish to thank Prof. P. Daponte for his support and useful sug-
gestions during the research work.
References
[1] S. Rapuano, P. Daponte, E. Balestrieri, L. D. Vito, S. J. Tilden, S. Max, J. Blair,
Adc parameters and characteristics, IEEE Instrumentation and Measurement
Magazine 8 (5) (2005) 44–54.
[2] Maxim application note AN634, Pipeline ADCs come of age (2000).
[3] IEEE TC-10, IEEE 1241 Standard: Terminology and test methods for analog-
to-digital converters, IEEE (2001).
[4] P. Real, D. H. Robertson, C. W. Mangelsdorf, T. L. Tewksbury, A wideband
10-b 20-ms/s pipelined ADC using current-mode signals, IEEE Journal on Solid-
State Circuits 26 (8) (1991) 1103–1109.
[5] D. F. Hoeshele, Analog-to-digital and digital-to-analog conversion techniques,
John Wiley and Sons, 1984.
14
[6] L. Michaeli, J.Saliga, V.Sedlak, An approach to diagnostic of the A/D converter
embedded on ATMEL microcontrollers, in: Proc. of 4th International Workshop
on ADC Modeling and Testing, 1999, pp. 247–252.
[7] Analog Devices, Norwood, MA, U.S.A, AD773 Datasheet.
[8] W. T. Vetterling, W. H. Press, S. A. Teukolsky, Numerical Recipes in C. The
Art of Scientific Computing, 2nd Edition, Cambridge University Press, 1997.
[9] W. Gomez, J. A. Gomez, On multi-directional search in optimisation (1995).
URL http://citeseer.nj.nec.com/gomez95multidirectional.html
[10] P. Arpaia, F. Cennamo, P. Daponte, Metrological characterisation of analog-
to-digital converters - a state of the art, in: Proc. of 3rd IEE Int. Conf. on
Advanced A/D and D/A Conversion Techniques and their Applications, 1999,
pp. 134–144.
[11] D. Dallet, Contribution a la caracterisation des convertisseurs analogiques–
numeriques : evaluation des methodes et mise en oeuvre de nouveaux procedes,
Ph.D. thesis, Universite de Bordeaux 1 (1995).
[12] N. J.E.Dennis, Algorithms for bilevel optimisation, Tech. Rep. TR-94474,
Center for research on parallel computation, Houston, TX, USA (1994).
URL http://www.crpc.rice.edu/CRPC/softlib/TRsonline.html
[13] Analog Devices, Norwood, MA, U.S.A, AD872 Datasheet (1997).
URL http:
//www.analog.com/UploadedFiles/DataSheets/233336251AD872Aa.pdf
[14] P. Arpaia, P. Daponte, Y. D. Sergeyev, A-priori statistical parameter design
of adcs by a global optimisation algorithm with local tuning, in: Proc. of 4th
International Workshop on ADC Modeling and Testing, 1999, pp. 236–244.
15