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NAVAL POSTGRADUATE SCHOOLMonterey, CaliforniaAD-A267 433III ~ ~ C!1 SlllUll~~DTICSELECTEAUG 0 199311rRA~`A

THESISFOUR FREQUENCY-SHIFT KEYING (4-FSK)

SPREAD SPECTRUM MODULATOR AND DEMODULATORby

Terrence J. MurrayMarch, 1993

Thesis Advisor: Tri T. Ha

Approved for public release; distribution is unlimited.

93-17365

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Classification of this pageREPORT DOCUMENTATION PAGE

la Report Security Classification: Unclassified lb Restrictive MarkingsZa Security Classification Authority 3 DistributtotuAvadLabilit of Report"hDeclassitication, Do%%ngrading Schedule Approved for public release: distribution is unlimited.4 Pertrminc Organization Report Numberisi 5 Monitoring Organization Report Numberis)ba Name ,t Performing Oreanization 6b Office Symbol 'a Name of Monitoring OrganizationNaval Postgraduate School (if applicable) EC Naval Postgraduate SchoolCc Add'ress tin. itate. an, ZIP -ode,' 7b Address witv', state, and ZIP ,'ode,.lonterey CA 93943-5000 Monterey CA 93943-5000Sa Name .t FundingSponsoring Organization 6b Offce Symbol 9 Procurement Instrument Identification Number

ff(fifpplicableAddress win. ,tate. and ZIP code) 10 Source of Funding Numbers

Program Element No IProject No I.Task N. iWork Liii A oessiII Title unclvde .eciarir cla'hsiticationi FOUR FREQUENCY SHIFT KEYING (4-FSK) SPREAD SPECTRUM MODULATOR AN DDEMODULATOR12 Personal Authorysi Terrence J. Murray

13 ~p .rRpot13b Time Covered 14 Date ot Report Lxear, monith. dayw 5Pc C,.unt 101Master's Thesis From 07/90 To 03,93 March 199316 Supplementary Notation TIle views expressed in this thesis are those or the author and do not reflect the official policy or positionof the Department of Defense or the U.S. Government.17 Cosati Codes 18 Subject Terms Wvontinue on reierse zt! ecessarv and idennrYv bt hlo, ,zonreriField Group := Subgroup19 ,A/stract

This thesis explores the potential use of a four frequency-shift keying 4-FSK), spread spectrum modulator and demodulator(MODEM) in a low orbit satellite. In this first approach a short maximal length sequence of 127 chips would be used to spread thefour frequencies. After successful implementation. the design could be extended to longer codes which would provide for greaterprocessing gain. This MODEM was not preselected for use in satellite communications based on the merits of 4-FSK. but wasassigned as one of four possible digital communication designs. A MODEM would be selected for use in the Petite Amateur Na%Satellite after a thorough design review.

'0 DistributionAvailability .f Abstract 21 Abstract Security Classification_X unclassified/unlimited __ same as report __ DTIC users Unclassified,.a Name it Responsible Individual 22b Telephone (include Area Code, [22c Office SymbolE T. Ha (408) 656-2352 EC/Ab

FORM 1473.84 MA R 83 AP R edition may be used until exhausted securtt" ciassification ot itr, Pa"All other editions are obsolete Unclassifie

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Approved for public release; distribution is unlimited.

FOUR FREQUENCY-SHIFT KEYING (4-FSK)SPREAD SPECTRUM MODULATOR AND DEMODULATOR

by

Terrence J. MurrayLieutenant Commander. United States Navy

B.S.. Northern Arizona University, 1977

Submitted in partial fulfillmentof the requirements for the degree of

MASTER OF SCIENCE IN ELECTRICAL ENGINEERINGfrom the

NAVAL POSTGRADUATE SCHOOLMarch. 1993

Author: . ---- / . . ,Terrence J. MurrayApproved by: -T,>':6

Tn T Ha. Thesis Advisor

Rudolf Panholzer. Secoq Reader

Michael A. MorganChairmanDepartment of Electrical and Computer Engineering

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ABSTRACT

This thesis explores the potential use of a four frequency-shift keying (4-FSK),spread spectrum modulator and demodulator (MODEM) in a low orbit satellite. In thisfirst approach a short maximal length sequence of 127 chips would be used to spread thefour frequencies. After successful implementation, the design could be extended to longercodes which would provide fo r greater processing gain. This MODEM was notpreselected fo r use in satellite communications based on the merits of 4-FSK. but wasassigned as one of four possible digital communication designs. A MODEM would beselected fo r use in the Petite Amateur Navy Satellite after a thorough design review.

A~cce~jOn For .LNTS CP&

..d ;,'Ou: %~d

DiA btoB......................v / cr

D]! S1ec.a1

DTIC QUAIJ2TT EDp 3

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TABLE OF CONTENTS

I. INTRODUCTION . . . . . . . . . . . . . . . . . . . 1

II. Design Theory .................. ................... 3A. 4-FSK SPREAD SPECTRUM MODULATION ..... ....... 3

1. General ................. .................. 32. Serial-to-Parallel Data Conversion Module 43. Sine Wave Generator Module ....... ........ 64. Spread Spectrum Module ... .......... .. 12

B. 4-FSK Spread Spectrum Demodulation ...... .. 141. General ........... .................. 142. Band Pass Filter Module ... .......... .. 153. Decision Making Module .... ........... .. 164. Frequency Sweep Module .... ........... .. 215. Early Minus Late ........ .............. .. 236. Track ............. ................... .. 297. Demodulator Synchronization .. ........ .. 32

III. CIRCUIT CONSTRUCTION ....... .............. .. 36A. 4-FSK SPREAD SPECTRUM MODULATION .. ....... .. 36

1. Serial-to-Parallel Data Conversion Module 362. Sine Wave Generation Module .. ........ .. 363. Spread Spectrum Module .... ........... .. 37

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B. 4-FSK SPREAD SPECTRUM DEMODULATION .. ...... 381. Fourth Order Band Pass Filter Module . . .. 382. Decision Making Module .... ........... 393. Frequency Sweep Module .... ........... 394. Early Minus Late Module ... .......... 405. Track ............... ................... 416. Demodulator Synchronization .. ........ 41

IV. EXPERIMENTAL RESULTS ........ ............... 42A. 4-FSK SPREAD SPECTRUM MODULATION .. ....... 42

1. General ............. .................. 422. Serial-to-Parallel Data Conversion and

Precision Sine Wave Generator Module . . .. 423. Spread Spectrum Module .... ........... .. 43

B. 4-FSK SPREAD SPECTRUM DEMODULATION .. ...... 461. General ............. .................. 462. Band Pass Filter Module ... .......... 463. Decision Making Module .... ........... .. 464. Frequency Sweep Module .... ........... 505. Early Minus Late Module ... .......... 536. Track ............... ................... 577. Demodulator Synchronization .. ........ 578. Probability of Bit Error .... .......... 60

V. RECOMMENDED DESIGN MODIFICATIONS ... ......... 62A. 4-FSK SPREAD SPECTRUM MODULATION .. ....... 62

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B. 4-FSK SPREAD SPECTRUM DEMODULATION .. ...... 62

APPENDIX A: CIRCUIT SCHEMATICS ....... ............ 65

APPENDIX B: GENERALIZED IMPEDANCE CONVERTER (GIC) FILTERDESIGN ................. ...................... 75

APPENDIX C: BUFFERS ............ .................. 82

APPENDIX D: DOPPLER SHIFT ........ ............... 84

APPENDIX E: COMPUTER PROGRAMS ...... ............. 88

LIST OF REFERENCES ............. .................. 93

INITIAL DISTRIBUTION LIST ........ ............... 94

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I. INTRODUCTION

The Petite Amateur Navy Satellite (PANSAT) concept callsLor a low earth orbit satellite which provides digital, spreadspectrum, store-and-forward, packet radio communication.PANSAT was originated by Professor Rudy Panholzer at the NavalPostgraduate School to provide the school's graduate studentswith an opportunity to apply classroom theory to a "realworld" engineering project. To extend this opportunity toseveral communication graduate students, it was proposed thatfour modulators/demodulators (MODEMS) would be designed asindependent thesis projects. The four MODEMS proposed are:binary phase-shift keying (BPSK), quadrature phase-shiftkeying (QPSK), differential phase-shift keying (DPSK), andfour frequency-shift keying (4-FSK).

The objective of this thesis is to design, build, and testa 4-FSK spread spectrum MODEM which could possibly beinstalled in PANSAT. The following initial parameters wereprovided as guidance in formulating the design:

1. noncoherent 4-FSK MODEM2. spread spectrum using a maximal length spreadingsequence (m-sequence) of 1273. each data bit would be spread by one complete m-sequence4. data bit spread would commence at the start of a chip(no single chip would span any two bit periods)

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5. data bit rate equal to 1200 bits per second6. spread spectrum channel bandwidth not to exceed 900 kH z7. low power using CMOS technology8. low orbit equal to 400 nautical miles

A design review would be held to determine which of thecompleted designs best meets the PANSAT requirements for size,weight, power consumption, cost, complexity (ability toduplicate the prototype), bandwidth and bit error rate.

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II. Design Theory

A. 4-FSK SPREAD SPECTRUM MODULATION1. General

The diagram of Figure 1 shows the Modulator Groupconsisting of the following three modules:

1. Serial-to-Parallel Conversion (MV)2. Sine Wave Generation (M2)3. Spread Spectrum (M3)

The theory considered during the design of each of thesemodules is discussed under separate sub-paragraphs of thischapte-. A basic understanding of electronic circuit and

M2Sine WaveGenerator

1 1`2 t3 A

Dato Parallel 4-r3K SpreaoConverter SpectrumSoectrum Siqnal

Clock T

Figure 1: Modulator Group

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spread spectrum theory is assumed. References 1, 2, and 3should be reviewed for additional information concerningdigital, analog, and spread spectrum engineering designrespectively.

2. Serial-to-Parallel Data Conversion ModuleBefore the modulator's serial-to-parallel converter

can be designed, consideration must be given to the method bywhich the demodulator will synchronize with the receivedsignal. As a result of spread spectrum modulation, thedemodulator must synchronize with the spreacing m-sequenceprior to data transmission. Because of this, the m-sequencewas inspected for possible use in data synchronization. Thedigital logic sequence fo r a seven stage shift register withtaps at stage three and seven is written out in Figure 2. FromFigure 2 it was recognized that any successive grouping of

1 1. : 0 0 0 1 O)D0 1 1 1 0 1 0 1 : 3 3 C 1 0 1 0 1 0 1 1 )'AI 0 1 0 0 1 0 0 0 0 i

1 C 0 0 1 1 0 1 0 1 0 0 (1 1 0 0 1 1 1 1 )E 1) 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 i 0 1 i

;1 0 1 (1 1 1 2 1),0 1 1I,0 1 1 0 0 1 0 1 1 0 3

C o0 0 0 0 1 1 1 1) 0 0 0 0 0 0 0

Figure 2. M-sequence, N = 127, taps at stage 3 and 74

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seven chips from the total set of 127 chips was unique (notrepeated) . The serial-to-parallel converter module of DrawingA-! utilizes eight chip m-sequence code bytes for datasynchronization. By clearing the m-sequence shift register atthe start of data transmission a reference would beestablished for clocking in serial data and clocking out aparallel symbol (two bits). From Figure 2 subscripted groupsA and B are used to clock serial data into the serialinput/parallel output shift register by clocking d~ta in themiddle of each serial data bit period. Subscripted group Clatches a pair of bits into the decoder short2y after thesecond bit of the two bit pair is clocked into the shiftregister. Within 0.5As a radio frequency (RF) pulserepresenting the bit pair which was latched into the decoderis switched to the output of the demodulator. Forsynchronization purposes at the demodulator, subscripted groupC will signal the start of an RF pulse. The analog switch isa guaranteed "break before make" switch which results in onlyone of the four radio frequencies on the output line at anygiven time. All digital logic circuit set-up times wereachieved by maintaining at least a one chip time intervalbetween bit transfers.

To ensure that incoming data is synchronized to theshift register and decoder clocks two additional subscriptedgroups D and E should be created as outputs from the serial-to-parallel converter. These two pulses would be used to clock

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the external data device thus ensuring that the serial inputdata is latched in the middle of the data period. Advantagesto using the m-sequence to control synchronization are:

1. Deletes the requirement that the m-sequence shiftregister be cleared at the start of data transmission.This would eliminate a critical timing consideration andeliminate the potential fo r drift between twoasynchronous timing waveforms.2. Any chip rate can be selected.3. The data rate will always be dependent on the chip rate.4. Each data bit will always be sub-divided by one completechip sequence.5. The start of each RF pulse is known.6. Each RF pulse can be further sub-divided into 127 equalparts.

3. Sine Wave Generator ModuleThe FSK signal can be generated in one of two ways as

indicated in Figure 3. Either using a separate oscillator foreach frequency and switching on the desired frequency or usinga frequency modulator (voltage controlled oscillator) which iscapable of producing multiple frequencies. With only fourfrequencies required to implement a 4-FSK modulator it isviable to build four separate sine wave generators or a singlevoltage controlled oscillator (VCO). In the case of higherorder FSK modulators (16 or greater), it would be impracticalto build 16 or more separate oscillators in which case a VCOwould be a better choice. This design uses four separate

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FIlc ro'u1 "]Os. ii! orFreq.=

, i Im FSK

Freq I u.L..

Binjrs da., p,, rM' I /"

DiN.w n uluo Phase FSK

Bmjijinit Frequen~y",,I t I modulator FSK(arrie'r Iretl = 1C) - u

lb IContmoous-Phase FSKFigure 3. Generation of FSK (Ref. 4:p. 337]

precision sine wave generators which allows fo r precisefrequency, maximum reduction of harmonfc distortion, andsecond order low pass filters to significantly attenuateharmonics. A single VCO does not allow fo r this much controlover the sine wave shape and would require additional switchesto route each frequency as it is selected to the appropriatelow pass filter.

For 4-FSK, four frequencies must be determined. Theprecision sine wave generator module of Drawing A-2 is limitedto approximately 350 khz and active filter design is limitedto approximately 500 khz. If square law detection was usedthen the lowest probability of bit error would result if andonly if the frequencies were mutually orthogonal. This means

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that the change in one frequency to another is an integermultiple of the bit rate (Rb).

Af = -L- nRb n = 1,2,3,Tb

The bit rate of the data is 1200 bits per second but in 4-FSKmodulation this is reduced to a symbol rate (Rs) of 600symbols per second.

A f nRT,

In this spread spectrum modulation scheme, each symbol is sub-divided by the length of one entire m-sequence which fo r thisdesign is equal to 127 chips.

Af - n2 - 127nR ,T"/127

Using the requirement for mutually orthogonal sinusoids, Rs =600, and n = 1, 2, 3, and 4, the four frequencies are:fl = 76.2 khz, f2 = 152.4 khz, f3 = 228.6 khz, and f4 = 304.8khz.

Square law detection only works if the channelfrequencies are constant values. An orbiting satellite whoseposition changes with time in relation to a site on earthcreates a doppler shift which causes the channel frequenciesto continually vary. Due to varying channel frequencies, thedemodulator was designed using envelope detectors. Envelopedetectors do not require that the FSK frequencies be mutuallyorthogonal, but that they are far enough apart in the

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frequency domain so that one frequency does not get mistakenfor another. Since 4-FSK is simply a series of independent RFpulses, frequency separation can be determined by viewing thefrequency domain of a single RF pulse, g(t).

g(t) = P rect(t) cos(2-nfft)T

Figure 4 is the time domain plot of the RF pulse. The FourierTransform of g(t) is G(f).

G(f) - PT(sinc[T(f-fc)I + sinc[T(f +fC)])2Figure 5 is the frequency domain magnitude plot of G(f). Notefrom Figure 5 that the RF pulse has a main lobe bandwidthequal to twice the inverse of the RF pulse period CT). For aspread spectrum signal, the RF pulse phase is no longerconstant but is changed according to the m-sequence. When theRF pulse period (T) is segmented into 127 parts (number ofchips in the m-sequence) , the resultant RF pulse period isreduced to a new, shortened period, called the chip period(To) . Substituting Tc for T in Figure 5 results in thefrequency spectrum magnitude plot of Figure 6. The bandwidthis still equal to twice the inverse of the RF pulse period.Only now the pulse period is the shorter chip period (Tc), andthe bandwidth is widened in proportion to the length of the m-sequence.

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g t

TFigure 4: RF Pulse in the Time Domain (Ref. 5:p. 37]

A minimum channel frequency separation for a spread spectrum

,ITT - -

I -.f- 4 f ,equency

Figure 5: RF Pulse in the Frequency Domain (Ref. 6:p. 3351

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r - T

Figure 6: Spread Spectrum RF Pulse in the Frequency Domain(Ref. 6:p. 335]2 2

Spread Spectrum BW - 2 -72 152.4 kHzT~ T/12-7

demodulator which uses envelope detectors is one half thespread main lobe bandwidth or 76.2 khz. The modulatorfrequencies of 76.2 khz, 152.4 khz, 228.6 khz, and 304.8 khzwere selected. These frequencies are within the range of thesine wave generators, can be shaped with active filters, andmeet the minimum separation requirements.

The low pass filters are 2nd order GIC filters. Allactive filters used in both the modulator and demodulator areGIC filters and are covered as a separate topic in Appendix B.

All buffers used in both the modulator and demodulatorwere constructed using LM318 operational amplifiers because ofthe component's high slew rate (70 V/As) and wide bandwidth(15 Mhz). These are covered as a separate topic in Appendix C.

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4. Spread Spectrum ModuleThe spread spectrum module, M3, of Drawing A-3 is

comprised of a code sequence generator, a doubly balancedmixer, and a buffer. Using Table 8-5 of [Ref. 6:pp. 390-3911,the generator polynomial fo r an m-sequence of length 127 isg(D) = 1 + D3 + D7 . The powers of the generator polynomialdetermine the final form of the General Multiple-Tap SimpleSequence Generator (SSRG) of Figure 7. The SSRG circuit isimplemented by connecting the third (D3 ) and seventh (D7 ) stageoutputs of an eight stage shift register to an exclusive-norgate and back to the shift register's first stage data input.The sequence can be tapped off of any of the shift register'seight outputs (Q1 through Q8). An eight input nand gateprevents the generator from locking-up with all ones (high

M1 M M3

I I

Figure 7. Multiple-tap simple sequence generator (SSRG)[Ref. 3:p. 681

digital value equal to a nominal plus five volts). If atstart-up or due to noise all of the outputs are one, the

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output of the nand gate will be zero (low digital value equalto a nominal zero volts) and will clear the shift register toall zeros and re-start the m-sequence. In order to introducephase changes and not imbalance the amplitude of the outputsinusoid, the spreading m-sequence must alternate betweenpositive and negative voltages of equal amplitude rather thanthe nominal zero to five volt digital logic output of theshift register. This is accomplished by connecting the outputof the shift register to a comparator whose reference voltageis set at a mid-point value between zero and five volts. Thecomparator voltage supplies are adjusted so that the outputvoltage swings between positive and negative values of equalamplitude (A). Hence as the digital logic m-sequence changeslogic levels, the comparator output voltage changes betweenA.

The doubly balanced mixer (DBM) multiplies the twoinputs. The output is one of the four symbol frequencies butinstead of being at a constant phase during its pulse durationits phase now varies with the change of phase of the m-sequence. This has the effect on the amplitude and bandwidthof the frequency domain signal as shown in Figure 6. Theamplitude is reduced and the bandwidth is increasedproportional to the length of the m-sequence.

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B. 4-FSK Spread Spectrum Demodulation1. General

The diagram of figure 8 shows the 4-FSK demodulationgrouped into the following six modules:

1. Band Pass Filter (M4)2. Decision Making (M5)3. Frequency Sweep (M6)4. Early Minus Late (M7)5. Track (M8)6. Synchronization (M9)

'A.8

S'ea-e,'cv

Figure 8. Demodulator Group

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Module M5 with some additional synchronization circuitry isthe only module required if spread spectrum had not beenemployed. The other three modules are all involved inacquiring/tracking the m-sequence used to despread thereceived signal and provide synchronization to the decisionmaking module.

2. Band Pass Filter ModuleIdentical sets of band pass filters are used in the

decision making circuitry prior to envelope detection and inthe early minus late acquisition circuitry. These applicationswill be discussed separately. This section covers band passfilter design.

The 4th order band pass filters were designed bycascading two Generalized Impedance Converter (GIC) secondorder active filter networks. The center frequency for each ofthe band pass filters is equal to the channel frequency asdetermined in paragraph II.A.3. To find the upper and lower3dB frequencies, the frequency shift from the centerfrequencies due to worst case doppler shift and the main lobebandwidth of the despread channel frequencies must first becalculated. The worst case doppler shift as calculated inAppendix D is 9784 Hz. Adding one-half the channel bandwidthto the maximum doppler shift frequency results in 10,384 Hz asthe amount that must be added and subtracted from each of thecenter frequencies to calculate the upper and lower 3dB

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frequencies respectively. The design criteria fo r each of thefour band pass filters is listed below:

Q center freq(Hz) lower 3d B freq(Hz) upper 3dB freq(Hz)3.67 76,200 65,816 86,5847.38 152,400 142,016 162,78411.00 228,600 218,216 238,98414.68 304,800 294,416 315,184

Each band pass filter was designed using the procedure inAppendix B. Magnitude plots of the band pass filters using thepassive elements of Drawing A-4 are shown in Figures 9 through12 for channel frequencies 76.2kHz through 304.8kHzrespectively.

3. Decision Making ModuleAs previously discussed in paragraph II.A.3.,

demodulation would be accomplished using envelope detectors.The block diagram of a two channel noncoherent FSK demodulatoris shown in Figure 13. Any higher order m-ary FSK demodulatorcan be designed by duplicating the building blocks of Figure13 once fo r each additional pair of transmission channels. The4-YSK decision making module comprised of filters, amplifiers,envelope detectors, integrators, and decision making circuitryis shown in Drawing A-5.

The gain of the amplifiers at the output of the bandpass filters was determined on the constructed circuit byinserting each of the four channel frequencies (all of two

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-5- 7'

-25La 'a '2

-REQ -Z

Figure 9. 4th Order BPF, f0= 76.2 kHz, Q=3.66

-20'

--2 5 -- . . .

1 12 1.3 14 15 is 17 '8 2P8CQ -Z

Figure 10. 4th Order BPF, fo = 152.4 kHz, Q = 7.50

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S9s2 2 22 2 3 2d l 2 5 2 a 2- .oM -Z

Figure 11. 4th Order BPF, fo = 228.6 kHz, Q = 7.75

-25

2. 2 6 26 2 28 2 9 3 3 ' 32 33"w"ea-Z 'c

Figure 12. 4TH Order BPF, fo = 304.8 kHz, Q = 15.0

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Upper chlnnel (mark)r- - -1Bandpass filter (I)to entered atf I Envelopc tL

BI,= eifcctivc bandwidth) I detecto

Bandpass ftltarA

centered Jt f2 Envelope output(BP = ettctive bandwidth) detector L )L

"-Lewer haonel Ispace)

Figure 13. Noncoherent detection of FSK (Ref. 4:p. 543]

volts peak-to-peak) into their respective band pass filtersand calculating th e gain required to have a 12 volt peak-to-peak signal out of each of the amplifiers. This was done sothat each transmitted channel when received by the envelopedetector has equal weight in the decision making process.

The design of the envelope detectors was taken from[Ref. 5:pp. 272-273] but unlike envelope detectors foramplitude demodulation, the charging and discharging timeconstant, RC, must both be relatively short compared to thesymbol duration. To keep subsequent integrations mutuallyindependent, the stored energy in the envelope detector mustbe zero prior to the start of an integration. Tiiis requiresthat the capacitor voltage approach zero before the nextintegration begins. A simple passive low pass filter with a1600 Hz cut-off frequency was placed after the envelope

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detector to remove the high frequency ripple. The integratorwas designed to ramp up in its nearly linear region during thesymbol period, be sampled at the end of the symbol periodwhere the maximum amount of signal energy could be captured,and dumped at the start of the next symbol. The integratoramplifier buffers the integrator from the comparator circuitthat follows and also amplifies the integrator voltage whichincreases the likelihood that the comparators will correctlychoose the integrator with the greatest signal energy.

A decision must be made as to which frequency is beingreceived and then decoded to its two bit symbolrepresentation. Once the bit pair is known, the pair must beseparated and emitted from the module one bit at a time justas it was fed into the modulator at the transmission site. Th edecision criteria is simple. If fl integrator voltage isgreater than f2, f3, and f4 integrator voltages when comparedon an individual basis then fl was received. When thiscomparison is made for all four possible combinations only onefrequency can be chosen as the received frequency. Given fourfrequencies, six comparators are required to implement allpossible combinations (1 and 2, 1 and 3, 1 and 4, 2 and 3, 2and 4, and 3 and 4). There are actually 12 permutations butsince the other six are inverse relationships thesecomparisons can be achieved by inverting the comparators'output. Combinations of these 12 results ar -onnected to thefour three-input nand gates where an all rt drives the

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appropriate priority encoder pin low which in turn activatesone of the four bit pairs (00, 01, 10, 11). This comparison isdone on a continuous basis and is only optimized to be correctat the end of the integration process. The synchronizationwhich determines when to accept these comparisons is discussedin the demodulator synchronization module section. The bitpair is clocked into a parallel-to-serial shift register andthen clocked out at twice the symbol rate.

4. Frequency Sweep ModuleNot knowing the exact frequency and phase of the

received m-sequence requires that the demodulator sweepthrough the range of all possible frequencies while lookingfo r the correct one. The purpose of the frequency sweep moduleis to sweep through its range of frequencies until signaled bythe early minus late module that the frequency is close enoughto the received frequency to be acquired/tracked and that thephase of the received spreading m-sequence and demodulatordespreading m-sequence match within one-half of a chip. Thisis summarized by the algorithm of Figure 14 . Initial effortsto design an analog frequency sweep were unsuccessful becauseonce the fixed analog voltage level required to drive thevoltage controlled oscillator (VCO) was determined, it couldnot be held constant. Attempts to hold the voltage on lowleakage polypropylene capacitors buffered by low input biascurrent (5OpF) JFET operational amplifiers failed due to a

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LtOS Retaul ecelvp, Yes Stollfclock oced search ode

t se.)rch

STrack

Figure 14. Flow diagram for sliding correlator acquisition(Ref. 3:p. 219]

slow discharge of the capacitors resulting in an unacceptabledrift of the JFET output voltage. To correct for theinevitable discharge of the capacitor a refresh loop wasinstalled to recharge the capacitor with the correct voltagelevel. This did not work because the operational amplifiersutilized in the refresh loop induced their own voltage driftdue to the minute offset voltages which could not becompletely removed. Therefore, the design shown in Drawing A-6was developed using digital components. The eight bit countersteps through all 256 states, one state change for everypositive-going clock pulse. The eight bits of each state arethen clocked into an eight bit latch on every negative-goingclock pulse. The one-half clock period delay assures that the25ns set-up time is met. The digital-to-analog converter (DAC)produces incremental voltages based on the digital input which

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in turn steps the VCO through the range of possiblefrequencies. This method works very well. Once the frequencysweep module is signaled to stop clocking, the latch holds thecorrect digital code indefinitely. The latched code drives aDAC whose output voltage is held constant by the use of itsow n voltage regulator. It is this well regulated voltage whichlocks in the frequency output of the VCO.

5. Early Minus LateThe concept behind the early minus late module is to

provide the frequency sweep and track modules with thefollowing information:

1. it signals when both the received m-sequence frequencyapproximately equals the demodulator m-sequence frequencyto within plus or minus 100 Hz and the two m-sequences arein-phase.2. provides feedback so that the final frequencyadjustments can be made and the two frequencies remain in-phase within plus or minus one-half of a chip.

Early refers to an m-sequence which is advanced by one-half achip in time ahead of the punctual (spreading) m-sequence andlate refers to an m-sequence which is delayed by one-half ofa chip in time behind the punctual m-sequence. Theautocorrelation function (ACF) of these two m-sequences withthe punctual m-sequence is plotted in the upper two graphs ofFigure 15 . The ACF term is used because in this context thetwo m-sequences are identical. Note that the ACF isapproximately zero (equal to -1/127) everywhere except where

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the m-sequences are within one chip of being in phase.Drawing A-7 shows the early minus late circuit. The early/latecode sequence generator is identical to the modulator's codesequence generator of Drawing A-3 except fo r the addition ofone shift register and one comparator. The shift register tapsthe digital logic m-sequence one full chip ahead of thepunctual m-sequence and then by use of an inverted clock pulseadvances the full chip early by one-half chip (early) and byone and one-half chips (late). There are now three digital m-sequences: punctual at the output of the upper (eight stage)shift register pin 4, one-half chip early at the output of thelower (four stage) shift register pin 5, and one-half chiplate at the output of the lower (four stage) shift registerpin 4. The comparators convert the early and late digital m-sequences to analog (A constant voltage amplitude) m-sequences fo r reasons explained in paragraph II.A.4. Earlyminus late refers to the difference of the one-half chip earlym-sequence autocorrelated with the punctual m-sequence and theone-half chip late m-sequence autocorrelated with the punctualm-sequence. In Figure 15 the top waveform is the early ACF,the middle waveform is the late ACF, and the bottom waveformis the early ACF minus the late ACF waveform. Using the blockdiagram of a full-time early-late noncoherent code trackingloop of Figure 16 , a two channel loop was built. A two channelloop introduces problems in trying to precisely amplitudebalance the early and late channels [Ref. 6:p. 447).

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Correlation

Correlationoutput 2

Tracking pointCompositecorrelationfunction

Figure 15. Autocorrelation Waveforms [Ref. 3:p. 254]Specifically, it was found to be most difficult to build bandpass filters with identical transfer functions. Even thoughgreat care was taken to match the values of the passiveelements, the transfer functions were not the same. Additionalwork would be required to find operational amplifiers withmatching small signal bandwidths. This was not done. Insteadit was decided that it would be easier, use fewer components,and be more accurate to use a single channel and switch theACF through one set of band pass filters thus assuring thatboth the early and late autocorrelation function productswould be acted upon by the same band pass filter transferfunction. The Tau dither early-late noncoherent code trackingloop of Figure 17 was used as a model for the modified singlechannel design of Drawing A-7. To more easily understand thecircuit, the early autocorrelation and identification process

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Dinate rawMI~~~-.:- Iu. _____

I - ate-a-7..AIW~ IF-~m:.t A fuser1

I . -w l w.611

Figure 16. Full-time early-late noncoherent code trackingloop [Ref. 6:p. 434]

---------------------- --------------

IF~at~ta~srate!

off) ;1t-1 7

*1 -t)

Figure 17. Tau-dither early-late noncoherent code trackingloop (Ref. 6:p. 448]

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will be explained; the late autocorrelation and identificationprocess is identical with the exception that theautocorrelation function (ACF) is inverted by reversing theenvelope detector diode. The doubly balanced mixer multipliesthe early analog m-sequence with the received spread spectrumsignal and via switch SW-06 routes the product (ACF) to a bankof band pass filters identical to the ones used in theconventional demodulator of Drawing A-4. When each RF pulse isspread (see Figure 6), the spectral density found within thepass band of the band pass filter is reduced. As the m-sequences begin to correlate the spectral density begins tocollapse about the RF pulse's center frequency until the twosequences are perfectly correlated. At this point in time,spectral density is at its greatest (Figure 5); therefore,there exists a direct relationship between spectral densityand m-sequence autocorrelation. The early minus late moduleuses this relationship to provide voltage feedback to thefrequency sweep and track modules. The magnitude of thespectral density of interest is found by passing the ACFthrough all four band pass filters, summing the outputwaveforms, and connecting the sum to an envelope detector.Since it is the change in magnitude in the pass band that isused as feedback, the DC offset is removed and the change inmagnitude is amplified. The early ACF and the inverted lateACF are summed together to get the output of the discriminatorof Figure 17. The modified loop filter is a lag RC filter

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designed according to Figures 18 and 19 to reduce highfrequency response. "Output signal-to-noise ratio can besignificantly improved by this simple addition, which alsodecreases loop jitter with noisy input signals." [Ref. 3:p.189] The voltage output of the loop filter is connected to thesumming amplifier in the frequency sweep module via a voltagedivider (variable resistor). Through experimentation, it wasfound that an approximately 40 mV peak-to-peak feedbackcontrol voltage locked the two m-sequences together. Largerfeedback voltages caused ex "sive jitter and lower feedbackvoltages would fail to lock the m-sequences together.

To signal the change from the acquisition mode to thetrack mode, two comparators were used to monitor the early andlate ACF voltages. As both the early and late ACF voltagesexceeded their reference voltages (plus and minus one voltrespectively), the comparator outputs would go high. Bylooking at the ACF voltage waveforms of Figure 15, the only

LduRC 11,.

R c toIUr b ei

F,cqv cv

Figure 18. Loop filter [Ref. 3:p. 189128

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Third breakpointdue to R, C,

R2 6TeBioctave0 iC2; 0 1C ,

Figure 19. Modified loop filter [Ref. 3:p. 190]

time both the early and late ACF voltages are greater thanzero is when the composite (early minus late) correlationfunction is in the linear region about the tracking point.When the and gate goes high, the counter which drives the DACand VCO freezes the current value of the byte indicating thatthe VCO is close to the received m-sequence frequency. Thefeedback control voltage is then able to make the smalladjustments necessary to maintain a lock on the received m-sequence frequency and phase. Because the spreading anddespreading m-sequence frequencies were not perfectly matched,a DC offset to the composite correlation function of Figure 15results. It is this DC offset that will be used as feedbackto track frequency drift and doppler shift.

6. TrackIf the transmitter and receiver were stationary, then

there would be a relative velocity and doppler shift equal tozero. In this instance, the early minus late feedback voltagewould provide all the necessary control to maintain

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correlation between the spreading and despreading m-sequences.The relative velocity, however, is not equal to zero. Withouta means of adjusting the average feedback voltage to zero, theDC offset would continue to increase (either negatively orpositively depending on whether the doppler shift increased ordecreased the frequency of the spreading m-sequence frequency)until it exceeded the range of feedback voltages. Two adverseevents occur as the DC offset voltage increases:

1. The m-sequences will move further out of alignmentresulting in a smaller signal-to-noise ratio and a higherbit error rate.2. Acquisition will be lost prior to successful receipt ofthe entire information packet.

To track the doppler shift, a second feedback loop is createdwhich will monitor the DC offset of the early minus latefeedback voltage and adjust the digital code which ultimatelydetermines the base frequency of the despreading m-sequence.When the frequency of the two m-sequences are equal, the DCoffset of the control voltage waveform is zero. For a spreadspectrum communication system which must correct for dopplershift, the goal is to keep the early minus late DC offset asclose to zero as possible, thus overcoming both adverseeffects of reduced signal-to-noise ratio and short acquisitiontimes.

For optimum results, the early minus late feedbackvoltage should be sent to integrate, sample, and dump

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circuitry to determine the average DC offset. The crudedesign of Drawing A-8 randomly samples the feedback voltage 30times per second and compares the sample to zero volts. Ifthe sample value is greater than zero, the comparator outputgoes low and then the byte 0000 0001 is added to the currentbyte which is driving the DAC. When the arithmetic logic unit(ALU) adds 0000 0001, it is the same as adding one bit to thecurrent byte and decreasing the despreading m-sequencefrequency. This more closely matches the two frequencieswhich reduces the DC offset. Conversely, if the sample valueis less than zero, the comparator ourput goes high and thenthe byte 1111 1111 is added to the current byte which isdriving the DAC. When the ALU adds 1111 1111, it is the sameas subtracting one bit from the current byte and increasingthe despreading m-sequence frequency. Once again, this moreclosely matches the two frequencies and reduces the DC offset.

This design could result in an incorrect adjustmentsince the lower portion of a positive DC offset waveform couldhave a negative value and vice versa. As long as thefrequency resolution is not too great, the correct adjustmentwould be made on successive samples and the DC offset would bemaintained about the ideal zero reference. The adjustmentrate should be sufficient to correct for the fastest frequencychange caused by the doppler shift. For example, if thefrequency resolution was one hertz per bit and the fastestfrequency change was 4 hertz per second, an adjustment rate of

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5 samples per second would allow the despreading m-sequencefrequency to overtake the spreading m-sequence frequency andslowly oscillate about the zero reference point. However, ifthe adjustment rate is set too fast the despreading m-sequencewill jitter, and acquisition will be lost.

7. Demodulator SynchronizationFor the decision making circuitry to provide an

optimum result, the integrator in the decision making modulemust be able to start the integration process as close to thestart of an RF pulse as possible and sample the result as nearto the end of that same RF pulse as possible. The timingwaveforms of Figure 20 relate the demodulator synchronizationsequence of events which must take place during each RF pulseperiod. The subscripted letters relate to the code sequence

Dump A BP/s B CClock _ _ _ _

E DFigure 20. Synchronization timing waveforms

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generator groups as discussed later in this section. When thedump timing waveform is high, the RC integrator is connectedto ground and all previous capacitor charge and any initialcharge due to unreliable signals is removed (transitionsbetween RF pulses must be ignored because of noise introducedduring switching). When the dump waveform goes low, theintegration process begins and continues until the start ofthe next RF pulse. At the end of the integration, comparisonsare made as to which of the four possible transmittedfrequencies contains the greatest signal energy. The resultis a parallel load of two bits into the parallel-to-serialconverter. This is accomplished by bringing both the P/Swaveform and the clock waveforms high. The LSB is immediatelyavailable as data out. The MSB is shifted out by the middleclock pulse one-half period later, resulting in data clockedout at twice the rate of the received symbols (two bits,clocked in.

Synchronization is accomplished using knowledge of them-sequence introduced in section II.A.2. The spreading m-sequence is rewritten in Figure 21 to facilitate thedemodulator synchronization discussion. Once the m-sequencesare in-phase, it is known that each pulse begins when the codesequence generator (CSG) output is subscripted group A.Subscripted group A initiates the start of the charge dump.Twenty percent of the time into the period, the dump iscompleted. Integration begins when the CSG output is

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subscripted group B. Prior to the end of the integration andin preparation fo r a parallel load, the parallel-to-serialconverter P/S pin is set high when the CSG output issubscripted group C. Three chips before the start of a newsymbol and with 80% of the RF pulse period integrated, thesymbol with the greatest signal energy is loaded into theparallel-to-serial converter shift register when the CSG codeis subscripted group D. The integration process repeatsitself, but before the next parallel load, the second bit isshifted to the data output by the clock when the CSG code issubscripted group E, thus completing one cycle.

The circuitry of Drawing A-9 accomplishes alldemodulator synchronization. The inverters and 8-input nandgates emit a logical one pulse when their specific CSG c=Je

" 1 i 0 3 0 1 0 0 1 1 1 0 i C 1 1 0 1 C 11j I 0 1 0 1 0 1 1 e)1 0 1 3 0 1 0 3 C j i3 3 0 1 1 0 1 0 i 3 0 1 1 0 0 - '-1 - ':

SIC 01 0 1 3 0 C 1 0 1 1 i C 0 1 i C 1 1- 0 1 1 1)'0 1.1 '0 1 1 3 C i 3 1 1 C C

O 31i 0 C 0 1 1 1 ::ac 0 C 0 0 0 3

Figure 21. m-sequence, N = 127, taps at stage 3 and 7

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bytes are selected. The dump and P/S timing waveforms areachieved by toggling a JK flip-flop. Initiation is notrequired because the middle clock pulse clears the flip-flops(sets the Q output to zero) on each cycle prior to beingtoggled high. Because the early minus late feedback voltagemaintains a one-half chip phase relationship between thespreading a despreading m-sequences, synchronization can neverbe further apart than one-half chip. This allows for veryaccurate synchronization with the modulated data.

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III. CIRCUIT CONSTRUCTION

A. 4-FSK SPREAD SPECTRUM MODULATION1. Serial-to-Parallel Data Conversion Module

The idea to use a shift register and decoder as thebasic building blocks fo r a serial-to-parallel (S/P) convertercame from a text on digital logic circuits. [Ref. 11 It was thedesigner's idea, however, to combine them to form the S/Pconverter of Drawing A-i. Four analog switches were requiredto pass the analog frequencies. Switch SW-06 was selectedbecause of its in-house availability and installed per itsdata sheet. The timing information (set-up and propagation)and pin-out data were found in each components data sheet. For4-FSK the size of the circuit in Drawing A-i should be reducedby substituting a 2-4 line latched input decoder for the 4-16line latched input decoder shown. The latter was used due toavailability.

2. Sine Wave Generation ModuleThe precision sine wave generator design is based on

the circuits of [Ref. 2:p. 164] and [Ref. 7:p. 12]. The AD630(doubly balanced mixer) output at pins 12,13, and 14 is a l. 8Vpeak-to-peak square wave which is fed into an integrator viaresistor R1. The integrator output at pin 6 of the LM318operational amplifier is a 1.8V peak-to-peak triangular wave

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which is fed into pin 1 of the AD639 (trigonometric functiongenerator). The AD639 output at pins 13 and 14 is a sinusoidwhose frequency and accuracy are based on the frequency andaccuracy of the triangular wave input at pin 1. "The AD639 cangenerate continuous sinewaves of very low distortion using alinear, highly symmetric triangle wave of 1.8 V amplitude."[Ref. 7:p. 6] To produce a precision sine wave, build the sine

wave generator of Drawing A-2, replace resistor R1 with a 10kQvariable resistor and adjust until the triangle wave output ofthe integrator equals the required frequency, replace resistorR2 with a 5kQ variable resistor and adjust until the sine waveoutput of the AD639 has minimum distortion as viewed on anoscilloscope and/or a spectrum analyzer, and finally replacethe variable resistors with fixed-value resistors.

The LM318 operational amplifiers in the low passfilters and buffers of Drawing A-2 must have their powersupplies capacitively bypassed and be decompensated forstability as shown in Drawing B-3 and Drawing C-1.

3. Spread Spectrum ModuleThe digital logic m-sequence generator of Drawing A-3

consisting of thE shift register, exclusive-or, and inverterwas constructed from knowledge of the generator polynomial andthe SSRG of Figure 7. This circuit also matches the 7 stage m-sequence of [Ref. 8:p. 21-12]. The comparator circuit wastaken from [Ref. 9:p. 2-54]. The variable resistors used in

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adjusting the comparator power supply voltages (and hence theupper and lower values of the comparator output) must be 10 or25 turn potentiometers to allow fo r adequate resolution tofine-tune the values of plus and minus one volt output at pin1. The one volt magnitude is not critical but the magnitudesof the upper and lower output being equal is important. Setthe reference variable resistor connected to pin 2 toapproximately 2.5 volts. The doubly balanced mixer (DBM)circuit was taken from [Ref. 10:p. 7] . For best results,minimize the offset voltage in accordance with the procedureon offset voltage nulling. [Ref. 10:p. 6] . Construct the bufferas discussed in Appendix C.B. 4-FSK SPREAD SPECTRUM DEMODULATION

1. Fourth Order Band Pass Filter ModuleAll of the LM318 operational amplifiers on the circuit

diagram of Drawing A-4 do not show bypass capacitors on thepower supplies or decompensation capacitors. These were leftoff so that a cleaner, more concise diagram could bepresented. These must be included as shown on the band passfilter of Drawing B-2 or as shown on the buffer of Drawing C-1. Place all bypass capacitors as close to the power suppliesas practical. The high frequency section of the circuit islocated between the input to the band pass filter and theoutput of the buffer. In this region keep all leads as shortas possible.

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The band pass filters were taken from [Ref. ll:pp. 18-22] with the choice of operational amplifiers made by thedesigner for their wide small signal bandwidth and high slewrate. If operational amplifiers with a different small signalbandwidth than the LM318 (small signal bandwidth equals 15MHz) are used, then the values of the passive elements must berecalculated using the procedure provided in Appendix B.

2. Decision Making ModuleConstruct the DBM as shown in Drawing A-5 and adjust

the variable resistors according to section III.A.3. tominimize the offset voltage. Install capacitors on theoperational amplifiers as indicated on the buffer of DrawingC-1. The non-inverting amplifiers, envelope detectors, lowpass filters, integrators, and comparators were designed usingguidance and/or sample circuits from [Ref. 2:p. 57], [Ref.5:p. 273], [Ref. 12:pp. 37-39], [Ref. 13 :pp. 213-234], and[Ref. 9:p. 2-54] respectively. The digital logic required tomake the comparisons and the implementation using inverters,three input nand gates, an encoder, and decoder were thedesigner's ideas. All pin positions were taken from eachcomponent's data sheet.

3. Frequency Sweep ModuleAll components in this module were constructed fromeach component's data sheet. The DAC and VCO data sheets

include these application circuits with notes. The VCO output

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is a OV to -15V square wave. Efforts to modify the circuit tooutput a positive square wave were unsuccessful. The use of acomparator was successful in creating a 0V to +5V square waveto clock the despreading m-sequence. Using an oscilloscope,adjust the 500 Q variable resistor between VCO pins 4 and 6 tobalance the square wave duty cycle. Set the comparatorreference voltage at pin 3 to -7.5V and adjust the variableresistor connected to pins 7 and 8 until the comparator squarewave output alternates between OV and +5V.

4. Early Minus Late ModuleThe early/late m-sequence generator uses the same

components and construction guidance found in paragraphIII.A.3. used to build the modulator spread spectrum modulewith the exception of the additional shift register. Theadditional shift register was the designer's idea fo r onemethod of producing an incrementally advanced and delayedversion of the punctual m-sequence. It was determined throughexperimentation that fo r the circuit of Drawing A-7, a clockrate of 4 kH z into the sampling switch produced useable earlyand late ACF signals through the band pass filters. The 10 kQvariable resistors which are summed into the pair of invertingadders must be adjusted to remove the DC offset. This shouldbe done while the two m-sequences are sliding past one another(before any feedback is sent to the frequency sweep or trackmodules). Not shown on the final inverting adder is the 10 kQ

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variable resistor connected between pins 1 and 5 to remove theoperational amplifiers DC offset. With zero volts connected toall summing inputs, adjust the variable resistor until theoutput at pin 6 is OV. Adjust the 100 kQ variable resistor atthe operational amplifier output, pin 6, until the feedbackvoltage is 40 mV peak-to-peak. After the m-sequences locktogether, increase the feedback voltage until the despreadingm-sequence starts to jitter then reduce the voltage until thejitter stops. Adjust the comparator variable resistors to 2V.It is important that these reference voltages be greater thanthe maximum noise level and less than the correlated early andlate minimum voltages (inputs to comparator pins 2 and 3respectively).

5. TrackThe or gates were included *as a buffer between the

analog comparator and the digital latch. There are noadjustments required in this module.

6. Demodulator SynchronizationThe eight input nand gates available to the designer

did not have a non-inverting (and) output as shown in DrawingA-9; therefore, the inverters at the nand output were requiredto produce the desired eight input nand gate. The JK flip-flops were designed to toggle using the data sheet truthtable. There are no adjustments required in this module.

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IV. EXPERIMENTAL RESULTS

A. 4-FSK SPREAD SPECTRUM MODULATION1. General

Unless otherwise advised all of the figures in th eexperimental results chapter were plotted using a Hewlett-Packard 54510A Digitizing Oscilloscope with Think Jet Printer.Axis scales have been left out but were included in thecaptions in time per division and volts per divisionrespectively.

2. Serial-to-Parallel Data Conversion and Precision SineWave Generator ModuleThe serial-to-parallel (S/P) converter was first

tested manually by clocking the four possible datacombinations of zeros and ones into the data input and thenverifying that the correct frequency was output to the spreadspectrum module. The bit pairs of 00, 10 , 01, and 11 correctlyproduced the output frequencies of 76.2, 152.4, 228.6, and304.8 kH z respectively. A maximal-length sequence generator of15 chips was built to supply a repetitive, continuous stringof data for follow-on tests. In Figure 22, the bottom waveformis the digital m-sequence (length of 15). One entire sequenceand part of a second is shown. The top waveform is the outputfrom the S/P converter module. After each pair of bits is

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/ .j !*i'jk'\\ . . ,i !*............... ..........

......... *I I

..... ........ ......... . ... .- ... .. . . .. .... . ..... .. ...

...... .... ....... ..... . . ..... . .. . _ ..........

Figure 22. Bottom: Data in, 2.Oms, 1V; Top: Frequenciesout, 2.Oms, 1Vgrouped together, the decoder selects the appropriate switcQ>and outputs the appropriate frequency. Notice the phasechanges which signal the start of the next RF pulse. This wasexpected since the S/P converter was designed to bediscontinuous-phase FSK (see Figure 3).

3. Spread Spectrum ModuleThe bottom waveform, of Figure 23 is a portion of a

76.2kHz RF pulse prior to being mixed w~ith the spreading m-sequence (input to the DBM). The top waveform is the sameportion only after being mixed with the rn-sequence. For each180 degree phase change in the in-sequence, a corresponding 180

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..... .... ..... .... .... ........ ..... ... . .... . i . .... ..... .... .......................... ..... .... ..... .... .... ..... .... ..... .... ...........~.. .. .. ........................................ .I I.......-.. . . . . .. . . . .. . . . .

. '. . ... ... ..... . ... .... . ... .... ... . .. .- .. . . .

II 3 I'1 I" f : '

. . .... . . I... . . ......................-. -........ . .. ... ............. ...................... ...... ....... ...................sp e d n m s qu nc , 20 0js 1V ; ..... pulse... a...........

i i I i 1I c i n h ig i

I I I 1 l I g " i iI I I % / ! / 'spre -adin r.n-sequencet.2 .O:-s , .,._ Top: RF... pulse. at.__r.

section A.3., the shortened RF pulse period causes the signalbandwidth to increase. Figures 24 and 25 show the 1200 bit persecond, 4-FSK, signal spectral density before and after beingspread by the rn-sequence (as seen on a Hewlett Packard 8567ASpectrum Analyzer). As expected the bandwidth has widened andthe amplitude decreased. It was difficult to measure thespread spectrum bandwidth due to th e proximity of the 4-FSKsignals.

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RE F 25 . e !em -E -SN.Z0ca.0 9 "

.

I, I

1 I I, .'\\\ , I -.

START a S-CP 400 kzOESw 1fkz VOW I kdz S'P :2 meac

Figure 24. 4-FSK prior to being spread

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B. 4-FSK SPREAD SPECTRUM DEMODULATION1. General

Testing was accomplished only after the demodulatorwas independently able to acquire and track the 4-FSK, spreadspectrum, modulated signal. All figures with correlatedwaveforms are a result of this acquisition and track. The onlyconnection between the modulator and demodulator is zhechannel (hard wired).

2. Band Pass Filter ModuleThree of the band pass filters performed as designed.

The band pass filter which was designed to have a centerfrequency of 228.6 kH z was actually centered at approximately250 kHz. This filter was redesigned with passive elementswhich moved the center frequency down to the desired location.

3. Decision Making ModuleFrom the input to the band pass filters to the ouzpu:

of the integrator amplifiers, there are four similar circu::s.To reduce the number of repetitive statements and shortenexplanation of this module, a portion of a single RF pulsewill be followed through th e to p branch in Drawing A-5 .--bottom waveform of Figure 26 is the received snread spectrumsignal from the modulator. After being mixed with theuncorrelated m-sequence, additional phase changes are added bythe despreading m-sequence (top waveform) causing thebandwidth to be further increased. The waveform at the bottcm

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K/k..I IAI - -- :. .. . m1-|| i i i

SIL

~~~~.. . . . .1 .Figure 26. Bottom: Received signal, 20As, IV; Top:Uncorrelated received signal, 20As, IV

of Figure 27 is again the received signal only no w the tcopwaveform is of the correlated signal. For each phase change inthe received signal, there is now a second phase change tocancel the first. Notice that the second phase changecancellation does not occur at the same position as the first.This is a result of the m-sequences being slightly out ofphase. This is to be expected since the m-sequences willoscillate about the zero phase point. For a final comparisonin Figure 28, the bottom waveform is the RF pulse prior tobeing spread by the modulator, and the top waveform is the RFpulse after the demodulator despreads the received spreadspectrum signal. As can be seen in Figure 28, spreading anddespreading are inverse operations. Because the operations

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* ,-I\i-jI -

* II Iit I~l, I f . . . 3 I.l/ !fAIflt I W.M .- . ~..... . .. I

L_.2".__'_vi~L ..., _.. L . :_ ............. ................_ ..... E ,.Lv,.. .VIA i T i............... ..... ' ........ ....... '..... . 7;.......;; ............... ,, ic ..............., .... ...................................,. .........,.......... ..............................

_ ' ~ u . u ! L i

Figure 27. Bottom: Received signal, 2 0s, IV; Top:Correlated received signal, 20ps, IV

3P Aal.......... ...,,. /..

.. . ., ... .k... ... . . . ...I .. .. x l i , .. ..r ... ............ .. ...... .-. .

S, i , . , , , . Is,s. ., . .. .1 . . . .. . .. ... I..

I"13".1I.. . .":i I I , T I 1 I |,

. "' i , : 'tv

Figure 28. Bottom: RF pulse prior to being spread, 2Ops,IV; Top: RF pulse after being despread, 20As, lV

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occur at the output of the demodulator and the input of t._demodulator, the operations are transparent to the rest of thecircuit. The bottom waveform oi Figure 29 is the unccrrelatedinput to the bank of band pass filters. From the top waveform,the magnitude of the uncorrelated RF pulse is no longerconstant but varies pseudorandomly as the m-sequencs move inand out of phase. By contrast in Figure 30 the output

AIri~ l '< I' V Aliit '' 'i.i! 1 '.I A * 1 1fls

i I ~ i !' ii li ''

I 1U. IL V A I I.1 I ll. , W A . i 1

I 1 ' A i ,Lk,! II I ,.I li:'.. ... !... ... A . . .... ..... . ............... .. .....il

............. ..... . .. ............. .... . . .............. . . . ..... !. .............. :.......... ..... :.................. ..... .......... ........ .... ......... .Figure 29. Bottom: Uncorrelated input to BPF, 2 0s, 1V;Top: Uncorrelated output from BPF, 20As, 1V

magnitude of the band pass filter (top waveform) is nearlyconstant for the correlated input (bottom waveform). Figures31 and 32 show a comparison between the uncorrelated andcorrelated RF pulses and its effect on the envelope detector'slow pass filter output (bottom waveform) and the integratoramplifier output (top waveform). Since the integrator outputvoltage level is ultimately used to determine the received

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!/Ii A- I 7 V. :lJ!!iiIt~~~~ I~(1TV....... L.. .... . .!~ ~ ~ ~ ~~~L I.Jt/III]tI/][] I I I !, i

'i il j In11A I J II. .. . A

S' 7V i : '4i II . . . . . ...... ... . .J l ~ l l~~.............. . ..... ....... .. ............... ................. . .............. ...... ........................ .... .............. .I I I . .

Figure 30. Bottom: Correla ted RF pulse input to BPF,20As, 1V; Top: Correla ted RF pulse out of BPF, 20As, 1V

data, a highly correlated signal increases the signal-to-noiseratio and reduces the bit error rate. To verify that thecomparators and digital logic integrated circuit chips wereproperly connected and the synchronization timing (to bediscussed later) was properly calculated, the 15 chip m-sequence was clocked as data into the modulator (Figure 33,top waveform) and compared with the data clocked out of thedemodulator (Figure 33, bottom waveform) . From this figure thereceived data is a delayed duplicate of the transmitted data.

4. Frequency Sweep ModuleBecause eight bit digital components were used to

construct the sweep module, the frequency sweep range waslimited by the frequency resolution. A frequency resolution

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I. ..... . .. .. ..... ...... . . . . .................. ." ... .............. . . . .. ....... . .... ....... .... + ..... . .. .. . ...i . . . . . . . ...... ..... ...... .... . .

.. . ... . .

S: . ,9..

4.:... ..... - - ...-.... . . .. ...... ........

Fgr 31 Botm ,norlaeenloedtcroup ,

... . .

........ -... .. ... ..---. - -- . .................... . - - .- ' -.. . .+..... -...............

I Ii. I I- - - -I - -

SII i I 9,p y I ":. l l i

Fiur 32 Botm Corltd neoe eetrupt

* * *

I , .. " 9 p,f.I .,, + ; + , . + , .. II I 1. ,:I ,Figure 31. , .. .,,I.'4otm:Ucorlte nvlp deetr ou-... ltput,

2.Oms, 2v; Top: Correlated integrator output, 2.Oms, 4V

'I *I I 'I I i a

... 4.. .-. ,,, -...-..,.","

' ,'I I. I 'i t, I I. :I I

Figue1 Botm Unorltdevlp eecoIupt

2.0ms, 2V ; Top: UCorrelated integrator output, 2.0ms, 4V

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.i i. TT11N - -. F1TTYT 3I I I i '3)) ! I!1 I I 13 I

fi4,U. UJ UU1 .i J-L..................... ...................... .,.....................

. .... ...

k)l ! 33It 11,; 1.......... --........................ J..........................L U. ...............-....i . . , .. . . .. . ... ... ............ . ..... ........ . .. .. . , . . . .... . .....-.... .. .. .... .. .. . ... ...... . ..... . .. .....Fgr 3 Bio m

Figure ou3 Bottm aainemodulator, 5.Oms, 2V;

of six hertz per bit worked well for this design. A coarserresolution resulted in increments too great for thedemodulator to maintain track after acquisition. With theseconstraints the sweep range was approximately 1.5 kHz. Usingthe variable resistor in the DAC block of Drawing A-6, thesweep range was centered about the modulator chip rate of 76.2kHz. In addition to sweeping the range of possible m-sequence frequencies, the frequency sweep module acceptsanalog voltage feedback into the klo "esistor in the DACblock and digital voltage feedback into the latch in thedigital count block.

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5. Early Minus Late ModuleFigures 34 and 35 are the one-half chip early (top)

and one-half chip late (bottom) waveforms represented usingsingle and dual axis displays. The inverted late correlationwaveform was produced by inverting the diode in Drawing A-7.Summing the early and inverted late correlation waveformsresulted in the early minus late waveform of Figure 36. Thisis the analog feedback control voltage which holds the m-sequences within one-half chip in-phase. The waveforms ofFigures 34 through 36 are only generated when the two m-sequences are sliding past one another. When the m-sequenceslock together, the early and late waveforms ramp up and

9 1i1 I,**.4 - . 4 t+................ ................. .. ............ .. ..... ............... ..................... ......... ......... .......... ......4 ....... ...... . .. . .. . .t t ,

/ LI I*. ....

/ h-- -____

" ...- .. . ... ...... .... . .......- . ... .......... . ..............Fiur 3. Botom Lat ACF 10Os 5V To:EryA

SI I

10 O s 5V t ,i

.53

i .... ....... - -. ......... i .... . ............. .... .. ... +..............I I i* I9

P.: tI Ii I I I I I9 I ! I

Figure 34 . Bottom: Late ACF, l0.Oms, 5V ; Top: Early ACF,10.0ms, 5V53

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Ii~: '".-,z,,.. -," : ...... ............ ..- ' .:-.."-... . r......-,..-......... r . ..... --....-.... .. .... - -.. -.- ...... - ' ............. ....... t....... ...,.............

.................. .... ......................... .............................................. ...................,...... ......... I.............. ,,,, . ...........................................~~~ ~ .. . . i :.L

i. ... . .. .. .... .. ........ .i............. . .-. ....... ....... .. ....... ............ ... ...... ........ . . . . . . . . . . ..... ........... ............... ............ .......... .. . .. . ... . ......... .. . . ............ .............. . ............ ...............

.I . . .. ... ..

Figure 35. Bottom: Late ACF, 5.0Oms, 5V; Top: Early ACF,5. Oms, 5V 4.0

2.. . . .

I .....~~~~~ ~~~................................. ...... .................. ....................... .................... 4 .............. [.. .......... .... .i ... .........-j . ._. - . ..Ii Ti

Fiue3.Botm ae C m 'V o Eal ACE5.ms 5V [

.... ..... .... ............... ........ ............ .....i... i. ........I I i,.LI . :............................ . .. . . . .. . . . .. .. .. .. .. . I....... ................ .. .......... . . . . .

F g 36 Ea l AC inu lat A , I0O,2

SI ..- I4, I , I , ,2 a I 2 2

liI j II ISI I I4 I 2

2 I I

Figure 36 . Early ACF minus late ACE, 10.0ms, 2.5V

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oscillate about their mid-range voltages (See Figure 37) . Theearly minus late waveform oscillates about a reference voltage(DC offset) determined by how close the two m-sequencefrequencies were together at acquisition. If the m-sequences' phase line-up just as the frequencies matched, thenthe DC offset would be zero (See Figure 38). Since this isthe exception rather than the rule, some DC offset exist (SeeFigure 39). This occurrence will be used to track a dopplershift.

................ ................... ...... .............. .............. . .. ........... . ..................... . ...... . .. ................ .. ............ ....... ... ..............

i a a..... .. . .......... ............ * I..................................... . -

..........-. y -1 i

....... a .. . ..i ................... . ...... ................ ..... ... ......... ..... i ................ i.... ......... ... ....... ... ................... .. .. . ....... ....... . . . . ..

. .......

. - .S.1 --. .t. ..... .. ............ .. .

S,-.....- .- -- ...- . , - ." ." ..- .............vA.-.-..,...... ..-...... . . .- .. ........... - . .-. .+-- .-......................

a I a

10. , ,V

j.a I S"... 4.;-/4.a { a i a

.I , I.I, I I I ,

/I . ia a i |i ii :t aI III a

Figure 37 . Bottom: Late ACF, 10.0ms, 5V ; Top: Early ACE,10.0ms, 5V

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. .. -... ...............

L ................ & .... ...... .... ....... ........ ..................... I. . . ......... .. ......... ........ ................... ......... .. . . .- . . ...... ......... . . . .

. ........ ............. . .. .....--....

A- 1 .....i ....-..... ++ ..--.-.................... .......... .... .. . ... ................. ......... ................. ....... ' ............ ....... ..... ... .. ...414

f, .: .4

J.4

.. ...... I I.. .....

4l I

LI !

............ . ........ ................... . ........... .................. 4.-.... .................

Figure 39. Feedback voltage withou DC offset, 20. 0ms,0

, , I ... . .

,I,..,. . .+a. tI I I ;ii I

t.--I-___ -----.---..__.&," .. *,:_-L. ... ..._ .L.-.4l-*,.,. . ..8.........+.L . .+-+.+.A -. ..+...;..;.+. ..............A ..-..- 5. .... . +.---.-.-.-.. -.... ... -.-.. ......Figre39 Fedbc votae "t "C ofst 20Om,

5.

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6. Track

The track module of Drawing A-8 monitors the earlyminus late waveform DC offset and adds or subtracts one bit ata rate of 30 times per second. With a frequency resolution of6 hertz per bit, a doppler shift of less than 180 hertz persecond can be tracked. To test this circuit, a secondfrequency sweep module was constructed, except the digitalcount and DAC were replaced with a 0.44 pF polypropylenecapacitor and a FET unity gain buffer. The capacitor wascharged to a voltage slightly higher than the voltage requiredto drive the VCO at the upper range frequency. When thevoltage source was removed from the capacitor, the capacitorwould discharge current at a rate equal to the FET input biascurrent (50pA). The voltage would decrease at a linear rateequal to the rate corresponding to the max doppler shift ofsix hertz per second. The demodulator successfully tracked asix hertz per second doppler shift over its full range offrequency sweep (1.5 kHz).

7. Demodulator SynchronizationLet the synchronization timing cycle begin at the

start of an RF pulse. Recall from section II.B.7. that theintegrator charge would be dumped at the start of each RFpulse. From Figure 40, the 275 us pulse (the longest pulse,second from left) closes all four switches in Drawing A-5 to

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ground which dumps (discharges) all four integrators. Whenthe dump pulse goes low, integration begins and continuesuntil the next dump pulse (partially drawn at the far right ofFigure 40) . Prior to selecting the RF pulse with the greatestenergy, the parallel-to-serial (P/S) converter must be se t upfor a paral lel load from the encoder. This is accomplished byth e 215 us P/S pulse (the longest, first from left) in Figure41. While P/S pulse is high, the paral lel mode is selectedand the clock pulse (centered in the parallel load pulse ofFigure 41) activates the parallel load. This also moves thefirst bit of the encoded pair out of the serial-to-parallelconverter. This is the same clock pulse as can be seen

............

. . . . .

. . . . .

.. ... . ..... .. .. .. .. .......... ............ ........ .. .. . .......... . ......... i . ............. i ................... ... ........... ..... .. ............... 4 .. .. . .hi: I I S ,

S........:".... ..... ....... -.-._-... ...... ...... ...- ..... . .. .. - ,,,I |I

{, .- t--, ,.......I...... ._ ._I s S

I I I i i

................. ... .................... ......................

Figure 40. Synchronization sample and dump timing, 200gs,2.5V58

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occurring right before the start of an integrator dump (end ofRF pulse) in Figure 40. When the P/S pulse goes low, theserial mcde is activated. The next clock pulse (not centeredin th e P/S pulse of Figure 41) moves th e second of th e twoenroded bits out of th e parallel-to-serial converter. Thiscycle repeats itself with th e start of th e integrator dump.

.. .............. ..i ................ ... .......... ..... ..... ..................... ......... .......... ....... ......... I .............. ..... $........... ..... ...I ... ............ . . . .t -i J i

I'*... ... . .... ..... .".. . .. . ... . .. .. . ... . . ... ... ... .. ....I" '

.. . .. , . -. ,..........' ................ . ..... .............. .................... ......... . .. ..... . .......... .. .................... ........ .... .... ..... .... .. ..L-... -......... .. ..... ........ J--........ .................. .- . ..... ..... -. .........$-- . . . .- - - -i--

Figure 41. Synchronization paral lel load timing, 5 004s,2.5V

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8. Probability of Bit ErrorProbability of bit error testing was accomplished

using the following equation taken from [Ref. 4:p. 44]:

(S/N) dB 201ogl0 ( Vis signaLVlms noise

The modulator signal was a 1V amplitude RF pulse. Forsinusoidal waveforms Vrms = V/12; therefore, Vrms signal = 1/12.Vrms noise was generated by a Wavetek, model 132, VCG/NoiseGenerator with a sequence length of 220-1 and a noise frequencyof 160 kHz to 1.6 MHz. The Vrmsnoise amplitude was determined bymeasuring the value read on an averaging AC voltmeter(Hewlett-Packard 427A Voltmeter) and multiplying that value by1.13. [Ref. 12:p. 454] The noise was added to the output of themodulator using a summing amplifier. A test circuit wasdesigned and built. It took the modulator input data andcompared it with the demodulator output data using anexclusive-or gate (XOR). When the inputs to the XOR disagreedthe XOR output went high. In the middle of each bit period,the output of the XOR was clocked into a 4-bit shift register.If the shift register output (QI) goes high, the positive-going pulse clocks a counter and one error is recorded. At thestart of each bit period, the shift register is cleared whichprepares it to clock the next error. LEDs were connected tothe counter output via a driver so that errors could be

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visually counted. Tw o sets of data were recorded, one with ananalog feedback rate of 5 Hz and a second with an analogfeedback rate of 10 Hz. The results are plotted in Figure 42.Based on these limited tests, a SNR greater than -1.25 dBwould be required to have a bit error rate less than 10s.

--2 -- '5 -- ' -- 0 2

Figure 42. Probability of bit error61

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V. RECOMMENDED DESIGN MODIFICATIONS

A. 4-FSK SPREAD SPECTRUM MODULATIONReduce the size of the S/P convertor module by replacing

the 4-16 line latched input decoder with a 2-4 line latchedinput decoder. No change in performance would result. Forgreater stability replace the sine wave generators (the AZ63c,AD639, and LM318 integrator) with crystal oscillators. Thesine wave generators were initially selected because theycould be adjusted over a wide range of frequencies whichallowed fo r design changes. The crystal oscillators takelonger to receive and allow for only slight frequencyadjustment. The second order low pass filters could be changedto fourth order by cascading a second identical stage. Thiswould further reduce the signal energy in the lowerfrequencies' harmonics from showing up as noise in thedemodulator's higher frequencies envelope detectors.

B. 4-FSK SPREAD SPECTRUM DEMODULATIONIn the frequency sweep module, replace the 8-bit counter,

latch, and digital-to-analog convertor with at least 12-oitcomporents to greatly increase the frequency range and retainadequate resolution of the frequency sweep module. 12-bitcomponents would allow fo r 4,096 frequency steps vice the 25 6frequency steps available with 8 b it components. Increased

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number of frequency steps results in a frequency resolution of4.9 hertz per bit over a 20 kH z doppler shift. It wasdemonstrated on the prototype that the maximum doppler shiftcould be tracked over a limited range of frequencies. 12-bitcomponents would be capable of tracking through the fullfrequency range.

Modify the -arly minus late module by eliminating one-half of the envelope detectors, low pass filters summingoperational amplifiers, and gain amplifier. This can be doneif both early and late are switched alternately through theremaining half and then adding a sample and hold to retainthese signal values for subsequent subtraction. This wouldresult in a better balance (identical) between early and latesignals, which would lock the m-sequences closer in-phase.

In the track module, add an integrate and dump circuitwhich would take the input early minus late voltage and outputthe average DC offset voltage. This would preclude anypossibility of a false comparison with the zero volt referencevoltage. The ALU can be removed if a BUS is added which wouldallow the communications control unit microprocessor toperform the required additions and subtractions.

The demodulator synchronization was based on a m-sequence length of 127 with taps on the third and seventhstages. A second two tap m-sequence length of 127 exists withtaps on the first and seventh stages. If the taps are changedthen the synchronization code bytes must also be changed to

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correspond to the same relative positions within the m-sequence.

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APPENDIX A: CIRCUIT SCHEMATICS

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> C-c

0) 00 L..Lnf

(I)" ';s

0 ( (JS)

(0)

em 0

00

z5kz

IL

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- -tI ----- - -0 -

I Q) >ILIE

(D >I C/' fn

rrn> k Onu0 0 0 Z +> P) 0 0Q jI,II io E

0 +-

> IIi Il

t :CN f) In0--D LJzz

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LnJ

0J9 ,

w ccoo EL LLJ

CLC

44K MK

_ H69.

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-L atI

ILnL ... ~... D

D[

-0 I~ - -

--- -- --

-- . ----I 0

zJ- ------ ------ ---- -- -------- T,--------------------

022

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w~ 0J

7AU

0 00 Lo

cxL~

L . . -- 1 z

m I N 0I

a -aL --------- ---- I ---- - - -

L ------------------------------ 4Iix

zzI- (0

71---

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S 1LA& -j

Jfltn 0 a

2 2

- I.

Lli

Z)I-

PzzAt

D I

2 72

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-o I

to 00m

Wat 0 15 -S

m~~~~~C 1c,____ __ _

I I _ _ _ _A_It.-I

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(S)U-~~~C >

< 5 -0

0~ :) : )0 0-

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APPENDIX B: GENERALIZED IMPEDANCE CONVERTER (GIC) FILTERDESIGN

The GIC was selected fo r the active filter design becauseit eliminates the need fo r inductors, has superior sensitivitycharacteristics, and 20dB per decade attenuation outside thepass band per each two operational amplifier, eiaht passiveelement stage. The GIC information contained in this Appendixwas extracted from [Ref. 1i:pp. 18-22] which should bereviewed fo r additional details.

Drawing B-l is a diagram of the GIC where the Y representsthe impedance of one or two passive elements and T representsthe transfer function at that circuit node. Two values of Tare identified, Ti for th e transfer function of a band passfilter and T2 fo r the transfer function of low pass filter.The GIC is capable of implementing high pass, notch, and allpass filters, but these are not discussed since they were notused in this thesis. The non-ideal (operational amplifiersmodeled by a single pole) transfer function of the GIC atoutput nodes T1 and T2 are

T, NUMERATOR = yy7) (7) Y 5-3A,

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T, DENOMINATOR = - _8(_3__5____8( _5_0AIA, Al

Y4- Y'- YS) (Y-YY5 - Y'Y3

A, m% z,-YS) YY) r Y)(Y ,T. NUMERATOR Y A - (S(Y O -YY3Y--Y YY -

T, DENOMINATOR = T, DENOMINATOR

To create a band pass filter use transfer function T, and secYI=Y,=Y4 =Y6=G , Y3=Y,=C, and Y,=G/Q where G is admittance, C :scapacitance, and Q is the quality factor of the filter. Theactual values of G(l/R) and C are calculated from the equa:isnfo r the band pass filter's center frequency (W )

1WO0 i--

The Q of the filter is calculated using the center frequencyand the upper and lower 3dB frequencies (W, and Wrespectively).

W

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Observe that th e transfer functions contain terms divided byth e small signal bandwidth (A) . For ideal filters "A"approaczhes infinity and these terms approach zero. Theequation used to calculate w. assumes that ideal operationalamplifiers are used to construct th e filter, this is not th ecase in practice. As th e frequency increases th e denominatorof th e small signal bandwidth terms no longer dominates andth e magnitude of th e transfer function becomes less than th eidealized model. The net result is that the idealized bandpass filter shifts down in frequency and passes a band offrequencies less than designed for using the equations for w,and Q.

To correct for an operational am plifier 's finite smallsignal bandwidth, use th e following procedure (test resultswere quite accurate):

1. Choose operational amplifiers with a relatively widesmall signal bandwidth and fast slew rate. (The design ofall active filters in this thesis used LM318 operationalamplifiers which have a small signal bandwidth of 15 MHzand a slew rate of 70 volts per microsecond.)2. Using th e Matlab program for plotting th e non-ideal GICband pass filter transfer function (TM) provided inAppendix E, enter th e range of frequencies of interest (w)in radians, th e center frequency (wO) , and th e Q of thefilter.3. Plot th e non-ideal transfer function and calculate fromth e plot how far down in frequency th e center frequencyshifted from th e required center frequency.4. Add this amount to th e center frequency (wO) in th eMatlab program.

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5. After only a few iterations, the plot of the band passfilter will meet the filter design specifications.6. The ratio of the passive element values can now becalculated from the equation

-RCwhere w.1 is the adjusted center frequency. Choose R and Cbased on availability.

7. Construct the band pass filter circuit of Drawing B-2.

For low pass filter design use the same steps as fo r aband pass filter, only replace transfer function T. for T,. Usethe Matlab program provided in Appendix E and construct thelow pass filter of Drawing B-3.

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CNK

-0 0.4 -

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CNL

z LL) I< C-

0

IN0 a)(S

-~~> - ----Of

u z

u 0 D10.J03130 LOnv3-1

zzm c

3 L-OK1032J1 3 0LkOdi331]

L 4"80

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040>

u7- CCLC

U-)LL

I 4)

dfl~t0

II I

o~z

oo >J

0 1001013 i-181 Ol

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APPENDIX C: BUFFERS

High frequency buffers are used throughout this design.Each buffer was designed to isolate components which wouldotherwise not function properly when connected together due toimpedance mismatch. This is accomplished by the use of LM318operational amplifiers constructed as in Drawing C-i. A 0.1MF ceramic and a 1.0 AF electrolytic capacitor are placed nearthe positive and negative power supplies to bypass highfrequency signals. A 30 pF ceramic capacitor is placedbetween the decompensation pins (1 and 5) to extend the gain-bandwidth product. Buffers built without the power supplybypass capacitors and decompensation capacitor were extremelyunstable even at low frequencies (below 1KHz).

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CNC

U-z flLUJ

LL Z)Lin0 u-E

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APPENDIX D: DOPPLER SHIFT

Worst case doppler shift calculations were based on thefollowing assumptions:

1. The earth is spherical with a constant radius.2. The azimuth angle between the satellite and the positionon earth is equal to zero; only the elevation anglechanges.3. The satellite elevation above the earth (a) isconstant.

Using the law of cosines and Figure D-l, the slant range as afunction of time, a(t), is equal to :

a 2 (t) = R 2r 2 -2Rrcos6(t)

a(t) = V!R2+r2-2Rrcos6(t)

where R (radius of earth) = 6373 kmr (radius of satellite orbit) = 7113.8 km

To find the change in slant range as a function of time, takethe first derivative of a(t).

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d a (t) RrsinO d~-a~t)dt R2 r2 -2RrcosOSubstituting the orbital velocity (V) for rdO/dt in theprevious equation and knowing the velocity of a circular orbitis equal to :

GMV =-N r

the equation for the relative velocity between a satellite anda fixed position on earth given the assumptions stated aboveis:

RiG s in8d a(t) = r~ sdR 2 +r2 -2RrcosO

Figure D-1. Satellite Orbit

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where G (Gravitational constant) = 6.67xlO1 1 Nm /kg 2M (Mass of the earth) = 5.98x10 24 kg

A plot of relative slant range velocity (u) versus elevationangle is shown in Figure D-2.

Knowing the maximum relative slant range velocity (Umaxfrom Figure D-2 and the equation for doppler shift,

fl ifU CS-cosec

th e maximum shift in channel frequency fl 1 can beax 'calculated from:

if1 = ~ ff1max f:-fSUmaxCosOminC

3C

-$30C :o -0 -. 000 -2030C20 *0 60 ~

Figure D-2. Slant range velocity86

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where fc (Carrier frequency) = 437.25 MHzf 4 (Highest baseband frequency) = 304.8 kHzUmax (Maximum slant range velocity) = 6708 m/sc (Speed of light) = 3X10 8 m/semin (Minimum elevation angle) = 0 degrees

The maximum doppler shift in frequency is equal to 9784 Hz.A plot of the channel frequency shift caused by the dopplereffect versus the elevation angle of the satellite withrespect to the horizon is shown in Figure D-3. The MATLAB codeused to create these plots is provided in Appendix E.

2'0

05 5 2 25

Figure D-3. Channel frequency doppler shift87

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APPENDIX E: COMPUTER PROGRAMS

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