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DRC 2011

60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised

source-drain regrowth

Device Research Conference 2011Santa Barbara, California

6/20/2011

Andrew D. Carter, J. J. M. Law, E. Lobisser, G. J. Burek, W. J. Mitchell, B. J. Thibeault,

A. C. Gossard, and M. J. W. RodwellECE Department

University California – Santa Barbara

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DRC 2011

Overview

• Why III-V MOSFETs?• Device Physics and Scaling Laws• Process Flow• Measurements• Conclusions

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DRC 2011

Why III V VLSI?Higher electron velocities than Si MOS

For short Lg FETs,

Transconductance,

Jd and gm are key figures of merit in VLSI

However:Jd and gm degraded by source large Raccess

Jd and gm degraded by interface trap density, Dit

Therefore, we must develop:Low access resistance source/drain contacts

Thin, high-k, low Dit dielectrics on InGaAs

Fully self-aligned process modules

satchannelsdrain vnqJ ,

sateffectivem vCg

MOSFETs have been, and always will be, a materials challenge.

1/Ron

Jd,max

gm

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DRC 2011

)( dosdos

channel Vq

Cn

FET Device Physics

ox

roox t

C

2channel

channelodepth tC

2

*2

2, gmqC Ddos

satchannelsdrain vnqJ ,

sateffectivem vCg

*Ceffective includes Cox, Cdepth, Cdos Electron band diagram of a quantum well FET

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DRC 2011

FET Device Scaling

Si CMOS scaling: Contacted gate pitch 4x the gate length1)

4:1 reduction of contact area2) 4:1 reduction of contact

22 nm node 33 nm LS/D For LS/D = LT, requires 5x10-9 ohm-cm2 contact

sh

cT R

L Length Transfer Contact

Contacted Gate Pitch

LS/D

Lg

WS/D

1) S. Natarajan, et al, IEDM 2008.2) M.J.W. Rodwell, et al, IPRM 2010.

LS/D

Lg

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DRC 2011

Gate First FET Process FlowThick (10 nm) channel

Process damage mitigation Heavy ( ~ 9x1012 cm-2) doping

Prevents ungated sidewall current chokeIn0.52Al0.48As heterobarrier

Carrier confinementSemi-insulating InP

Device isolation

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DRC 2011

Gate First FET Process Flow

Front End: Gate Stack DefinitionIn-situ hydrogen plasma / TMA treatment before Al2O3 growthMixed e-beam / optical lithographyBi-layer gate (Sputtered W + e-beam evaporated Cr)

High selectivity, low power dry etch

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DRC 2011

FET Process DevelopmentUse optical lithography to produce >0.5um gates

Use electron beam lithography to produce sub-100nm gates

Need to investigate possible e-beam damage to oxides

Cr

HSQ (SiO2)

W

CrSiO2

EBL Tests

Cr + SiNx

SiO2 + SiNx

W + SiNx

Field: SiNx

Finished Gate Etch + Sidewall Deposition

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DRC 2011

FET Process Development

ICP dry etches calibrated to perform at sub-100nm scale

W

HSQ

Cr

Cr

SiO2

W

HSQ

Cr

Cr

SiO2

Increased ICP Power

Higher power dry etch vertical gate stack

Undercutting leads to fallen gates, ungated access regions Minimize Cr undercut by reducing thickness

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DRC 2011

Gate First FET Process Flow

Front End: Gate Stack DefinitionSidewall Deposition

Conformal, protects S/D short circuit to gateSidewall etch

Vertical gate stack self aligned sidewall

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DRC 2011

FET Process DevelopmentLow power etch Isotropic etching + undercut fallen gatesLarge undercuts ungated regions high Raccess

Thick gate stack: Small LgLarge sidewall foot Unreliable gates

Thin Cr stack: Small LgLarge sidewall foot Repeatable gate etch?

ALD SiO2 sidewall:Small LgStill sidewall foot! Unrepeatable gate undercut

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DRC 2011

Gate First FET Process Flow

Regrowth and Back EndSurface preparation

UV O3 exposure to clean the source/drain, removed ex-situ before MBE loadMBE InAs Regrowth

Low arsenic flux, high temperature near gate fill inMetallization and Mesa Isolation

In-situ Mo in MBE optional for lower cTi/Pd/Au liftoffWet etch for mesa isolation

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DRC 2011

Gate First FET Process Flow

Regrowth Regrowth

Tungsten

Chrome

SiO2

SiNx Sidewalls

TEM micrographs of 60 nm Lg device

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DRC 2011

Gate First FET Results

60 nm Lg 115 nm Lg

Increased leakage current: Heavy doping leakage path Drain induced barrier lowering

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DRC 2011

Gate First FET Results60 nm Lg

High Jdrain but depletion mode

Transconductance: Similar to previous results* (~0.3mS/m)

Low Ron (371 ohm-m) for InGaAs MOSFETs

1/Ron

*) U. Singisetti et al, IEEE EDL Nov. 2009.

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DRC 2011

Gate First FET Results

Jdrain increases rapidly with gate length scaling

Transconductance: Relatively flat with gate length scaling

*) U. Singisetti et al, IEEE EDL Nov. 2009.

Wg = 9 m

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DRC 2011

FET: Access Resistance

Gateless transistor effective diagnostic of regrowth

0

500

1000

1500

2000

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Vgs

= 1V

Vgs

= 2V

Vgs

= 3V

y = 400.46 + 795.01x R2= 0.98313 y = 337.87 + 658.51x R2= 0.9877 y = 304.7 + 608.65x R2= 0.98906

On

Res

ista

nce

(ohm

-mm

)

Gate Length (m)

0

500

1000

1500

2000

0 0.2 0.4 0.6 0.8 1 1.2 1.4

y = 193.37 + 818.63x R2= 0.9865

Res

ista

nce

(ohm

-m

)

Gate Length (m)

accessgapsh

measured RWLR

R 2

MOSFET On Resistance Gateless Transistor Resistance

Wg=9 m Tchan=10 nm

Wg=25 m Tchan=15 nm

Raccess: 200 ohm-m

Raccess: 100 ohm-m

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DRC 2011

Gate First FET: Metal-Regrowth TLM

sh

cT

TT

cc

cgapsh

measured

RL

L.LWL

R

RWLR

R

51for

2

Metal-Regrowth access resistance is not a limiting factor in Jdrain

Ex-situ Ti/Pd/Au / n-type InAs contacts: c = 2 x 10-8 ohm-cm2

In-situ Mo / n-type InAs contacts have shown c = 6 x 10-9 ohm-cm2 *

Wg = 14 m

*) M.J.W. Rodwell, et al, IPRM 2010.

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DRC 2011

Gate First FET: Issues

Ungated region potential current chokeThinner sidewall can help…… but hard to control with gate undercut

Electron band diagram of channel underneath sidewall

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DRC 2011

Gate First FET: Issues

Heavy doping parallel conduction, poor gmLarge leakage current in deviceDecreases Cdepth limits gm

doping 109 212 cm doping no

Must reduce doping while maintaining low Raccess

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DRC 2011

Conclusions60 nm gate first InGaAs MOSFET process flow

Jdrain exceeding 1.2 mA/m

Low Ron = 371 ohm-m

Self-aligned process flow for sub-100 nm III-V VLSI

Continued research areasMinimizing ungated regionsThinner dielectricsDit passivation techniques

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DRC 2011

Thanks for your time!Questions?

contact address: adc [at] ece.ucsb.edu

This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006). A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.