3.Micro Controllers

8/9/2019 3.Micro Controllers

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3.MICROCONTROLLERS

3.1 INTRODUCTION:

Microprocessors and microcontrollers are widely used in embedded systems products. Microcontroller is a programmable device. A microcontroller has a CPU in

addition to a fixed amount of RAM, R M, !" ports and a timer embedded all on a single

chip. #he fixed amount of on$chip R M, RAM and number of !" ports in

microcontrollers ma%es them ideal for many applications in which cost and space are

critical.

#he !ntel &'() is *arvard architecture, single chip microcontroller + C- which

was developed by !ntel in ) &' for use in embedded systems. !t was popular in the ) &'s

and early ) 's, but today it has largely been superseded by a vast range of enhanced

devices with &'()$compatible processor cores that are manufactured by more than /'

independent manufacturers including Atmel, !nfineon #echnologies and Maxim

!ntegrated Products.

&'() is an &$bit processor, meaning that the CPU can wor% on only & bits of data

at a time. 0ata larger than & bits has to be bro%en into &$bit pieces to be processed by the

CPU. &'() is available in different memory types such as U1$2PR M, 3lash and 41$

RAM.

#he microcontroller used in this pro5ect is At& s(/. Atmel Corporation introduced

this at& s(/ microcontroller. #his microcontroller belongs to &'() family. #his

microcontroller had )/& bytes of RAM, 67 bytes of on$chip R M, two timers, one serial

port and four ports +each &$bits wide- all on a single chip. At& s(/ is 3lash type &'().

#he present pro5ect is implemented on 7eil Uvision. !n order to program the

device, proload tool has been used to burn the program onto the microcontroller.


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#he features, pin description of the microcontroller and the software tools used are

discussed in the following sections.

3.2 FEATURES OF At89s52:

67 8ytes of Re$programmable 3lash Memory.

RAM is )/& bytes.

/.91 to :1 perating Range.

3ully ;tatic peration< ' *= to /6 M*=.

#wo$level Program Memory >oc%.

)/& x &$bit !nternal RAM.

?/ Programmable !" >ines.

#wo ):$bit #imer"Counters.

;ix !nterrupt ;ources.

Programmable ;erial UAR# Channel.

>ow$power !dle and Power$down Modes.


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3.3 DESCRIPTION:

#he At& s(/ is a low$voltage, high$performance CM ; &$bit microcomputer with

67 bytes of 3lash programmable memory. #he device is manufactured using Atmel@s

high$density nonvolatile memory technology and is compatible with the industry$

standard MC;$() instruction set. 8y combining a versatile &$bit CPU with 3lash on a

monolithic chip, the Atmel At& s(/ is a powerful microcomputer, which provides a

highly flexible and cost$effective solution to many embedded control applications.

!n addition, the At& s(/ is designed with static logic for operation down to =ero

fre uency and supports two software selectable power saving modes. #he !dle Mode

stops the CPU while allowing the RAM, timer"counters, serial port and interrupt system

to continue functioning. #he power$down mode saves the RAM contents but free=es the

oscillator disabling all other chip functions until the next hardware reset.


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3.4 PIN DIAGRAM

Fig 4.2.1: Pin di g! "


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Fig 4.2.2: #$%&' di g! " %( t89s52


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3.5 PIN DESCRIPTION:

3.5.1 )CC: Pin 6' provides supply voltage to the chip. #he voltage source is B(1.

3.5.2 GND: Pin /' is the ground.

3.5.3 *TA+1 nd *TA+2:

#A>) and #A>/ are the input and output, respectively, of an inverting

amplifier that can be configured for use as an on$chip oscillator, as shown in 3igure )).

2ither a uart= crystal or ceramic resonator may be used. #o drive the device from anexternal cloc% source, #A>/ should be left unconnected while #A>) is driven, as

shown in the below figure. #here are no re uirements on the duty cycle of the external

cloc% signal, since the input to the internal cloc%ing circuitry is through a divide$by$two

flip$flop, but minimum and maximum voltage high and low time specifications must be

observed.


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Pin ?) is 2A. !t is an active low signal. !t is an input pin and must be connected to

either 1cc or F40 but it cannot be left unconnected.

#he &'() family members all come with on$chip R M to store programs. !n such

cases, the 2A pin is connected to 1cc. !f the code is stored on an external R M, the 2A

pin must be connected to F40 to indicate that the code is stored externally.

3.5. PSEN 0P!%g! " st%!, ,n $, :

#his is an output pin.

3.5. A+E 0Add!,ss $ t& ,n $, :

#his is an output pin and is active high.

3. PORTS 67 17 2 3:

#he four ports P', P), P/ and P? each use & pins, ma%ing them &$bit ports. All the

ports upon R2;2# are configured as input, since P'$P? have value 33* on them.

3. .1 PORT 60P6 :

Port ' is also designated as A0'$A09, allowing it to be used for both address and

data. A>2 indicates if P' has address or data. Ghen A>2D', it provides data 0'$09, but

when A>2D), it has address A'$A9. #herefore, A>2 is used for demultiplexing address

and data with the help of an internal latch.

Ghen there is no external memory connection, the pins of P' must be connected

to a )'7$ohm pull$up resistor. #his is due to the fact that P' is an open drain. Gith

external pull$up resistors connected to P', it can be used as a simple !" , 5ust li%e P) and


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P/. 8ut the ports P), P/ and P? do not need any pull$up resistors since they already have

pull$up resistors internally. Upon reset, ports P), P/ and P? are configured as input ports.

3. .2 PORT 1 PORT 2:

Gith no external memory connection, both P) and P/ are used as simple !" .

Gith external memory connections, port / must be used along with P' to provide the ):$

bit address for the external memory. Port / is designated as A&$A)( indicating its dual

function. Ghile P' provides the lower & bits via A'$A9, it is the 5ob of P/ to provide bits

A&$A)( of the address .

3. .3 PORT 3:

Port ? occupies a total of & pins, pins )' through )9. !t can be used as input or

output. P? does not need any pull$up resistors, the same as port ) and port /. Port ? has an

additional function of providing some extremely important signals such as interrupts .

T $, 4.2.1: P%!t 3 A$t,!n t, F/n&ti%ns


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3. Add!,ssing M%d,s:

Ghile operating, processor processes data according to the program instructions.

2ach instruction consists of two parts. ne part describes what should be done and

another part indicates what to use to do it. #his later part can be data +binary number- or

address where the data is stored. All &'() microcontrollers use two ways of addressing

depending on which part of memory should be accessed<

3. .1 Di!,&t Add!,ssing:

n direct addressing, a value is obtained from a memory location while theaddress of that location is specified in instruction. nly after that, the instruction can

process data +how depends on the type of instruction< addition, subtraction, copyH-.

bviously, a number being changed during operating a variable can reside at that

specified address. 3or example< ;ince the address is only one byte in si=e + the greatest


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number is /((-, this is how only the first /(( locations in RAM can be accessed in this

case the first half of the basic RAM is intended to be used freely, while another half is

reserved for the ;3Rs.

3. .2 Indi!,&t Add!,ssing:

n indirect addressing, a register which contains address of another register is

specified in the instruction. A value used in operating process resides in that another

register. 3or example<

nly RAM locations available for use are accessed by indirect addressing +never

in the ;3Rs-. 3or all latest versions of the microcontrollers with additional memory bloc%

+those )/& locations in 0ata Memory-, this is the only way of accessing them. ;imply,

when during operating, the instruction including IJK sign is encountered and if the

specified address is higher than )/& +93 hex.-, the processor %nows that indirect

addressing is used and 5umps over memory space reserved for the ;3Rs.

3.8 MAC INE C C+E FOR 8651:

#he CPU ta%es a certain number of cloc% cycles to execute an instruction. !n the

&'() family, these cloc% cycles are referred to as machine cycles. #he length of the

machine cycle depends on the fre uency of the crystal oscillator. #he crystal oscillator,

along with on$chip circuitry, provides the cloc% source for the &'() CPU.

#he fre uency can vary from 6 M*= to ?' M*=, depending upon the chip rating

and manufacturer. 8ut the exact fre uency of )).'( / M*= crystal oscillator is used to

ma%e the &'() based system compatible with the serial port of the !8M PC.


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!n the original version of &'(), one machine cycle lasts )/ oscillator periods.

#herefore, to calculate the machine cycle for the &'(), the calculation is made as )")/ of

the crystal fre uency and its inverse is ta%en.

#he assembly language program is written and this program has to be dumped into

the microcontroller for the hardware %it to function according to the software. #he

program dumped in the microcontroller is stored in the 3lash memory in the

microcontroller. 8efore that, this 3lash memory has to be programmed and is discussed in

the next section.

3.9 PROGRAMMING T E F+AS

#he At& s(/ is normally shipped with the on$chip 3lash memory array in the

erased state +that is, contents D 33*- and ready to be programmed. #he programming

interface accepts either a high$voltage +)/$volt- or a low$voltage +1CC- program enable

signal. #he low$voltage programming mode provides a convenient way to program the

At& s(/ inside the user@s system, while the high$voltage programming mode is

compatible with conventional third party 3lash or 2PR M programmers. #he At& s(/ is

shipped with either the high$voltage or low$voltage programming mode enabled. #he

respective top$side mar%ing and device signature codes are listed in the following table.

T $, 4.3.1: T%; sid, " !'ing D, i&, Sign t/!, &%d,s


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#he At& s(/ code memory array is programmed byte$byte in either programming

mode. #o program any nonblan% byte in the on$chip 3lash Memory, the entire memory

must be erased using the Chip 2rase Mode.

3.9.1 P!%g! ""ing A$g%!it ":

8efore programming the At& s(/, the address, data and control signals should be

set up according to the 3lash programming mode table. #o program the At& s(/, the

following steps should be considered<

). !nput the desired memory location on the address lines.

/. !nput the appropriate data byte on the data lines.

?. Activate the correct combination of control signals.

6. Raise 2A"1PP to )/1 for the high$voltage programming mode.

(. Pulse A>2"PR F once to program a byte in the 3lash array or the loc% bits. #he byte$

write cycle is self$timed and typically ta%es no more than ).( ms.

Repeat steps ) through (, changing the address and data for the entire array or until the

end of the ob5ect file is reached.

3.9.2 D t P%$$ing:

#he At& s(/ features 0ata Polling to indicate the end of a write cycle. 0uring a

write cycle, an attempted read of the last byte written will result in the complement of the

written datum on P .9. nce the write cycle has been completed, true data are valid on


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all outputs, and the next cycle may begin. 0ata Polling may begin any time after a write

cycle has been initiated.

3.9.3 R, d


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Fig 4.3.1: P!%g! ""ing t , F$ s

3.Micro Controllers

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