S. K. CHAUDHARY EDUCATIONAL TRUST’s

SHANKARA INSTITUTE OF TECHNOLOGY

KUKAS, JAIPUR

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

SESSION-(2011-2012)

ABSTRACT ON

THREE DIMENSIONAL INTEGRATED CIRCUIT

SUBMITTED IN PARTIAL FULFILLMENT FOR AWARD OF DEGREE OF BACHELOR OF TECHNOLOGY

RAJASTHAN TECHNICAL UNIVERSITY ,KOTA(RAJASTHAN)

SUBMITTED TO SUBMITTED BY

MR. ASHUTOSH MISHRA TANUJA MATHUR

H.O.D. (08ESIEC120)

(ECE DEPARTMENT)

THREE DIMENSIONAL INTEGRATED CIRCUIT

INTRODACTION

In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is pursuing this promising technology in many different forms, but it is not yet

widely used; consequently, the definition is still somewhat fluid.

3D ICs vs. 3D packaging

3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate using on-chip signaling, whether vertically or horizontally. A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board.

Manufacturing technologies

There are four ways to build a 3D IC:

Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then dicedinto 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This

monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.

Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size – but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300mm), complicating heterogeneous integration.

Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing.

Die-on-Die – Electronic components are built on multiple dice, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack [5]. Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).