[Technical Paper] Thermal Performance of 3D IC Package ...

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Tain et al.: 3D IC TSV Thermal Performance (1/10)

1. IntroductionThrough-silicon via (TSV) technology for 3D IC has

drawn significant attention in recent years. The idea of

having through vias in silicon is to shorten the transmis-

sion wire to reduce the RC delay, and thus the perfor-

mance of the IC can be improved by lowering power con-

sumption with shortened wiring network.[3] Using the

TSVs, a conventional IC design can be divided into two or

more than two chips and these IC chips can be stacked up

vertically and communicate with each other through vias.

However, thermal challenge of the 3D IC chip stack

becomes a limitation for using the TSVs because the heat

spreading in the stack is less effective than non-stacked

chips.[4, 5] Therefore, thermal performance is the major

concern for vertical IC chip stack. TSV is a metal-filled

component embedded in a silicon chip, where a dielectric

layer (e.g. silicon dioxide, SiO2) is deposited between the

bulk silicon and the metal filling. The thermal conductivity

of SiO2 layer is orders of magnitude less than that of metal

filling, e.g. the copper. Thus, the thermal property for a

TSV or a TSV group is much better in vertical direction

than in the planar direction.

Thermal solutions for stacked IC structure have been

proposed and investigated from literature.[6, 7] Experi-

ment results and simulation analyses have also been

reported, especially for the TSV thermal behavior.[4, 5, 8, 9]

Oprins et al.[8] has designed and fabricated a test chip as

well as conducted the measurements of thermal perfor-

mance for the test vehicle, which one thinned chip with

TSV is bonded on top of a thick chip without TSV using

Cu-Cu thermo-compression bonding technology. Heaters

are designed in the test chip at various locations for the

application of generating hot spots surrounded by array of

TSVs. Diode sensors are also placed in the region of heat-

ers to measure the temperature distribution of the test

vehicle. Finite element model was also constructed to con-

duct thermal simulations for comparisons against the mea-

surement results. A good agreement of comparison

between the results of simulations and measurements

were obtained.

From another aspect, TSV’s thermal characteristics are

also of interest to apply for thermal design guidelines in

3D IC structure. The aforementioned anisotropic thermal

properties of TSV are particularly important for thermal

[Technical Paper]

Thermal Performance of 3D IC Package with Embedded TSVsRa-Min Tain, Ming-Ji Dai, Yu-Lin Chao, Sheng-Liang Li, Heng-Chieh Chien, Sheng-Tsai Wu, Wei Li,

and Wei-Chung Lo

Industrial Technology Research Institute, Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 31040, Taiwan

(Received July 23, 2012; accepted November 5, 2012)

Abstract

A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement

of thermal resistance from junction to the package case surface (bottom). The thermal resistances for the layers of chips,

micro bumps, underfill resin between chips, and ceramic substrate are also being analyzed with the thermal RC model

theory and the cumulative structure function. The top chip is embedded with through-silicon vias (TSVs) and is thinned

down to 60 μm thick. The bottom chip has no TSV and the thickness is the same as a normal IC chip. Both chips have

the same layout and include two types of heaters. The first heater is designed to emulate a hot spot and is located at the

chip center. The second heater, with heat flux level (uniform heating) close to 1/20 of the first heater, is designed to heat

up the surrounding area of the first heater. A simulation model of the QFP package is developed and a set of equivalent

thermal conductivity correlations in planar (xy) and vertical (z) directions of TSVs are used in order to simplify the

simulation model and shorten the computational time. Comparisons between simulation models show that the result is

accurate for uniform heating condition and satisfactory for hot spot heating condition.

Keywords: 3D IC, Through Silicon Via, Chip Stacking, Thermal Conductivity, QFP Package

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Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012

analysis in design phases. Lau and Yue[9] studied the

equivalent thermal conductivities in planar and vertical

directions for 3D IC structure with TSVs embedded in

stacked chips in simulations. The simulation results of

equivalent thermal conductivities are for the entire chip

embedded with TSVs. However, there is no dielectric layer

assumed between the copper filling and silicon. Thus, the

evaluated values of equivalent thermal conductivities in

planar and vertical directions are both larger than the iso-

tropic thermal conductivity of the silicon. A 3D cell-based

TSV structure is developed to investigate the anisotropic

equivalent thermal conductivity properties by Chien et

al.[1, 2] The TSV cell as shown in Fig. 1 includes a single

cylindrical copper filling and is surrounded with a dielec-

tric layer of SiO2. Then, the copper filling and dielectric

layer are embedded in a rectangular silicon block, which

includes circular copper pads partly cover on its top and

bottom surfaces and connected with the copper filling.

Thermal simulations using CFD tool of ANSYS Icepak

were performed based on the parametric matrix shown in

Table 1. In addition to the parameters used in Lau and

Yue,[9] Table 1 has also included the parameter of SiO2

thickness, which results in a smaller planar equivalent

thermal conductivity and a larger vertical equivalent ther-

mal conductivity of TSV cell than the isotropic thermal

conductivity of silicon. The studies of Chien et al.[1, 2]

derived the empirical correlations of equivalent TSV ther-

mal conductivities in planar and vertical directions. For the

selective chip area having a cluster of TSVs, the TSV cell

can be tiled together and then employ the empirical corre-

lations of planar and vertical equivalent thermal conductiv-

ities for this TSV area. This approach has the advantage of

dramatically reducing the mesh number of 3D IC simula-

tion model and shortening the computational time with

accurate thermal analysis.

Different from the study of Oprins et al.[8] which the

measurement is conducted on a wafer level probe station

and their die stack is mounted on a temperature-controlled

chuck. In present study, we have assembled a two-chip

stacking 3D IC in a QFP package and conducted measure-

ments of thermal resistances from junction to the package

case surface (bottom), Rjc. Both chips have identical

design and are fabricated with 0.18 um CMOS technology.

The top chip is embedded with TSVs and is thinned down

to 60 um thick. The TSV diameter is 30 um and the pitch is

230 um. The bottom chip has no TSV and the thickness is

800 um. Both chips have the same size of 5 × 5 mm2 and

include two types of heaters which are designed with poly-

silicon. For the measurement of Oprins et al.,[8] only top

chip has heaters and they are made by the metal meander

in metal-2 layer of the Back End (BEOL) and for hot spot

heating only. In present study, micro bumps are placed in

between two chips directly under TSVs in order to provide

power to the bottom chip through the top chip’s TSVs.

One temperature sensor diode is embedded at the chip

center surrounded by the hot spot heater. Three other

temperature sensors are located at the chip corners and

one temperature sensor is located at the middle of chip

Fig. 1 Cross-sectional view and structural view of a TSV cell.[1, 2]

Table 1 Parametric matrix of TSV thermal simulations.[1, 2]

DTSV(μm) 10 20 30 40 50

H(μm)10, 20, 30, 50,

100, 15010, 20, 50, 100,

150, 20010, 20, 50, 100,

150, 25010, 20, 50, 100,

150, 25010, 20, 50, 100,

150, 250

P(μm)25, 35, 40, 50, 70, 100, 130

35, 45, 55, 65, 80, 120, 150

45, 55, 65, 75, 100, 150, 200

55, 65, 75, 85, 100, 150, 200

65, 75, 85, 100, 150, 200

tSiO2(μm) 0.2, 0.5, 1.0, 2.0 0.2, 0.5, 1.0, 2.0 0.2, 0.5, 1.0, 2.0 0.2, 0.5, 1.0, 2.0 0.2, 0.5, 1.0, 2.0

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edge. Underfill resin is used in gaps among micro bumps

between the two chips. A simulation model of the QFP

package is also developed and the equivalent thermal con-

ductivity correlations in planar and vertical directions of

TSVs published in Chien et al.[1, 2] are used in order to

simplify the simulation model and the results are com-

pared with those from detailed simulation model.

2. Thermal Test Chip Design and Test VehicleFigure 2 is the circuit view of the thermal test chip,

where two types of heaters are designed in this chip. The

first heater is designed to simulate a hot spot and is located

at the chip center (denoted as R2, inside the yellow square

line) with the size of 1 × 1 mm2. The second heater is

designed to heat up the rest area (denoted as R1, in the

interior area of the white square line) with much less heat

flux level compared to the first heater. One temperature

sensor diode (D3) is placed at the chip center surrounded

by the hot spot heater. Three other temperature sensors

are placed at the chip corners (D1, D4 and D5) and one

temperature sensor (D2) is placed at the middle of chip

edge.

Both R1 and R2 are made of poly-silicon, which has

many applications in VLSI manufacturing and one of its

uses is for gate electrode material in MOS devices. The

electrical conductivity of poly-silicon gate may be changed

by depositing a metal or a metal silicide over the gate.

Thus, poly-silicon can be employed as a resistor, a conduc-

tor or an ohmic contact for junctions. When poly-silicon is

used as a gate resistor, it can act like a heater with proper

circuit design. Figure 3 shows a typical CMOS struc-

ture[10] in a chip where in present study the islands of n+

and p+ as well as the n- well were not fabricated for heaters

(R1 and R2) but for diodes (D1~D5). Once the top chip is

completed with TSV fabrication and is thinned down to 60

um thick, it is mounted on top of the bottom chip which

has no TSV being fabricated inside. As shown in Fig. 4

which is modified from a cross-sectional SEM photo, both

chips are connected with micro-bumps (u-bumps) under-

neath the TSVs and the gap among u-bumps is filled with

underfill resin. The TSVs are at the vicinity of the diode

sensors and interconnect circuits of M1~M4 are laid on top

of the poly-silicon gate and electrically connected with

TSVs. Please note that it appears to be a crack occurred at

the top side of the TSV. This is not a failure of the chip but

is simply a delamination between chip and molding resin

when preparing the sample for cross-sectional SEM photo.

Fig. 2 also shows the 20 × 20 TSVs evenly populated on the

test chip inside the white square line. Not all TSVs are con-

nected with the interconnect circuits and simply act as

thermal TSVs.

The chip-to-chip stack is then assembled in a QFP pack-

age as shown in Fig. 5, where Fig. 5a is the cross-sectional

schematic view of the QFP package and Fig. 5b is a photo

of the package. From Fig. 5b, the top-surface of QFP is a

transparent plastic and the interior of QFP has not been

filled with molding compound. From Fig. 5a, the two-chip

stack is mounted on a ceramic substrate with die attach

Fig. 2 Circuit view of the thermal test chip.

Fig. 3 A typical CMOS structure.[10]Fig. 4 SEM cross-sectional photo of TSVs, micro bump, diode sensors and interconnects.

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material. Leadframes are wire bonded to the pads of top

chip so that power is able to supply from the leads outside

the package and signals of sensors are also able to be

extracted from the leads.

3. Experimental Set UpLike the temperature sensor diodes used in the thermal

test chip of Oprins et al.,[8] diodes must be calibrated for

their temperature sensitivity parameters, i.e. TSP curve.

This curve is a linear relationship for a forward voltage

drop corresponding to a constant and low current over a

range of temperatures, e.g. from 20 to 80 deg. C. Unlike

the calibration method used in Oprins et al.[8], the TSP

curve measurement is performed in a test rig of T3Ster

system from MicRed®,[11] where a cold plate is provided

with thermoelectric cooling/heating device. With accurate

programming, the thermoelectric device is able to main-

tain the cold plate at a constant temperature. The test

setup is shown in Fig. 6. While testing, the bottom of the

QFP is attached to the cold plate and within minutes the

QFP package reaches a thermal equilibrium state. A con-

stant current of 1 mA is then provided to the QFP and the

forward voltage is measured. At least four measurements

are performed from 20 to 80 deg. C so that a linear TSP

curve is obtained as shown in Fig. 7, which results in a

voltage drop slope of –1.55 mV/deg. C.

The thermal resistance measurements are then con-

ducted using T3Ster system, which employs thermal RC

model theory to generate cumulative structure func-

tions[12, 13] where the cumulative thermal capacitance

can be plotted against a function of cumulative resistance.

A differential structure function can be further derived

from the cumulative structure function to identify the

interfaces between sections of different materials. Figure 8

is a sample test results for QFP being heated by only R1

and only R2, respectively, where the Y axis (k) is the deriv-

ative of cumulative thermal capacitance (dCth) over the

derivative of cumulative thermal resistance (dRth). The

peaks correspond to regions of high thermal conduction

such as chips or heatsinks and low points represent

regions of lower thermal conduction like die attach mate-

rial.[14, 15] For hot spot heating (R2) the peaks and low

points looks less obvious than those of the uniform heating

Fig. 5 QFP package schematic view and photo.(b) photo of the package

(a) cross-sectional schematic view

Fig. 6 Experimental setup for TSP curve and Rjc measure-ments.

Fig. 7 TSP curve measured for QFP package.

Fig. 8 Differential structure functions of sample test results.

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(R1) at regions from bottom chip to the bottom surface of

the package. Detailed analysis of this phenomenon is dis-

cussed in the next section. The total thermal resistance of

hot spot heating is about twice as that of the uniform heat-

ing at the same current input because the power density of

hot spot heating is much higher than that of the uniform

heating.

4. Results of MeasurementsFigure 9 shows the cumulative structure function curves

of QFP for both hot spot heating (R2) and uniform heating

(R1) measurements, respectively. For hot spot heating

(R2), the input currents are 200, 300 and 400 mA, corre-

sponding to heat fluxes at 29, 58 and 110 W/cm2, respec-

tively, and resulting in the measured junction tempera-

tures of 31.8, 39 and 53 deg. C, respectively. The measured

thermal resistances (Rjc) are in the range between 23 and

25 K/W, which demonstrate the trend of lower Rjc with

higher heat flux. For uniform heating (R1), 300 and 400

mA are supplied to QFP and the measured junction tem-

peratures are 34 and 42 deg. C, respectively. The mea-

sured thermal resistances (Rjc) are in the range between

10 and 12 K/W, which also demonstrate the trend of lower

Rjc with higher heat flux. Fig. 9 also shows that the Rjc for

hot spot heating is about twice as that of uniform heating.

For thermal resistances (Rth) in regions of different

materials, Fig. 10 shows the results of uniform heating

measurement where the numbers on top of Fig. 10a repre-

sent the thermal resistances (Rth) at different regions.

The Rth for top chip with TSVs is the smallest of all QFP

package structures. The die attach has the largest Rth at

3.66 K/W and the region of micro bump and underfill has

the second largest Rth at 2.49 K/W. The heaters are

located on the top surfaces of chip substrates marked with

red colors in Fig. 10b. From Fig. 10a, the Rth of thin (top)

chip with TSVs is 0.89 K/W and the Rth of thick (bottom)

chip is 1.86 K/W, which is twice as that of the thin chip.

When compared with uniform heating measurements,

the average Rth (Rhs1) of top chip for hot spot heating is

three times as that (Rnhs1) of the top chip for uniform

heating as shown in Fig. 11. However, the peaks and low

points below the top chip become less obvious for hot spot

heating as shown in the circled area in Fig. 11. This phe-

nomenon may have been explained that three dimensional

Fig. 9 Cumulative structure function curves of QFP for both hot spot heating (R2) and uniform heating (R1) measure-ments.

Fig. 10 Results of uniform heating measurement: (a) the numbers on top of figure rep-resent the thermal resistances (Rth) at different regions, (b) the heaters are located on the top surfaces of chip substrates marked with red colors.

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heat-flow occurs in the bottom chip because the hot spot

takes only a small portion of the chip area and the heat

generated in the top chip may flow directly to the bottom

chip with the help of TSVs resulting near perfect one-

dimensional heat transfer. Since there is no TSV in the bot-

tom chip which is also 26 times thicker than the top chip,

the heat can spread laterally and then flows down to the

ceramic substrate forming a realistic three-dimensional

heat flow. Thus, the Rth for the bottom chip at hot spot

heating condition becomes difficult to be identified using

the differential structure function.

5. Thermal Model SimulationsA simulation model for the QFP package of Fig. 5 has

been developed using Flotherm from Mentor Graphics.

Both detailed and equivalent models have been con-

structed for simulations. The correlations developed in

Chien et al.[1, 2] are employed in the simulation for equiv-

alent model. Since the layouts of R1 and R2 heaters are

symmetric in chips, a quadric model is constructed to sim-

plify the computation. Figure 12 illustrates the boundary

conditions of the model where the ambient temperature is

assumed at 25 deg. C and the cold plate, below the sub-

strate (not shown), temperature is also maintained at 25

deg. C. The temperature contour shown in Fig. 12a is the

simulation result of a uniform heating for equivalent model

and Fig. 12b is for hot spot heating of equivalent model.

Figure 13 shows the dif ferent structures between

detailed and equivalent models used in simulations where

the silicon, SiO2, Cu filling, micro bumps and underfill

have to be meshed with different scales in detailed model

as shown in Fig. 13a. For equivalent model as shown in

Fig. 13b, TSV group is treated as an equivalent zone whose

thermal conductivities in planar (kxy) and vertical (kz)

directions can be calculated using the equations (1) and

(2) shown below, respectively, where tSiO2 is the thickness

of SiO2, DTSV the diameter of TSV, P the pitch between

TSVs and H the die thickness.

Fig. 11 Rth of hot spot heating (Rhs1) is three times as that of uniform heating (Rnsh1).

Fig. 12 Contours of temperature simulations (a) uniform heating, (b) hot spot heating.

Fig. 13 Simulation models (a) detailed structure, (b) equiva-lent structure.

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For planar equivalent thermal conductivity,

k tD

PH txy SiO

TSVSiO= ⋅ −( )⋅

⋅ + ⋅−90 148 16020 3 0 1

20 07. . . (1)

For vertical equivalent thermal conductivity,

0 002 0 01 1282. . exp≤ ≤ ⇒ = ⋅

tH

kD

PSiO

zTSV (2)

Where

0 2 0 510 50

200 1 0 77

2. .

. .

µ µµ µ

µ

m t mm D m

H mD P

SiO

TSV

TSV

≤ ≤≤ ≤

≥≤ ≤

The thermal loadings are assumed the same as those

conditions applied in the experiments, that is, the powers

supplied to both top and bottom chips are the same. How-

ever, the heat dissipations via the bond wires are neglected

and the air contained inside the QFP package is also

assumed at 25 deg. C. In addition to the equivalent correla-

tions employed for the TSV equivalent zone, the copper

traces on silicon surfaces and micro bumps surrounded by

underfill have also been assumed for equivalent zones as

shown in Figs. 14 and 15, where kt represent the thermal

conductivity of copper trace and kSB the thermal conductiv-

ity of solder ball or micro bump. Because the thermal con-

ductivity of underfill is one order smaller than that of the

solder ball, the equivalent thermal conductivity in planar

(kxy) direction is neglected.

6. Results of ComparisonsTable 2 shows the comparison results of junction tem-

peratures at top and bottom chips for uniform heating con-

dition between detailed model and equivalent model simu-

lations. The simulations show that the junction

temperature of top chip is higher than that of bottom chip

for both detailed and equivalent models. Table 2 also

shows that for top chip the temperatures result from

detailed model are higher than those from equivalent

model at both power input levels and the differences

between two models increase with increasing power input.

However, for bottom chip the temperatures result from

detailed model are the same as those from the equivalent

model. The maximum temperature difference between

two models is less than 3.6%.

For hot spot heating condition, Table 3 shows the com-

parison results of junction temperatures at top and bottom

chips between detailed model and equivalent model simu-

lations. Similar to the uniform heating condition, the simu-

lation shows that the junction temperature of top chip is

higher than that of bottom chip. However, the difference of

junction temperature between top chip and bottom chip

increases dramatically with increasing power input for

both detailed and equivalent models. This is because the

heat flux for hot spot heating is much higher than that of

the uniform heating condition. Because the top chip is

being thinned down, the planar heat spreading becomes

difficult. In addition, there is also a hot spot heating at the

same location of bottom chip, this makes the top chip tem-

perature increase significantly for hot spot heating. For

simulation results between detailed and equivalent mod-

els, the temperature difference of top chip increases when

power input is increased with the maximum difference

reaching 6.91%. However, for the bottom chip the tempera-

ture difference increases only slightly with increasing

power input.

Fig. 15 Equations of equivalent thermal conductivity for micro bump and underfill.

Fig. 14 Equations of equivalent thermal conductivity for cop-per trace.

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7. DiscussionsAs shown in Tables 2 and 3, the simulation results

between detailed and equivalent models are very close for

both the uniform heating and hot spot heating conditions

with the maximum difference less than 7%. This indicates

that the equivalent model can maintain good accuracy

when compared with the detailed model and have the

advantage of reducing the computational time to 1/10 as

well as saving the computer memory resources. There-

fore, the correlations of TSV equivalent thermal conductiv-

ities for planar and vertical directions are very useful when

they are incorporated into an EDA platform for 3D IC elec-

trical and thermal co-design.

The comparison of measurement results against the

simulation results for both detailed and equivalent models

of uniform and hot spot heating conditions are omitted

because the average temperature between top and bottom

chips from measurement does not represent the true tem-

peratures occurs in top and bottom chips due to the paral-

lel diode circuit arrangement. Therefore, further studies

are needed for either measuring individual junction tem-

perature of top chip and bottom chip or analyze the simula-

tion models a bit more details. One possible method of

modifying the experiment is to rotate the top chip for 90

Table 2 Comparison results of junction temperatures for uniform heating condition between detailed and equivalent simulation models.

Uniform heating condition

Junction Temperature Power = 0.88 W Diff (%) Power = 1.64 W Diff (%)

Simulation–Detailed model (deg. C) Top chip

31.1

–2.25

36.4

–3.57Simulation–Equivalent model (deg. C) Top chip

30.4 35.1

Simulation–Detailed model (deg. C) Bottom chip

29.7

0

33.8

0 Simulation–Equivalent model (deg. C) Bottom chip

29.7 33.8

Note: Diff (%) = [T (Equivalent) – T (Detailed)] / T (Detailed)*100%

Table 3 Comparison results of junction temperatures for hot spot heating condition between detailed and equivalent simula-tion models.

Hot Spot heating condition

Junction TemperaturePower = 0.292 W

Diff (%)Power = 0.584 W

Diff (%)Power = 1.138 W

Diff (%)

Simulation–Detailed model (deg. C) Top chip

35.4

–2.82

45.9

–4.58

66.6

–6.91Simulation–Equivalent model (deg. C) Top chip

34.4 43.8 62.0

Simulation–Detailed model (deg. C) Bottom chip

29.2

0.34

33.5

0.3

41.7

0.48Simulation–Equivalent model (deg. C) Bottom chip

29.3 33.6 41.9

Note: Diff (%) = [T (Equivalent) – T (Detailed)] / T (Detailed)*100%

83


degrees when it is mounted on the bottom chip. Since the

TSV array is symmetric, even though the top chip is

rotated for 90 degrees the TSVs are still aligned between

top and bottom chips. In this setup, each heater does not

share input power with others and each set of diode sen-

sors can have its own TSP curve calibrated.

8. ConclusionsIn present study, we have explored a set of thermal per-

formance measurement of two-chip stacking 3D IC struc-

ture assembled in a QFP package. Thermal test chips of

0.18 um CMOS technology are used for chip-to-chip stack-

ing with TSVs embedded in the top chip. Thermal resis-

tances for regions of different material in vertical direction

of QFP package were able to analyzed using the cumula-

tive structure and differential structure functions. The top

chip results in a smallest thermal resistance and the die

attach is the largest. Hot spot heating condition results in a

package thermal resistance twice as that of uniform heat-

ing condition. Improvement of measurement has been

identified by rotating the top chip for 90 degrees so that

the signals of temperature sensor diodes at top and bottom

chips can be measured individually. Thus, the actual tem-

peratures of top and bottom chips can be obtained.

Simulation models have also been developed for verifica-

tion. Both detailed and equivalent models are constructed

for comparison and analyzing the feasibility of empirical

correlations of Chien et al.[1, 2] for equivalent thermal

conductivities in planar and vertical directions of TSV. Sim-

ulations show both the detailed and equivalent models

result in very good agreement in junction temperature pre-

dictions for hot spot and uniform heating conditions.

AcknowledgementsThe authors would like to thank Mr. Keng-Li Su’s techni-

cal team for their support of test chip design. Without

these test chips, this paper would not be possible. Grati-

tude also extends to Dr. Cha-Hsin Lin’s, Dr. Yu-Hua Chen’s

and Mr. Tai-Hung Chen’s department teams for their sup-

ports of wafer process and chip stack assembly. Without

their assistances, QFP packaging and test results would

not be possible.

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Ra-Min Tain received his Ph.D. degree in mechanical engineering from the University of Ottawa, Canada, in 1995. He has worked in Industrial Technology Research Institute, Hsinchu, Taiwan since 2003. He is now a senior engineer and project manager in Advanced Packaging Technology Division of

Electronics and Optoelectronics Research Laboratory. His research interests include IC feasibility design, microelectronic device and optoelectronic packaging, printed-circuit-board ther-mal solution. His current research activities are thermal analysis of 3D IC and through silicon via structure, advanced packaging modeling, and development of the test chip.

Ming-Ji Dai received his M.S. degree in mechanical engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2004. He has been with the Electronics and Optoelectronics Research Laboratories (EOL), Industrial Technology Research Institute (ITRI), Hsinchu since 2004. His

research interests include thermal design and measurement, thermoelectric technology, power device packaging and 3D IC technology.

Yu-Lin Chao graduated from Southern Taiwan University of Science and Technol-ogy, in 1981. He has been with the Electron-ics and Optoelectronics Research Laborato-ries, Industrial Technology Research Institute, Hsinchu since 1989. His research interests include structural design and anal-

ysis of heat dissipation, advanced packaging of 3D IC intercon-nects.

Sheng-Liang Li received his M.E. degree in mechanical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2006. He has been with the Electronics and Opto-electronics Research Laboratories, Indus-trial Technology Research Institute, Hsinchu since 2006. His areas of interest include

FEM/FEA and measurement for thermal performance in IC/LED packages and design of thermoelectric module for its appli-cations.

Heng-Chieh Chien received his M.S. degree in mechanical engineering from Chung Yuan Christian University, Chung-Li, Taiwan, in 1992, and the Ph.D. degree in engineering and system science from National Tsing Hua University, Hsinchu, Taiwan, in 2010. He has been with the Electronics and Optoelectron-

ics Research Laboratories, Industrial Technology Research Insti-tute, Hsinchu, since 1999. His research interests include mea-surement method development for micro-/nanostructure thermal properties, design and application for thermoelectric devices, and also electronics thermal management.

Sheng-Tsai Wu received his M.S. degree in mechanical engineering from National Cen-tral University, Chung-Li, Taiwan, in 2008. He has work in the Electronics and Opto-electronics Research Laboratories, Indus-trial Technology Research Institute, Hsinchu since 2008. His research interests include

computational modeling and stress analysis, advanced packaging and reliability of 3D IC interconnects.

Wei Li received his M.S. degree in power mechanical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1995. He has worked in Industrial Technology Research Institute, Hsinchu, since 2000, and received Ph.D. degree in the area of green energy harvesting from National Chiao

Tung University, Hsinchu, Taiwan, in 2011. His major researches are stress simulation and reliability evaluation of advanced pack-aging. Now his research interests are stress analysis of 3D IC interconnects and through silicon via structure, advanced pack-aging modeling, and the strain sensing on the stress test chip.

Wei-Chung Lo received his Ph.D. degree in chemistry from National Taiwan University in 1997. Since 1997, he has been with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, where he is currently the director of the Packaging

Technology Division. Dr. Lo is currently the Executive Secretary of the Advanced Stacked-System and Application Consortium, the Program Committee Chair of the International Microsystems, Packaging, Assembly and Circuits Technology Conference, and the Chair of the Advanced Microsystems and Packaging Alliance, the largest package alliance in Taiwan.

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