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Cairo University

Faculty of Engineering

Communications and computer department

VLSI Course

Three Dimensional (3D) silicon integration

Submitted to:

Prof Dr. Mohamed Aboudina

Submitted by:

-Mohamed Ashraf Atwa

-Mohamed Badr

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TABLE OF CONTENTS

Abstract ........................................................................................................................................................................................ 3

Inroduction ................................................................................................................................................................................... 4

Definition ................................................................................................................................................................................. 4

Why 3D Integrated IC.......................................................................................................................................................... 4

Advantages and Challenges.................................................................................................................................................... 5

Advantages ............................................................................................................................................................................ 5

Challenges .............................................................................................................................................................................. 6

TSV... the critical component .................................................................................................................................................... 7

definition.................................................................................................................................................................................. 7

History ...................................................................................................................................................................................... 8

Industrial leaders ................................................................................................................................................................... 8

Wafer thinning............................................................................................................................................................................ 8

Roadmap ..................................................................................................................................................................................... 8

modeling ...................................................................................................................................................................................... 9

compact TSV Model ........................................................................................................................................................... 10

Applications .............................................................................................................................................................................. 11

Samsung 3D NAND gate: ................................................................................................................................................. 11

Design rules .............................................................................................................................................................................. 12

refrences ................................................................................................................................................................................... 13

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ABSTRACT

Applying Moore’s law over the past decades has reached a limit and faced clear challenges of power

consumption and interconnections for billions of transistors. We will be introducing over the research a new

technology that took a great part in solving these challenges and enhancing the IC design, packaging and

even system integration technologies; 3D silicon integration a terminology that was first introduced in 1950s by

William Shockley then in 1990s was its real growth. This terminology simply means “stacking silicon wafers

and/or dies and interconnecting those using TSVs”. This technological shift has great impact on enhancing the

performance of ICs specifically and systems in general, from the huge industrial leaders of this technology are

IBM, Texas Instruments and Intel.

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INRODUCTION

DEFINITION

Three dimensional integrated IC is an integrated circuit manufactured by stacking silicon wafers and/or dies

and interconnecting them vertically using Through Silicon Vias (TSV) so that they behave as a single device to

achieve performance improvements at reduced power and smaller footprint than conventional 2D processes.

WHY 3D INTEGRATED IC

Applying Moore’s law for decades, number of transistors nowadays is counted by billions of transistors per IC

– as we can notice in Fig. 2- which is huge number in factor of power consumption, wiring interconnections and

area. So, it was a must to switch to a new technology that improves the fabrication process and therefore

enhances the IC specifications. We can see in Fig.1 the difference in area consumed that was achieved by 3D

integration technology.

Fig.1 Inverter in 2D and 3D comparison

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Fig.2 Moore’s Law

ADVANTAGES AND CHALLENGES

ADVANTAGES

Footprint:

more functionality within the same space provided in 2D ICs.

Cost:

the new technology improves the yield which reduces cost. Moreover, it reduces the fabrication cost

because the number of dies needed to be tested now is much less than in 2D.

Heterogeneous Integration:

modern ICs include a number of heterogeneous functions such as memory, sensing, data transmission

and data processing. Incorporating these functions into a single die requires different fabrication

processes which is complex and costly operations. 3D integration offers the potential to merge once

incompatible fabrication processes into a stacked 3D system.

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Shorter interconnects:

the average wire length reduced in 3D integration and therefore less delay, higher speed and less

capacitance effect.

Less Power consumption

Noise

less noise contributions due to shorter interconnects

CHALLENGES

Alignment

Wafer thinning

Bonding (roughness and cleanliness)

Fig.3 Fabrication procedure in 3D integration

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TSV... THE CRITICAL COMPONENT

DEFINITION

TSV (Through Silicon Vias) is a cylindrical structure composed of either copper, aluminum, tungsten r polysilicon.

It joins two separately processed wafers, each additional plane requires another set of TSV.

Although it took the cylindrical shape, but sometimes it is tapered from a side with range of 0o to 15o

depending on the fabrication process as we can see in Fig. 3. Picture (A) is the normal cylindrical TSV while

picture (B) is tapered.

Fig. 4 TSV

Fig.5 Top View and cross section of TSV

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HISTORY

The term TSVs isn’t a new one, it was first introduced by William Shockley early in 1950s, then in the 1990s

started its exponential growth.

INDUSTRIAL LEADERS

Some of the leading industrial companies are IBM, Intel and Texas Instruments.

The formation of TSV has 5 major formation steps; Via formation, Via filling, wafer thinning, wafer bonding

then wafer bonding.

The most important and critical step pf these is the wafer thinning. So, we will discuss it briefly.

WAFER THINNING

First, wafer are thinned by a mechanical grinding process with mesh size #325 then another process is

performed with finer mesh size of #2000 for smoother surface.

The wafer thinning step is considered the most expensive of them all, it nearly costs 20% of TSV fabrication

cost.

The buried oxide layer acts as an etch stop for the substrate thinning for removal of SI substrate.

One of the most important benefits of wafer thinning process is that it improves alignment.

ROADMAP

The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a

group of semiconductor industry experts. These experts are representative of the sponsoring

organizations which include the Semiconductor Industry Associations of the United States, Europe,

Japan, South Korea and Taiwan.

The ITRS Roadmap for Assembly and Packaging [ITRS09] states that “Modeling of 3D structures”,

“Through Silicon Vias (TSV)” and “3D tools for System in Package (SiP)” are among the difficult

challenges for the decade to come. Multiple 3D techniques are being developed, driven by the

necessity of higher densities, shorter interconnects and lower power.

Through Silicon Vias (TSVs) are used to connect the different levels in several of these technologies:

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Coarse TSV are used for die-to-ball interconnection, such as in Wafer-Level Packaging.

Coarse TSV have a pitch of the order of 100µm which is expected to decrease to about

40µm by 2020

Fine TSV are used for die to die interconnect and have a pitch of several micrometers,

projected to be as low as 2µm by 2020

Advanced substrates, silicon interposers and redistribution layers all have feature dimensions in the

micrometer range, as small as 10µm and as large as several hundreds of micrometers and they are

not expected to shrink by more than perhaps by a factor of two in this decade. These 3D structures

are large compared to on-chip dimensions and need to be modeled electromagnetically to take into

account inductance and high-frequency effects. In addition, silicon resistivity, loss and capacitance

(potentially depletion capacitance in silicon) need to be modeled.

MODELING

Silicon as an “interposer” that serves as a substrate to mount several dies as shown in the Figure

presents some unique electromagnetic challenges. Silicon is a poor dielectric and also a potential

semiconductor. The main concern is to model the coupling between vias in the silicon (TSV) and

between vias and the metal redistribution layer (RDL) on the die that connects to it.

The basic idea of analytical models is to generate an equivalent circuit that models the coupling

effects and the losses as shown in the Figure. Note that due to wave effects, in particular due the skin

effect, the lumped parameters are frequency dependent.

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COMPACT TSV MODEL

Analytical compact models however have their limitations. In practice, there is little use in modeling

just pairs of TSV; the typical silicon interposer will involve modeling of arrays of TSV spaced

irregularly. In addition TSVs also interact with the RDL, requiring the analysis of the coupled RDL-TSV

system.

In principle, we can model these structures as 3 regions: Metal (conductor), SiO2 (dielectric) and

Silicon (imperfect dielectric with conductivity and permittivity). Additional complexity is introduced by

the Metal (Via) – Oxide (TSV liner) – Semiconductor (Silicon Interposer) structure. The metal acts as

the electrode of a MOS capacitor. The capacitance of this MOS capacitor can be dependent on the

voltage Vvs between the via and the silicon interposer and on the frequency of the signal.

An accurate electrical modeling of the TSV arrays and merged TSV-RDL structures requires a

complete 3D electromagnetic analysis. 3D full-wave simulation engines, that accurately capture the

frequency dependent dielectric property of silicon with appropriate conductivity and model the

depletion property for p-substrates to generate broadband S-parameters, can be used for this

purpose. However, 3D full wave solvers simulate many frequency points in discrete or adaptive

schemes and are time consuming.

A 3D quasi-static analysis in contrast extracts resistance (R), inductance (L), conductance (G), and

capacitance (C) each independent of each other at a given frequency point. 3D quasi-static analysis

is therefore much quicker. In some cases, to account for the skin effect, R and L are extracted at DC

and at high frequency and an equivalent circuit is synthesized. The C is extracted in an electrostatic

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formulation with only the real part of the dielectric constant and is therefore assumed constant over

the entire frequency spectrum. Hence, in its original form, a quasi-static tool fails to model the

accurate broadband characteristics of TSV interactions.

As the TSV is the critical component for interconnecting the separate device planes, accurate electrical

characterization of the impedance of the TSV is necessary to effectively model the inter-plane signal

delay and power characteristics, to better understand the impedance of the power network, and to

analyze the effects of inter- and intra-plane clock skew and slew. The primary objective is to develop

an equivalent electrical 𝜋 model of the TSV, These models are often used for simulation in SPICE.

APPLICATIONS

SAMSUNG 3D NAND GATE:

Worldwide data transferal continues to grow at an explosive rate. The amount of data being shared

by average users on a daily basis is at an all-time high:

Facebook: 250 billion photos uploaded per day

Twitter: 100,000 new tweets per minute

YouTube: 30 hours of video uploaded per minute

flickr: 3,000 photos uploaded per minute

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foursquare: over 2,000 check-ins per minute

Even semiconductor and memory chip development add to this increase in data sharing. Currently,

these fields account for the transferal of approximately 4 Exabytes of data per month. However, that

number is projected to increase to 10 Exabytes per month in 2016. Improvements must be made to

existing memory to rise to the challenge of such rapid data growth.

Samsung's new 3D V-NAND will be used for a wide range of consumer electronics and enterprise

applications, including solid state drives (SSDs). Consumers can expect their handheld computers to

perform better for longer periods of time between charges. Datacenter managers can expect

increased productivity and longevity while saving on their power bill.

Over the past 15 years, NAND Flash memory cell structure has gone from 120nm scale to 19nm

scale. Along with this drastically shrinking structure, capacity has grown by 100 times. Just how is

Samsung V-NAND Flash memory able to offer 100 times the capacity in only 1/10th the same area?

That's where the V in V-NAND comes in, as Samsung stacks the cells vertically.

Samsung's three-dimensional Vertical NAND Flash memory (3D V-NAND) breaks free of the scaling

limit for existing NAND Flash technology. Samsung has developed a new structure through its first 24-

layer V-NAND.

DESIGN RULES

We note that for system integration, technology considerations include 1) design, 2) architecture, 3)

design and modeling tools, 4) semiconductor technology, 5) package technology, 6) assembly

technology, 7) test technology, 8) power delivery and cooling technology, 9) module form factor, and

10) reliability requirements. As mentioned, for 3D systems, we must consider design redundancy for

interconnections, die size, manufacturing yield, cost, and test methodologies for manufacturing and

product applications.

Advancement of 3D technology requires an understanding of the boundaries that affect its use. Thus,

at its start, 3D design rules, physical structures, materials, processes, and tools must be explored to

understand what may be possible as well as practical to meet targeted product, electrical,

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mechanical, and thermal objectives for products. Where TSV and SSI interconnection density targets

are necessary, experiments need to be conducted to define practical ground rules for 3D technology.

The wide range of technology elements (numbered 1 through 10 at the end of the previous section)

must be considered when developing a 3D technology that goes far beyond existing design rules in

use today. At the same time, developing practical design rules for applications needs to take into

account materials, structures, processes, and tooling that can lead to a desired low-cost product with

high yield.

REFRENCES

Three dimensional silicon integration, by J. U. Knickerbocker, IBM 2008

http://www.samsung.com/global/business/semiconductor/minisite/SSD/global/html/ssd850pro/3dv

nand.html

http://www.eetimes.com/document.asp?doc_id=1279711&page_number=1

Characterization and Modeling of TSV Based 3-D Integrated Circuits, by Ioannis Savidis.

http://www.eetimes.com/document.asp?doc_id=1279711&page_number=1