178220 Digital Logic Design @Department of Computer Engineering KKU.1 Chapter 5 Sequential Systems...
-
Upload
jasper-franklin -
Category
Documents
-
view
216 -
download
0
Transcript of 178220 Digital Logic Design @Department of Computer Engineering KKU.1 Chapter 5 Sequential Systems...
178220 Digital Logic Design @Department of Computer Engineering KKU. 1
Chapter 5 Sequential Systems
Latches and Flip-flopsSynchronous CounterAsynchronous Counter
178220 Digital Logic Design @Department of Computer Engineering KKU.
2
Introduction
Up to now everything has been combinational – the output at any instant of time depends only on what inputs are at the time.
Later on of this course: sequential systems – systems that have memory. Thus, the output will depend not only on the present input but also on the past history – what has happened earlier.
178220 Digital Logic Design @Department of Computer Engineering KKU.
3
Clock Signals Two versions of a clock signal are as
below. In the first, the clock signal is 0 half of the time and 1 half of the time. In the second, it is 1 for a shorter part of the cycle.
The period of the signal (T on the diagram) is the length of one cycle. The frequency is the inverse (1/T).
T
178220 Digital Logic Design @Department of Computer Engineering KKU.
4
Conceptual View of a Sequential System
Memory
Combinational Logic
q1
qm
z1
zk
......
...
x1
xn
...
Clock
178220 Digital Logic Design @Department of Computer Engineering KKU.
5
Terminology State: what is stored in memory. State table: shows for each input
combination and each state, what the output is and what the next state is – what is to be stored in memory after the next clock.
State diagram (or state graph): a graphical representation of the state table.
(Finite) State Machine
178220 Digital Logic Design @Department of Computer Engineering KKU.
6
State Table and State Diagram
q q* z
x=0 x=1 x=0 x=1
A A B 0 0
B C B 1 0
C A D 0 0
D C C 0 0
A
D
B C
0/0
0/0
0/11/0
1/0 1/00/01/0
X/0
State table State diagram
present state
next state output
input
178220 Digital Logic Design @Department of Computer Engineering KKU.
7
The next state is a function of the present state and the input.
The output also depends on the present state (and on the input). It may change on a clock transition, but it may change where the input changes, as well.
In state diagram, there must be one path from each state for each possible input combination.
178220 Digital Logic Design @Department of Computer Engineering KKU.
8
Moore vs. Mealy Models
Moore model circuit (state-based) the outputs depend on the present state of the system but not on the inputs.
Mealy model circuit (input-based) the outputs depend on the inputs as well as the present state of the system.
178220 Digital Logic Design @Department of Computer Engineering KKU.
9
Moore: A system with no input and three outputs, that represent a number from 0 to 7, such that the outputs cycle through the sequence 0 3 2 4 1 5 7 and repeat on consecutive clock inputs.
Mealy: A system with two inputs,X1 and X2, and three outputs, Z1, Z2 and Z3, that represent a number from 0 to 7, such that the output counts up if X1=0 and down if X1=1 and recycles if X2=0 and saturates if X2=1. Thus, the following output sequences might be seen:
178220 Digital Logic Design @Department of Computer Engineering KKU.
10
X1=0 X2=0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7..
X1=0 X2=1 0 1 2 3 4 5 6 7 7 7 7 7 7..
X1=1 X2=0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0..
X1=1 X2=1 7 6 5 4 3 2 1 0 0 0 0 0 0..
178220 Digital Logic Design @Department of Computer Engineering KKU.
11
Design Process of Sequential Systems Table 5.1 Page 338
State table Timing trace State table with binary states Truth table K-map equations
178220 Digital Logic Design @Department of Computer Engineering KKU.
12
Design Process of Sequential Systemsq q* z
x=0 x=1 x=0 x=1
A A B 0 0
B C B 1 0
C A D 0 0
D C C 0 0
clk 1 2 3 4 5 6 7 8 9 10 11 12
x 0 1 1 0 1 0 1 0 1 1
q A A B B C D C D C D C
z 0 0 0 1 0 0 0 0 0 0 0 0
State table
Timing trace
178220 Digital Logic Design @Department of Computer Engineering KKU.
13
Design Process of Sequential Systems
q1 q1*q2* z
x=0 x=1 x=0 x=1
00 00 01 0 0
01 10 01 1 0
10 00 11 0 0
11 10 10 0 0
State assignment
State table with binary states
q q1 q2
A 0 0
B 0 1
C 1 0
D 1 1
178220 Digital Logic Design @Department of Computer Engineering KKU.
14
Design Process of Sequential Systems
x q1 q2 q1* q2* z
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 1 0 0State assignment
Truth table for system design
211 qxxq*q
11x
q2
1 1
q2’q2’
x’
q1q1’
q1q2
x
178220 Digital Logic Design @Department of Computer Engineering KKU.
15
Latches and Flip-flops A latch is a binary storage device, composed
of two or more gates, with feedback.
The latch can store either a 0 (Q = 0 and P = 1) or a 1 (Q = 1 and P = 0)
The P output is just labelled
Q
178220 Digital Logic Design @Department of Computer Engineering KKU.
16
Latches (cont.)•Edge-triggered
• rising/leading edge-triggered• falling/trailing edge-triggered
•Level-triggered• high level-triggered• low level-triggered
178220 Digital Logic Design @Department of Computer Engineering KKU.
17
Latches (cont.) Example: a latch constructed with 2 NORs.
QSP
S P
R QPRQ
QP PQ
The equations for this system:and
Normal storage stage both inputs inactive (S = R = 0).
and
178220 Digital Logic Design @Department of Computer Engineering KKU.
18
Latches (cont.)
S P
R Q
01Q)(1P 100)(0Q
Case 1: If S=1 and R=0
100)(0P 01P)(1Q
Case 2: If S=0 and R=1
01Q)(1P 01P)(1Q
Case 3: Finally, the flip-flop is not operated with both S and R active (=1).
178220 Digital Logic Design @Department of Computer Engineering KKU.
19
Latches (cont.)
D flip-flops (Delay flip-flops)SR flip-flops (Set/Reset flip-flops)T flip-flops (Toggle flip-flops)JK flip-flops
178220 Digital Logic Design @Department of Computer Engineering KKU.
20
D flip-flops
D q q*
0 0 0
0 1 0
1 0 1
1 1 1 0 1
1
10
0
D
D q*
0 0
1 1
q*=D
178220 Digital Logic Design @Department of Computer Engineering KKU.
21
D flip-flops (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
22
D flip-flops (cont.)
Two D flip-flops
178220 Digital Logic Design @Department of Computer Engineering KKU.
23
D flip-flops (cont.)With Clear and Preset
D q q*
0 1 X X 1 Static
1 0 X X 0 Immediate
0 0 X X - Not allowed
1 1 0 0 0
Clocked
(as before)
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
PRE CLR
178220 Digital Logic Design @Department of Computer Engineering KKU.
24
D flip-flops + Clear and Preset (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
25
SR flip-flopsS R q q*
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 -
1 1 1 -
S R q*
0 0 q
0 1 0
1 0 1
1 1 -
0 1
10
001001
0001
SR
qRSq*
1x1q
R
x
R’R’
1q’
SS’ SRq
Not allo
wed
178220 Digital Logic Design @Department of Computer Engineering KKU.
26
SR flip-flops (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
27
T flip-flopsT q q*
0 0 0
0 1 1
1 0 1
1 1 0
T q*
0 q
10 1
1
01
0
T
q
q*=Tq
178220 Digital Logic Design @Department of Computer Engineering KKU.
28
JK flip-flopsJ K q q*
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
J K q*
0 0 q
0 1 0
1 0 1
1 1 qKqJq*
0 1
1011
001001
11
0001
JK
11q
K
1
K’K’
1q’
JJ’ JKq
q
178220 Digital Logic Design @Department of Computer Engineering KKU.
29
JK flip-flops (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
30
Analysis of Sequential Systems
Figure 5.21 Page 342 Circuit Equations State table Timing trace Timing diagram Equations A*,B* State diagram
178220 Digital Logic Design @Department of Computer Engineering KKU.
31
Flip-flop Design Techniques
x q1 q2 q1* q2* z
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 1 0 1
From the truth table, it’s clear that
We need to create the appropriate flip-flop design table to obtain a truth table for the flip-flop inputs.
z=q1q2
q q* Input(s)
0 0
0 1
1 0
1 1
Main truth table
•D flip-flops•JK flip-flops•SR flip-flops•T flip-flops
next
178220 Digital Logic Design @Department of Computer Engineering KKU.
32
Design with D Flip-flop
D q*
0 0
1 1
q q* D
0 0 0
0 1 1
1 0 0
1 1 1
x q1 q2 D1=q1* D2=q2*
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 1
1 1 1 1 0
From the main truth table
178220 Digital Logic Design @Department of Computer Engineering KKU.
33
Design with D Flip-flop (cont.)
122 121 xqqxDxqxqD
x
q1q2 0 1
00
01 1
11 1
10 1
x
q1q2 0 1
00 1
01
11 1
10 1
178220 Digital Logic Design @Department of Computer Engineering KKU.
34
Implementation using D Flip-flops
back
178220 Digital Logic Design @Department of Computer Engineering KKU.
35
Design with JK Flip-flop J K q*
0 0 q
0 1 0
1 0 1
1 1
q q* J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
x q1 q2 q1* q2* J1 K1 J2 K2
0 0 0 0 0 0 X 0 X
0 0 1 1 0 0 X X 1
0 1 0 0 0 X 1 0 X
0 1 1 1 0 X 1 X 1
1 0 0 0 1 0 X 1 X
1 0 1 0 1 1 X X 1
1 1 0 1 1 X 0 1 X
1 1 1 1 0 X 0 X 0
q
From the main truth table
178220 Digital Logic Design @Department of Computer Engineering KKU.
36
Design with JK Flip-flop (cont.)
122
121
qxK ;x J
xK ; xqJ
x
q1q2 0 1
00
01 1
11 X X
10 X X
x
q1q2 0 1
00 X X
01 X X
11 1
10 1
x
q1q2 0 1
00 1
01 X X
11 X X
10 1
x
q1q2 0 1
00 X X
01 1 1
11 1
10 X X
J1 K1 J2 K2
back
178220 Digital Logic Design @Department of Computer Engineering KKU.
37
Design with SR Flip-flop S R q*
0 0 q
0 1 0
1 0 1
1 1 -
q q* S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
x q1 q2 q1* q2* S1 R1 S2 R2
0 0 0 0 0 0 X 0 X
0 0 1 1 0 0 X 0 1
0 1 0 0 0 0 1 0 X
0 1 1 1 0 0 1 0 1
1 0 0 0 1 0 X 1 0
1 0 1 0 1 1 0 0 1
1 1 0 1 1 X 0 1 0
1 1 1 1 0 X 0 X 0
From the main truth table
178220 Digital Logic Design @Department of Computer Engineering KKU.
38
Design with SR Flip-flop (cont.)
21222
121
qqxR ; qxS
xR ; xqS
x
q1q2 0 1
00
01 1
11 X
10 X
x
q1q2 0 1
00 X X
01 X
11 1
10 1
x
q1q2 0 1
00 1
01
11 X
10 1
x
q1q2 0 1
00 X
01 1 1
11 1
10 X
J1 K1 J2 K2
back
178220 Digital Logic Design @Department of Computer Engineering KKU.
39
Design with T Flip-flop
T q*
0 q
1
q q* T
0 0 0
0 1 1
1 0 1
1 1 0
x q1 q2 q1* q2* T1 T2
0 0 0 0 0 0 0
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 1 1 0 1 1
1 0 0 0 1 0 1
1 0 1 0 1 1 1
1 1 0 1 1 0 1
1 1 1 1 0 0 0
From the main truth table
q
178220 Digital Logic Design @Department of Computer Engineering KKU.
40
Design with T Flip-flop (cont.)
21222 2111 qqxqxqxTqqxqxT
x
q1q2 0 1
00
01 1
11 1
10 1
x
q1q2 0 1
00 1
01 1 1
11 1
10 1
back
178220 Digital Logic Design @Department of Computer Engineering KKU.
41
Quick method for JK
*qJ
J0K1Jq*
*qK
K1K0Jq*
Because
Notice that when q=0
And when q=1
qKqJq*
178220 Digital Logic Design @Department of Computer Engineering KKU.
42
Quick method for JK (cont.)state table to maps
178220 Digital Logic Design @Department of Computer Engineering KKU.
43
Quick method for JK (cont.)
First column of J1 and K1
Second column of J1 and K1
Conventional q q* J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
178220 Digital Logic Design @Department of Computer Engineering KKU.
44
Quick method for JK (cont.)Computation of J2 and K2 Conventional
178220 Digital Logic Design @Department of Computer Engineering KKU.
45
Quick method for JK (cont.)Computation of J1 and K1 Quick method
178220 Digital Logic Design @Department of Computer Engineering KKU.
46
Design of Synchronous Counters Design a decimal or
decade counter using JK flip-flops:
D C B A D* C* B* A*
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 x x x x
… … … … … … … …
1 1 1 1 X x x x
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, …
178220 Digital Logic Design @Department of Computer Engineering KKU.
47
Design of Synchronous Counters (cont.)D
DCBA
X 1
X
1 X X
X X
D
B
CC
A
C
A
BA
D DCBA
1 X
1 X
1 X X
1 X X
D
B
CC
A
C
A
BA
D DCBA
X
1 1 X
X X
1 1 X X
D
B
CC
A
C
A
BA
D DCBA
1 1 X 1
X
X X
1 1 X X
D
B
CC
A
C
A
BA
D* C*
B* A*
178220 Digital Logic Design @Department of Computer Engineering KKU.
48
D DCBA
X 1
X
1 X X
X X
D
B
CC
A
C
A
BA
D DCBA
X X
X X
1 X X
X X
D
B
CC
A
C
A
BA
D DCBA
X X X
X X X 1
X X X X
X X X X
D
B
CC
A
C
A
BA
D*D* JJDD
KKDD
AK ;CBA J DD
From the main truth table of the D*
Design of Synchronous Counters (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
49
Design of Synchronous Counters (cont.)D
DCBA
1 X
1 X
1 X X
1 X X
D
B
CC
A
C
A
BA
D DCBA
X X
X X
1 X X X
X X X
D
B
CC
A
C
A
BA
D DCBA
X X X
X X X
X 1 X X
X X X
D
B
CC
A
C
A
BA
C*C* JJCC
KKCC
BAKJ CC
From the main truth table of the C*
178220 Digital Logic Design @Department of Computer Engineering KKU.
50
Design of Synchronous Counters (cont.)D
DCBA
X
1 1 X
X X
1 1 X X
D
B
CC
A
C
A
BA
D DCBA
X
1 1 X
X X X X
X X X X
D
B
CC
A
C
A
BA
D DCBA
X X X X
X X X X
1 1 X X
X X
D
B
CC
A
C
A
BA
B*B* JJBB
KKBB
AK ;A DJ BB
From the main truth table of the C*
178220 Digital Logic Design @Department of Computer Engineering KKU.
51
Design of Synchronous Counters (cont.)D
DCBA
1 1 X 1
X
X X
1 1 X X
D
B
CC
A
C
A
BA
D DCBA
1 1 X 1
X X X X
X X X X
1 1 X X
D
B
CC
A
C
A
BA
D DCBA
X X X X
1 1 X 1
1 1 X X
X X X X
D
B
CC
A
C
A
BA
A*A* JJAA
KKAA
1K J AA
From the main truth table of the A*
178220 Digital Logic Design @Department of Computer Engineering KKU.
52
Example: A Base-16 CounterD C B A D* C* B* A* remark
0 0 0 0 0 0 0 1 01
0 0 0 1 0 0 1 0 12
0 0 1 0 0 0 1 1 23
0 0 1 1 0 1 0 0 34
0 1 0 0 0 1 0 1 45
0 1 0 1 0 1 1 0 56
0 1 1 0 0 1 1 1 67
0 1 1 1 1 0 0 0 78
1 0 0 0 1 0 0 1 89
1 0 0 1 1 0 1 0 9A
1 0 1 0 1 0 1 1 AB
1 0 1 1 1 1 0 0 BC
1 1 0 0 1 1 0 1 CD
1 1 0 1 1 1 1 0 DE
1 1 1 0 1 1 1 1 EF
1 1 1 1 0 0 0 0 F0
178220 Digital Logic Design @Department of Computer Engineering KKU.
53
Example: A Base-16 Counter (cont.)
JD = KD = CBA
D DCBA
1 1
1 1
1 1
1 1
D
B
C
A
C
A
BA
D DCBA
1 1
1 1
1 1
1 1
D
B
CC
A
C
A
BA
JC = KC = BA
178220 Digital Logic Design @Department of Computer Engineering KKU.
54
Example: A Base-16 Counter (cont.)
JB = KB = A
D DCBA
1 1 1 1
1 1 1 1
D
B
CC
A
C
A
BA
D DCBA
1 1 1 1
1 1 1 1
D
B
CC
A
C
A
BA
JA = KA = 1
178220 Digital Logic Design @Department of Computer Engineering KKU.
55
Example: An Up/Down CounterX C B A C* B* A* remark
0 0 0 0 0 0 1 01
0 0 0 1 0 1 0 12
0 0 1 0 0 1 1 23
0 0 1 1 1 0 0 34
0 1 0 0 1 0 1 45
0 1 0 1 1 1 0 56
0 1 1 0 1 1 1 67
0 1 1 1 0 0 0 70
1 0 0 0 1 1 1 07
1 0 0 1 0 0 0 10
1 0 1 0 0 0 1 21
1 0 1 1 0 1 0 32
1 1 0 0 0 1 1 43
1 1 0 1 1 0 0 54
1 1 1 0 1 0 1 65
1 1 1 1 1 1 0 76
JA = KA = 1
JB = KB = xA + xA
JC = KC = xBA + xBA
178220 Digital Logic Design @Department of Computer Engineering KKU.
56
Example: 0, 3, 2, 4, 1, 5, 7, and repeat
q1 q2 q3 q1* q2* q3* remark
0 0 0 0 1 1 03
0 0 1 1 0 1 15
0 1 0 1 0 0 24
0 1 1 0 1 0 32
1 0 0 0 0 1 41
1 0 1 1 1 1 57
1 1 0 X X X 6X
1 1 1 0 0 0 70
0
7 3
2
4 61
5
178220 Digital Logic Design @Department of Computer Engineering KKU.
57
Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
58
Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)
1 2 3 2 3 1 2 3 2 3 1
2 3
2 1 2 3 1 2 3 2 2 3
3 2 3 2
1 1 2 3 2 3 1 2 1
1 2
1
3
2 1 3 1 3
3 2 3 2 3
1 2 3 2
2
3 1 3 2
2 1 3 1 3 2 1 3
3 2 3
S q q q q R q q q q S
q q
S q q q q q q R q q
S q R q
T q q q q q q q q q
T q q q q
T q q q q
J q q q q K q q
J q
q q
q q
q q q K q q
J q K q2
178220 Digital Logic Design @Department of Computer Engineering KKU.
59
Design of Asynchronous Counters
Page 350…. Figure 5.31(2-bit counter)&5.32(timing delay) Advantage:
Simplicity of the hardware no combinational logic required
Disadvantage: Speed
178220 Digital Logic Design @Department of Computer Engineering KKU.
60
Derivation of State tables and State Diagrams
Consider the problem:
Another way of wording this same problem is
A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times.
A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times.
178220 Digital Logic Design @Department of Computer Engineering KKU.
61
A sample input/output trace is
x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1
z 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0
q1*q2* z
q1 q2 x=0 x=1 x=0 x=1
0 0 0 0 0 1 0 0
0 1 1 0 1 1 0 0
1 0 0 0 0 1 0 0
1 1 1 0 1 1 0 1
First approach: save the previous 2 inputs.
Knowing them and the present input output.
Just discard the older input stored in memory and store the newer one plus the current input.
178220 Digital Logic Design @Department of Computer Engineering KKU.
62
Second approach: store in memory the number of consecutive 1’s as follows: AA none, that is, the last input was 0 BB one CC two or more q* z
q x=0 x=1 x=0 x=1
A
B
C
A
A
A
B
C
C
0 0
0 0
0 1
A
B C
0/0
1/0
no 1’s
one 1
two or more 1’s
0/0
1/1
0/0
1/0
178220 Digital Logic Design @Department of Computer Engineering KKU.
63
The second approach requires only 3 states, whereas the first requires 4. Both, however, use 2 flip-flops.
Consider: the system produces a 1 if the input has been 1 for 25 consecutive clock times.
Now the first approach requires to store the last 24 inputs and a state table of 224 rows.
The second approach requires 25 states which can be coded with 5 flip-flops.