101'1 Digital Systems C6.pdf

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Dept. of Applied Electronics Technology, NTNU 6.0 6.0 Registers and Counters Registers and Counters 蔡政翰, Jeng-Han Tsai jht i@ t d t jhtsai@ntnu.edu.tw http://web.ntnu.edu.tw/~jhtsai/ 1 Dept. of Applied Electronics Technology, NTNU 6-1 Registers 6-1 Registers A n-bit register n flip-flops capable of storing n bits of binary information 4-bit register Fig. 6.1 2 Fig. 6.1 Four-bit register

Transcript of 101'1 Digital Systems C6.pdf

  • Dept. of Applied Electronics Technology, NTNU

    6.06.0Registers and CountersRegisters and Counters

    , Jeng-Han Tsaijht i@ t d [email protected]

    http://web.ntnu.edu.tw/~jhtsai/

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    Dept. of Applied Electronics Technology, NTNU

    6-1 Registers6-1 RegistersA n-bit register

    n flip-flops capable of storing n bits of binary information4-bit register

    Fig. 6.1

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    Fig. 6.1Four-bit register

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    4-bit register with parallel loadg pload'

    load

    Fig 6 2Fig. 6.2Four-bit register with parallel

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    with parallel load

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    6-2 Shift Registers6-2 Shift RegistersShift register

    a register capable of shifting its binary information in one or both directions

    Simplest shift register

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    01 10

    11

    01

    Fig. 6.3

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    Fig. 6.3Four-bit shift register

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    Serial transfer vs. Parallel transferSerial transfer

    Information is transferred one bit at a timeshifts the bits out of the source register into the destination register

    Parallel transfer:All the bits of the register are transferred at the same time

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    Example: Serial transfer from reg A to reg Bp g g

    Fig. 6.4

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    gSerial transfer from register A to register B

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    Example: Serial transfer from reg A to reg BExample: Serial transfer from reg A to reg B

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    Serial addition using D flip-flopsSerial addition using D flip flops

    01011 0

    101000

    1 01

    1010

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    10011?001

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    Fig. 6.5Serial adder

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    Serial adder

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    Serial adder using JK flip-flopsg p p

    JQ = x yK ( )

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    KQ = x y = (x + y)S = x y Q

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    Circuit diagramJQ = x yKQ = x y = (x + y)S QS = x y Q

    CiCi

    Fi 6 6

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    Fig. 6.6Second form of serial adder

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    Universal Shift RegisterUnidirectional shift registerBidirectional shift registerBidirectional shift registerUniversal shift register:

    has both direction shifts & parallel load/out capabilitieshas both direction shifts & parallel load/out capabilities

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    Capability of a universal shift register:1 A l t l t l th i t t 01. A clear control to clear the register to 0.2. A clock input to synchronize the operations.3 A shift right control to enable the shift right operation and3. A shift-right control to enable the shift right operation and

    the serial input and output lines associated w/ the shift right.4. A shift-left control to enable the shift left operation and the f f p

    serial input and output lines associated w/ the shift left.5. A parallel-load control to enable a parallel transfer and the n

    ll l i li i d / h ll l fparallel input lines associated w/ the parallel transfer.6. n parallel output lines.7 A control state that leaves the information in the register7. A control state that leaves the information in the register

    unchanged in the presence of the clock.

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    Example: 4-bit universal shift registerExample: 4 bit universal shift register

    Fig 6 7

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    Fig. 6.7Four-bit universal shift register

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    Function table !

    Clear s1 s0 A3+ A2+ A1+ A0+ (operation)C ea s1 s0 3 2 1 0 (ope at o )

    0 0 0 0 0 Clear1 0 0 A A A A N h e1 0 0 A3 A2 A1 A0 No change1 0 1 sri A3 A2 A1 Shift right1 1 0 A A A sli Shift left1 1 0 A2 A1 A0 sli Shift left1 1 1 I3 I2 I1 I0 Parallel load

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    Function Table Function Table

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    AA A1A2

    A0

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    Fig. 6.7 Four-bit universal shift register (continued)

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    6-3 Ripple Counters6-3 Ripple CountersCounter:

    a register that goes through a prescribed sequence of statesupon the application of input pulses

    Input pulses: may be clock pulses or originate from some external source

    The sequence of states: may follow the binary number sequence ( Binary counter) orthe binary number sequence ( Binary counter) orany other sequence of states

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    Categories of counters1.Ripple counters

    The flip-flop output transition serves as a source for triggering other flip-flops

    no common clock pulse (not synchronous)

    2 S h t2.Synchronous counters:The CLK inputs of all flip-flops receive a common clock

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    Example: 4-bit binary ripple counter Binary count sequence: 4-bit

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    10

    Fig. 6.8 Four-bit binary ripple

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    y ppcounter

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    BCD ripple counterBCD ripple counter

    Fig. 6.9 State diagram of a decimal BCD counter

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    g

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    The circuitThe circuit

    Fig. 6.10 BCD ripple counter

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    pp

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    Three-decade BCD counterThree-decade BCD counter

    Fig. 6.11 Block diagram of a three decade decimal BCD counterBlock diagram of a three-decade decimal BCD counter

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    6-4 Synchronous Counters6-4 Synchronous CountersSync counter

    A common clock triggers all flip-flops simultaneously

    Design procedureapply the same procedure of sync seq cktspp y p y qSync counter is simpler than general sync seq ckts

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    4-bit binary countery

    C_en A0_ 0

    C_en A0 A1

    C_en A0 A1 A2

    Fig. 6.12 Four-bit synchronous binary counter

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    y y

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    4-bit up/down up

    pbinary counter down up A0

    down A'0

    down A'0 A'1 up A0 A1

    down A'0 A'1 A'2

    Fig 6 13

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    Fig. 6.13 Four-bit up-down binary counter

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    BCD countersBCD counters

    Si lifi d f i Simplified functions:

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